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Searched refs:bit_idx (Results 1 – 25 of 104) sorted by relevance

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/linux/drivers/clk/imx/
H A Dclk-imx95-blk-ctl.c47 u32 bit_idx; member
68 .bit_idx = 0,
78 .bit_idx = 1,
88 .bit_idx = 2,
108 .bit_idx = 0,
118 .bit_idx = 1,
128 .bit_idx = 4,
138 .bit_idx = 5,
148 .bit_idx = 6,
167 .bit_idx = 0,
[all …]
H A Dclk-gate2.c31 u8 bit_idx; member
47 reg &= ~(gate->cgr_mask << gate->bit_idx); in clk_gate2_do_shared_clks()
49 reg |= (gate->cgr_val & gate->cgr_mask) << gate->bit_idx; in clk_gate2_do_shared_clks()
89 static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx, in clk_gate2_reg_is_enabled() argument
94 if (((val >> bit_idx) & cgr_mask) == cgr_val) in clk_gate2_reg_is_enabled()
108 ret = clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx, in clk_gate2_is_enabled()
138 void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask, in clk_hw_register_gate2() argument
153 gate->bit_idx = bit_idx; in clk_hw_register_gate2()
H A Dclk-lpcg-scu.c37 u8 bit_idx; member
78 reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); in clk_lpcg_scu_enable()
84 reg |= val << clk->bit_idx; in clk_lpcg_scu_enable()
102 reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); in clk_lpcg_scu_disable()
115 void __iomem *reg, u8 bit_idx, bool hw_gate) in __imx_clk_lpcg_scu() argument
127 clk->bit_idx = bit_idx; in __imx_clk_lpcg_scu()
H A Dclk-gate-93.c38 u32 bit_idx; member
58 val &= ~(gate->mask << gate->bit_idx); in imx93_clk_gate_do_hardware()
60 val |= (gate->val & gate->mask) << gate->bit_idx; in imx93_clk_gate_do_hardware()
111 if (((val >> gate->bit_idx) & gate->mask) == gate->val) in imx93_clk_gate_reg_is_enabled()
158 unsigned long flags, void __iomem *reg, u32 bit_idx, u32 val, in imx93_clk_gate() argument
173 gate->bit_idx = bit_idx; in imx93_clk_gate()
H A Dclk-scu.h44 void __iomem *reg, u8 bit_idx, bool hw_gate);
65 void __iomem *reg, u8 bit_idx, bool hw_gate) in imx_clk_lpcg_scu_dev() argument
68 bit_idx, hw_gate); in imx_clk_lpcg_scu_dev()
73 u8 bit_idx, bool hw_gate) in imx_clk_lpcg_scu() argument
76 bit_idx, hw_gate); in imx_clk_lpcg_scu()
/linux/drivers/net/wireless/ath/wcn36xx/
H A Dfirmware.c84 int arr_idx, bit_idx; in wcn36xx_firmware_set_feat_caps() local
92 bit_idx = cap % 32; in wcn36xx_firmware_set_feat_caps()
93 bitmap[arr_idx] |= (1 << bit_idx); in wcn36xx_firmware_set_feat_caps()
99 int arr_idx, bit_idx; in wcn36xx_firmware_get_feat_caps() local
107 bit_idx = cap % 32; in wcn36xx_firmware_get_feat_caps()
109 return (bitmap[arr_idx] & (1 << bit_idx)) ? 1 : 0; in wcn36xx_firmware_get_feat_caps()
115 int arr_idx, bit_idx; in wcn36xx_firmware_clear_feat_caps() local
123 bit_idx = cap % 32; in wcn36xx_firmware_clear_feat_caps()
124 bitmap[arr_idx] &= ~(1 << bit_idx); in wcn36xx_firmware_clear_feat_caps()
/linux/drivers/xen/events/
H A Devents_2l.c170 int word_idx, bit_idx; in evtchn_2l_handle_events() local
180 bit_idx = evtchn % BITS_PER_LONG; in evtchn_2l_handle_events()
181 if (active_evtchns(cpu, s, word_idx) & (1ULL << bit_idx)) in evtchn_2l_handle_events()
207 bit_idx = 0; in evtchn_2l_handle_events()
213 bit_idx = 0; /* usually scan entire word from start */ in evtchn_2l_handle_events()
228 bit_idx = start_bit_idx; in evtchn_2l_handle_events()
235 bits = MASK_LSBS(pending_bits, bit_idx); in evtchn_2l_handle_events()
241 bit_idx = EVTCHN_FIRST_BIT(bits); in evtchn_2l_handle_events()
244 port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx; in evtchn_2l_handle_events()
247 bit_idx = (bit_idx + 1) % BITS_PER_EVTCHN_WORD; in evtchn_2l_handle_events()
[all …]
/linux/drivers/clk/mvebu/
H A Dcp110-system-controller.c113 static unsigned long gate_flags(const u8 bit_idx) in gate_flags() argument
115 switch (bit_idx) { in gate_flags()
135 u8 bit_idx; member
145 BIT(gate->bit_idx), BIT(gate->bit_idx)); in cp110_gate_enable()
155 BIT(gate->bit_idx), 0); in cp110_gate_disable()
165 return val & BIT(gate->bit_idx); in cp110_gate_is_enabled()
176 struct regmap *regmap, u8 bit_idx) in cp110_register_gate() argument
193 init.flags = gate_flags(bit_idx); in cp110_register_gate()
196 gate->bit_idx = bit_idx; in cp110_register_gate()
/linux/drivers/clk/meson/
H A Da1-peripherals.c52 .bit_idx = 0,
67 .bit_idx = 1,
82 .bit_idx = 2,
97 .bit_idx = 3,
112 .bit_idx = 4,
127 .bit_idx = 5,
142 .bit_idx = 6,
157 .bit_idx = 31,
222 .bit_idx = 24,
256 .bit_idx = 30,
[all …]
H A Ds4-peripherals.c77 .bit_idx = 31,
161 .bit_idx = 30,
246 .bit_idx = 29,
292 .bit_idx = 13,
324 .bit_idx = 31,
415 .bit_idx = 30,
431 .bit_idx = 31,
522 .bit_idx = 30,
577 .bit_idx = 8,
593 .bit_idx = 11,
[all …]
H A Daxg.c423 .bit_idx = 27,
450 .bit_idx = 28,
488 .bit_idx = 29,
514 .bit_idx = 30,
542 .bit_idx = 31,
607 .bit_idx = 14,
657 .bit_idx = 14,
712 .bit_idx = 14,
762 .bit_idx = 0,
912 .bit_idx = 4,
[all …]
H A Dmeson8b.c396 .bit_idx = 27,
424 .bit_idx = 28,
452 .bit_idx = 29,
480 .bit_idx = 30,
508 .bit_idx = 31,
572 .bit_idx = 14,
616 .bit_idx = 14,
660 .bit_idx = 14,
718 .bit_idx = 7,
900 .bit_idx = 8,
[all …]
H A Dc3-pll.c40 .bit_idx = 0,
81 .bit_idx = 24,
109 .bit_idx = 4,
137 .bit_idx = 20,
165 .bit_idx = 21,
193 .bit_idx = 22,
221 .bit_idx = 23,
515 .bit_idx = 1,
548 .bit_idx = 0,
578 .bit_idx = 9,
[all …]
H A Dgxbb.c669 .bit_idx = 27,
696 .bit_idx = 28,
734 .bit_idx = 29,
760 .bit_idx = 30,
786 .bit_idx = 31,
871 .bit_idx = 14,
922 .bit_idx = 14,
964 .bit_idx = 14,
1027 .bit_idx = 7,
1078 .bit_idx = 8,
[all …]
H A Da1-pll.c75 .bit_idx = 20,
167 .bit_idx = 21,
205 .bit_idx = 22,
238 .bit_idx = 23,
271 .bit_idx = 24,
H A Ds4-pll.c132 .bit_idx = 24,
158 .bit_idx = 20,
184 .bit_idx = 21,
210 .bit_idx = 22,
236 .bit_idx = 23,
264 .bit_idx = 25,
591 .bit_idx = 31,
644 .bit_idx = 31,
697 .bit_idx = 31,
750 .bit_idx = 31,
H A Dg12a.c330 .bit_idx = 24,
347 .bit_idx = 24,
848 .bit_idx = 24,
885 .bit_idx = 20,
922 .bit_idx = 21,
948 .bit_idx = 22,
974 .bit_idx = 23,
1002 .bit_idx = 25,
1837 .bit_idx = 1,
1866 .bit_idx = 1,
[all …]
H A Dg12a-aoclk.c74 .bit_idx = 14,
101 .bit_idx = 31,
174 .bit_idx = 30,
192 .bit_idx = 31,
265 .bit_idx = 30,
359 .bit_idx = 8,
/linux/drivers/clk/actions/
H A Dowl-gate.c27 reg |= BIT(gate_hw->bit_idx); in owl_gate_set()
29 reg &= ~BIT(gate_hw->bit_idx); in owl_gate_set()
60 reg ^= BIT(gate_hw->bit_idx); in owl_gate_clk_is_enabled()
62 return !!(reg & BIT(gate_hw->bit_idx)); in owl_gate_clk_is_enabled()
/linux/drivers/clk/stm32/
H A Dreset-stm32.c43 line->bit_idx = offset; in stm32_get_reset_line()
70 writel(BIT(ptr_line->bit_idx), addr); in stm32_reset_update()
81 reg |= BIT(ptr_line->bit_idx); in stm32_reset_update()
83 reg &= ~BIT(ptr_line->bit_idx); in stm32_reset_update()
119 return !!(reg & BIT(ptr_line->bit_idx)); in stm32_reset_status()
/linux/drivers/clk/
H A Dclk-loongson2.c41 u8 bit_idx; member
56 u8 bit_idx; member
106 .bit_idx = _midx + 1, \
116 .bit_idx = _bidx, \
127 .bit_idx = _bidx, \
308 if (clk->bit_idx) in loongson2_freqscale_recalc_rate()
309 mode = val & BIT(clk->bit_idx - 1); in loongson2_freqscale_recalc_rate()
344 clk->bit_idx = cld->bit_idx; in loongson2_clk_register()
418 p->bit_idx, 0, in loongson2_clk_probe()
H A Dclk-stm32f4.c59 u8 bit_idx; member
430 u8 bit_idx; member
440 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_recalc_rate()
452 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_determine_rate()
486 unsigned long flags, u8 bit_idx) in clk_register_apb_mul() argument
496 am->bit_idx = bit_idx; in clk_register_apb_mul()
569 u8 bit_idx; member
954 pll->gate.bit_idx = vco->bit_idx; in stm32f4_rcc_register_pll()
960 pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1; in stm32f4_rcc_register_pll()
1102 void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx, in clk_register_rgate() argument
[all …]
H A Dclk-stm32h7.c217 void __iomem *reg, u8 bit_idx, u8 bit_rdy, in clk_register_ready_gate() argument
238 rgate->gate.bit_idx = bit_idx; in clk_register_ready_gate()
253 u8 bit_idx; member
332 static struct clk_gate *_get_cgate(void __iomem *reg, u8 bit_idx, u32 flags, in _get_cgate() argument
342 gate->bit_idx = bit_idx; in _get_cgate()
402 cfg->gate->bit_idx, in get_cfg_composite_div()
593 u8 bit_idx; member
603 .bit_idx = _bit_idx,\
622 u8 bit_idx; member
637 .bit_idx = 24,
[all …]
H A Dclk-ep93xx.c81 u8 bit_idx; member
123 return !!(val & BIT(clk->bit_idx)); in ep93xx_clk_is_enabled()
135 val |= BIT(clk->bit_idx); in ep93xx_clk_enable()
151 val &= ~BIT(clk->bit_idx); in ep93xx_clk_disable()
167 u8 bit_idx) in ep93xx_clk_register_gate() argument
179 clk->bit_idx = bit_idx; in ep93xx_clk_register_gate()
358 u8 bit_idx) in ep93xx_clk_register_ddiv() argument
370 clk->bit_idx = bit_idx; in ep93xx_clk_register_ddiv()
466 clk->bit_idx = enable_bit; in ep93xx_register_div()
/linux/drivers/gpio/
H A Dgpio-graniterapids.c181 unsigned int bit_idx = gpio % GNR_PINS_PER_REG; in gnr_gpio_irq_ack() local
188 reg |= BIT(bit_idx); in gnr_gpio_irq_ack()
196 unsigned int bit_idx = gpio % GNR_PINS_PER_REG; in gnr_gpio_irq_mask_unmask() local
204 reg &= ~BIT(bit_idx); in gnr_gpio_irq_mask_unmask()
206 reg |= BIT(bit_idx); in gnr_gpio_irq_mask_unmask()
292 unsigned int bit_idx; in gnr_gpio_irq() local
302 for_each_set_bit(bit_idx, &pending, GNR_PINS_PER_REG) { in gnr_gpio_irq()
303 unsigned int hwirq = i * GNR_PINS_PER_REG + bit_idx; in gnr_gpio_irq()

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