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Searched refs:bases (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/clk/ux500/
H A Du8500_of_clk.c131 u32 bases[CLKRST_MAX]; in u8500_clk_init() local
144 for (i = 0; i < ARRAY_SIZE(bases); i++) { in u8500_clk_init()
151 bases[i] = r.start; in u8500_clk_init()
303 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
307 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
311 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
315 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
319 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
323 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
327 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
[all …]
/linux/drivers/gpu/host1x/
H A Dsyncpt.c26 struct host1x_syncpt_base *bases = host->bases; in host1x_syncpt_base_request() local
30 if (!bases[i].requested) in host1x_syncpt_base_request()
36 bases[i].requested = true; in host1x_syncpt_base_request()
37 return &bases[i]; in host1x_syncpt_base_request()
282 struct host1x_syncpt_base *bases; in host1x_syncpt_init() local
291 bases = devm_kcalloc(host->dev, host->info->nb_bases, sizeof(*bases), in host1x_syncpt_init()
293 if (!bases) in host1x_syncpt_init()
302 bases[i].id = i; in host1x_syncpt_init()
306 host->bases = bases; in host1x_syncpt_init()
H A Ddev.h138 struct host1x_syncpt_base *bases; member
/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dbase.c33 } bases[] = { in nv50_base_new() local
46 cid = nvif_mclass(&disp->disp->object, bases); in nv50_base_new()
52 return bases[cid].new(drm, head, bases[cid].oclass, pwndw); in nv50_base_new()
/linux/include/linux/
H A Dposix-timers.h99 pct->bases[0].nextevt = U64_MAX; in posix_cputimers_init()
100 pct->bases[1].nextevt = U64_MAX; in posix_cputimers_init()
101 pct->bases[2].nextevt = U64_MAX; in posix_cputimers_init()
109 pct->bases[CPUCLOCK_SCHED].nextevt = runtime; in posix_cputimers_rt_watchdog()
131 .bases = INIT_CPU_TIMERBASES(s.posix_cputimers.bases), \
H A Dposix-timers_types.h57 struct posix_cputimer_base bases[CPUCLOCK_MAX]; member
/linux/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-nvidia.c36 void __iomem *bases[MAX_SMMU_INSTANCES]; member
52 return nvidia_smmu->bases[inst] + (page << smmu->pgshift); in nvidia_smmu_page()
322 nvidia_smmu->bases[0] = smmu->base; in nvidia_smmu_impl_init()
330 nvidia_smmu->bases[i] = devm_ioremap_resource(dev, res); in nvidia_smmu_impl_init()
331 if (IS_ERR(nvidia_smmu->bases[i])) in nvidia_smmu_impl_init()
332 return ERR_CAST(nvidia_smmu->bases[i]); in nvidia_smmu_impl_init()
/linux/kernel/time/
H A Dposix-cpu-timers.c28 pct->bases[CPUCLOCK_PROF].nextevt = cpu_limit * NSEC_PER_SEC; in posix_cputimers_group_init()
154 return !(~pct->bases[CPUCLOCK_PROF].nextevt | in expiry_cache_is_inactive()
155 ~pct->bases[CPUCLOCK_VIRT].nextevt | in expiry_cache_is_inactive()
156 ~pct->bases[CPUCLOCK_SCHED].nextevt); in expiry_cache_is_inactive()
422 return tsk->posix_cputimers.bases + clkidx; in timer_base()
424 return tsk->signal->posix_cputimers.bases + clkidx; in timer_base()
542 cleanup_timerqueue(&pct->bases[CPUCLOCK_PROF].tqhead); in cleanup_timers()
543 cleanup_timerqueue(&pct->bases[CPUCLOCK_VIRT].tqhead); in cleanup_timers()
544 cleanup_timerqueue(&pct->bases[CPUCLOCK_SCHED].tqhead); in cleanup_timers()
829 struct posix_cputimer_base *base = pct->bases; in collect_posix_cputimers()
[all …]
H A Dhrtimer.c959 void clock_was_set(unsigned int bases) in clock_was_set() argument
981 if (update_needs_ipi(cpu_base, bases)) in clock_was_set()
/linux/arch/x86/boot/
H A Dearly_serial_console.c77 static const int bases[] = { 0x3f8, 0x2f8 }; in parse_earlyprintk() local
86 port = bases[idx]; in parse_earlyprintk()
/linux/drivers/gpu/drm/exynos/
H A Dexynos_drm_scaler.c155 static unsigned int bases[] = { in scaler_set_src_base() local
163 scaler_write(src_buf->dma_addr[i], bases[i]); in scaler_set_src_base()
218 static unsigned int bases[] = { in scaler_set_dst_base() local
226 scaler_write(dst_buf->dma_addr[i], bases[i]); in scaler_set_dst_base()
/linux/arch/x86/kernel/
H A Dearly_printk.c162 static const int __initconst bases[] = { 0x3f8, 0x2f8 }; in early_serial_init() local
169 early_serial_base = bases[port]; in early_serial_init()
/linux/drivers/net/wireless/broadcom/b43/
H A Dpio.c82 static const u16 bases[] = { in index_to_pioqueue_base() local
105 B43_WARN_ON(index >= ARRAY_SIZE(bases)); in index_to_pioqueue_base()
106 return bases[index]; in index_to_pioqueue_base()
/linux/drivers/platform/mellanox/
H A DKconfig33 are defined per system type bases and include the registers related
/linux/drivers/gpu/drm/msm/
H A DNOTES58 register interface is same, just different bases.)
/linux/sound/pci/hda/
H A Dhda_proc.c249 static const char * const bases[7] = { in get_jack_location() local
266 return bases[cfg & 0x0f]; in get_jack_location()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_engine_cs.c344 const struct engine_mmio_base *bases) in __engine_mmio_base() argument
349 if (GRAPHICS_VER(i915) >= bases[i].graphics_ver) in __engine_mmio_base()
353 GEM_BUG_ON(!bases[i].base); in __engine_mmio_base()
355 return bases[i].base; in __engine_mmio_base()
/linux/Documentation/timers/
H A Dhighres.rst169 decision is made per timer base and synchronized across per-cpu timer bases in
171 clock event devices for the per-CPU timer bases, but currently only one
/linux/Documentation/driver-api/thermal/
H A Dcpu-idle-cooling.rst89 The implementation of the cooling device bases the number of states on
/linux/Documentation/arch/x86/
H A Dintel_txt.rst68 static root of trust must be used. This bases trust in BIOS
/linux/drivers/media/usb/gspca/
H A DKconfig437 Say Y here if you want support for Xirlink C-It bases cameras.
/linux/Documentation/filesystems/
H A Dvfat.rst204 **nostale_ro**: This option bases the *inode* number and filehandle
/linux/drivers/firmware/cirrus/
H A Dcs_dsp.c2091 __be32 bases[] = { xm_base, xm_base, ym_base, ym_base }; in cs_dsp_halo_create_regions() local
2093 return cs_dsp_create_regions(dsp, id, ver, ARRAY_SIZE(types), types, bases); in cs_dsp_halo_create_regions()
/linux/Documentation/arch/s390/
H A Dcds.rst128 not share interrupt levels (aka. IRQs), as the ISA bus bases on edge triggered