| /linux/drivers/clk/ux500/ |
| H A D | u8500_of_clk.c | 131 u32 bases[CLKRST_MAX]; in u8500_clk_init() local
144 for (i = 0; i < ARRAY_SIZE(bases); i++) { in u8500_clk_init()
151 bases[i] = r.start; in u8500_clk_init()
303 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
307 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
311 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
315 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
319 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
323 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
327 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
[all …]
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| /linux/drivers/iommu/ |
| H A D | rockchip-iommu.c | 111 void __iomem **bases; member
352 writel(command, iommu->bases[i] + RK_MMU_COMMAND); in rk_iommu_command()
372 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova); in rk_iommu_zap_lines()
382 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & in rk_iommu_is_stall_active()
394 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & in rk_iommu_is_paging_enabled()
406 done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0; in rk_iommu_is_reset_done()
431 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_enable_stall()
452 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_disable_stall()
473 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_enable_paging()
494 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_disable_paging()
[all …]
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| /linux/drivers/gpu/drm/nouveau/dispnv50/ |
| H A D | base.c | 33 } bases[] = { in nv50_base_new() local
46 cid = nvif_mclass(&disp->disp->object, bases); in nv50_base_new()
52 return bases[cid].new(drm, head, bases[cid].oclass, pwndw); in nv50_base_new()
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| /linux/include/linux/ |
| H A D | posix-timers.h | 104 pct->bases[0].nextevt = U64_MAX; in posix_cputimers_init()
105 pct->bases[1].nextevt = U64_MAX; in posix_cputimers_init()
106 pct->bases[2].nextevt = U64_MAX; in posix_cputimers_init()
114 pct->bases[CPUCLOCK_SCHED].nextevt = runtime; in posix_cputimers_rt_watchdog()
137 .bases = INIT_CPU_TIMERBASES(s.posix_cputimers.bases), \
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| H A D | posix-timers_types.h | 57 struct posix_cputimer_base bases[CPUCLOCK_MAX]; member
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| /linux/drivers/iommu/arm/arm-smmu/ |
| H A D | arm-smmu-nvidia.c | 36 void __iomem *bases[MAX_SMMU_INSTANCES]; member
52 return nvidia_smmu->bases[inst] + (page << smmu->pgshift); in nvidia_smmu_page()
322 nvidia_smmu->bases[0] = smmu->base; in nvidia_smmu_impl_init()
330 nvidia_smmu->bases[i] = devm_ioremap_resource(dev, res); in nvidia_smmu_impl_init()
331 if (IS_ERR(nvidia_smmu->bases[i])) in nvidia_smmu_impl_init()
332 return ERR_CAST(nvidia_smmu->bases[i]); in nvidia_smmu_impl_init()
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| /linux/arch/x86/boot/ |
| H A D | early_serial_console.c | 77 static const int bases[] = { 0x3f8, 0x2f8 }; in parse_earlyprintk() local
86 port = bases[idx]; in parse_earlyprintk()
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| /linux/drivers/gpu/drm/exynos/ |
| H A D | exynos_drm_scaler.c | 155 static unsigned int bases[] = { in scaler_set_src_base() local
163 scaler_write(src_buf->dma_addr[i], bases[i]); in scaler_set_src_base()
218 static unsigned int bases[] = { in scaler_set_dst_base() local
226 scaler_write(dst_buf->dma_addr[i], bases[i]); in scaler_set_dst_base()
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| /linux/arch/x86/kernel/ |
| H A D | early_printk.c | 171 static const int __initconst bases[] = { 0x3f8, 0x2f8 }; in early_serial_init() local
178 early_serial_base = bases[port]; in early_serial_init()
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| /linux/drivers/net/wireless/broadcom/b43/ |
| H A D | pio.c | 82 static const u16 bases[] = { in index_to_pioqueue_base() local
105 B43_WARN_ON(index >= ARRAY_SIZE(bases)); in index_to_pioqueue_base()
106 return bases[index]; in index_to_pioqueue_base()
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| /linux/kernel/time/ |
| H A D | tick-internal.h | 190 void clock_was_set(unsigned int bases);
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| /linux/drivers/gpu/host1x/ |
| H A D | dev.h | 138 struct host1x_syncpt_base *bases; member
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| /linux/drivers/gpu/drm/msm/ |
| H A D | NOTES | 58 register interface is same, just different bases.)
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| /linux/drivers/platform/mellanox/ |
| H A D | Kconfig | 59 are defined per system type bases and include the registers related
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| /linux/Documentation/timers/ |
| H A D | highres.rst | 169 decision is made per timer base and synchronized across per-cpu timer bases in
171 clock event devices for the per-CPU timer bases, but currently only one
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| /linux/Documentation/driver-api/thermal/ |
| H A D | cpu-idle-cooling.rst | 89 The implementation of the cooling device bases the number of states on
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| /linux/Documentation/arch/x86/ |
| H A D | intel_txt.rst | 68 static root of trust must be used. This bases trust in BIOS
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| /linux/drivers/media/usb/gspca/ |
| H A D | Kconfig | 437 Say Y here if you want support for Xirlink C-It bases cameras.
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| /linux/Documentation/filesystems/ |
| H A D | vfat.rst | 204 **nostale_ro**: This option bases the *inode* number and filehandle
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| /linux/Documentation/admin-guide/ |
| H A D | workload-tracing.rst | 183 line tool for browsing C, C++ or Java code-bases. We can use it to find
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| /linux/Documentation/arch/s390/ |
| H A D | cds.rst | 128 not share interrupt levels (aka. IRQs), as the ISA bus bases on edge triggered
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| /linux/Documentation/filesystems/nfs/ |
| H A D | nfsd-maintainer-entry-profile.rst | 41 Bug reports against upstream Linux code bases are welcome on the
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