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Searched refs:base_reg (Results 1 – 25 of 36) sorted by relevance

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/linux/drivers/accel/habanalabs/goya/
H A Dgoya_coresight.c232 u64 base_reg; in goya_config_stm() local
241 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE; in goya_config_stm()
243 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in goya_config_stm()
251 WREG32(base_reg + 0xE80, 0x80004); in goya_config_stm()
252 WREG32(base_reg + 0xD64, 7); in goya_config_stm()
253 WREG32(base_reg + 0xD60, 0); in goya_config_stm()
254 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in goya_config_stm()
255 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask)); in goya_config_stm()
256 WREG32(base_reg + 0xD60, 1); in goya_config_stm()
257 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask)); in goya_config_stm()
[all …]
/linux/arch/sparc/include/asm/
H A Dwinmacro.h38 #define LOAD_PT_INS(base_reg) \ argument
39 ldd [%base_reg + STACKFRAME_SZ + PT_I0], %i0; \
40 ldd [%base_reg + STACKFRAME_SZ + PT_I2], %i2; \
41 ldd [%base_reg + STACKFRAME_SZ + PT_I4], %i4; \
42 ldd [%base_reg + STACKFRAME_SZ + PT_I6], %i6;
44 #define LOAD_PT_GLOBALS(base_reg) \ argument
45 ld [%base_reg + STACKFRAME_SZ + PT_G1], %g1; \
46 ldd [%base_reg + STACKFRAME_SZ + PT_G2], %g2; \
47 ldd [%base_reg + STACKFRAME_SZ + PT_G4], %g4; \
48 ldd [%base_reg + STACKFRAME_SZ + PT_G6], %g6;
[all …]
/linux/drivers/accel/habanalabs/gaudi/
H A Dgaudi_coresight.c394 u64 base_reg; in gaudi_config_stm() local
403 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE; in gaudi_config_stm()
405 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in gaudi_config_stm()
413 WREG32(base_reg + 0xE80, 0x80004); in gaudi_config_stm()
414 WREG32(base_reg + 0xD64, 7); in gaudi_config_stm()
415 WREG32(base_reg + 0xD60, 0); in gaudi_config_stm()
416 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in gaudi_config_stm()
417 WREG32(base_reg + 0xD60, 1); in gaudi_config_stm()
418 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask)); in gaudi_config_stm()
419 WREG32(base_reg + 0xE70, 0x10); in gaudi_config_stm()
[all …]
/linux/drivers/gpu/drm/imx/dcss/
H A Ddcss-blkctl.c26 void __iomem *base_reg; member
32 dcss_writel(0, blkctl->base_reg + DCSS_BLKCTL_CONTROL0); in dcss_blkctl_cfg()
35 blkctl->base_reg + DCSS_BLKCTL_CONTROL0); in dcss_blkctl_cfg()
38 blkctl->base_reg + DCSS_BLKCTL_RESET_CTRL); in dcss_blkctl_cfg()
49 blkctl->base_reg = devm_ioremap(dcss->dev, blkctl_base, SZ_4K); in dcss_blkctl_init()
50 if (!blkctl->base_reg) { in dcss_blkctl_init()
H A Ddcss-ss.c64 void __iomem *base_reg; member
76 dcss_writel(val, ss->base_reg + ofs); in dcss_ss_write()
94 ss->base_reg = devm_ioremap(ss->dev, ss_base, SZ_4K); in dcss_ss_init()
95 if (!ss->base_reg) { in dcss_ss_init()
109 dcss_writel(0, ss->base_reg + DCSS_SS_SYS_CTRL); in dcss_ss_exit()
172 dcss_writel(0, ss->base_reg + DCSS_SS_SYS_CTRL); in dcss_ss_shutoff()
H A Ddcss-dpr.c93 void __iomem *base_reg; member
138 ch->base_reg = devm_ioremap(dpr->dev, ch->base_ofs, SZ_4K); in dcss_dpr_ch_init_all()
139 if (!ch->base_reg) { in dcss_dpr_ch_init_all()
148 dcss_writel(0xff, ch->base_reg + DCSS_DPR_IRQ_MASK); in dcss_dpr_ch_init_all()
181 dcss_writel(0, ch->base_reg + DCSS_DPR_SYSTEM_CTRL0); in dcss_dpr_exit()
/linux/arch/arm/mach-omap1/
H A Dirq.c58 unsigned long base_reg; member
116 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
117 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
120 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 },
121 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 },
128 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },
129 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd },
130 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff },
131 { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff },
208 irq_banks[i].va = ioremap(irq_banks[i].base_reg, 0xff); in omap1_init_irq()
/linux/sound/soc/codecs/
H A Darizona.h168 #define ARIZONA_MUX_ENUMS(name, base_reg) \ argument
169 static ARIZONA_MUX_ENUM_DECL(name##_enum, base_reg); \
172 #define ARIZONA_MIXER_ENUMS(name, base_reg) \ argument
173 ARIZONA_MUX_ENUMS(name##_in1, base_reg); \
174 ARIZONA_MUX_ENUMS(name##_in2, base_reg + 2); \
175 ARIZONA_MUX_ENUMS(name##_in3, base_reg + 4); \
176 ARIZONA_MUX_ENUMS(name##_in4, base_reg + 6)
178 #define ARIZONA_DSP_AUX_ENUMS(name, base_reg) \ argument
179 ARIZONA_MUX_ENUMS(name##_aux1, base_reg); \
180 ARIZONA_MUX_ENUMS(name##_aux2, base_reg + 8); \
[all …]
H A Dmadera.h215 #define MADERA_MUX_ENUMS(name, base_reg) \ argument
216 static MADERA_MUX_ENUM_DECL(name##_enum, base_reg); \
219 #define MADERA_MIXER_ENUMS(name, base_reg) \ argument
220 MADERA_MUX_ENUMS(name##_in1, base_reg); \
221 MADERA_MUX_ENUMS(name##_in2, base_reg + 2); \
222 MADERA_MUX_ENUMS(name##_in3, base_reg + 4); \
223 MADERA_MUX_ENUMS(name##_in4, base_reg + 6)
225 #define MADERA_DSP_AUX_ENUMS(name, base_reg) \ argument
226 MADERA_MUX_ENUMS(name##_aux1, base_reg); \
227 MADERA_MUX_ENUMS(name##_aux2, base_reg + 8); \
[all …]
H A Dcs48l32.h115 #define CS48L32_MUX_ENUMS(name, base_reg) \ argument
116 static CS48L32_MUX_ENUM_DECL(name##_enum, base_reg); \
119 #define CS48L32_MIXER_ENUMS(name, base_reg) \ argument
120 CS48L32_MUX_ENUMS(name##_in1, base_reg); \
121 CS48L32_MUX_ENUMS(name##_in2, base_reg + 4); \
122 CS48L32_MUX_ENUMS(name##_in3, base_reg + 8); \
123 CS48L32_MUX_ENUMS(name##_in4, base_reg + 12)
/linux/drivers/watchdog/
H A Drdc321x_wdt.c51 int base_reg; member
67 rdc321x_wdt_device.base_reg, &val); in rdc321x_wdt_trigger()
70 rdc321x_wdt_device.base_reg, val); in rdc321x_wdt_trigger()
99 rdc321x_wdt_device.base_reg, RDC_CLS_TMR); in rdc321x_wdt_start()
103 rdc321x_wdt_device.base_reg, in rdc321x_wdt_start()
159 rdc321x_wdt_device.base_reg, &value); in rdc321x_wdt_ioctl()
232 rdc321x_wdt_device.base_reg = r->start; in rdc321x_wdt_probe()
246 rdc321x_wdt_device.base_reg, RDC_WDT_RST); in rdc321x_wdt_probe()
/linux/drivers/clk/
H A Dclk-en7523.c49 u32 base_reg; member
102 .base_reg = REG_GSW_CLK_DIV_SEL,
116 .base_reg = REG_EMI_CLK_DIV_SEL,
130 .base_reg = REG_BUS_CLK_DIV_SEL,
144 .base_reg = REG_SPI_CLK_FREQ_SEL,
159 .base_reg = REG_SPI_CLK_DIV_SEL,
171 .base_reg = REG_NPU_CLK_DIV_SEL,
185 .base_reg = REG_CRYPTO_CLKSRC,
198 .base_reg = REG_GSW_CLK_DIV_SEL,
212 .base_reg = REG_EMI_CLK_DIV_SEL,
[all …]
/linux/sound/soc/cirrus/
H A Dep93xx-i2s.c96 unsigned base_reg; in ep93xx_i2s_enable() local
111 base_reg = EP93XX_I2S_TX0EN; in ep93xx_i2s_enable()
113 base_reg = EP93XX_I2S_RX0EN; in ep93xx_i2s_enable()
114 ep93xx_i2s_write_reg(info, base_reg, 1); in ep93xx_i2s_enable()
126 unsigned base_reg; in ep93xx_i2s_disable() local
135 base_reg = EP93XX_I2S_TX0EN; in ep93xx_i2s_disable()
137 base_reg = EP93XX_I2S_RX0EN; in ep93xx_i2s_disable()
138 ep93xx_i2s_write_reg(info, base_reg, 0); in ep93xx_i2s_disable()
/linux/drivers/bus/
H A Duniphier-system-bus.c118 void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE; in uniphier_system_bus_check_boot_swap() local
121 is_swapped = !(readl(base_reg) & UNIPHIER_SBC_BASE_BE); in uniphier_system_bus_check_boot_swap()
136 void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE; in uniphier_system_bus_set_reg() local
171 writel(val, base_reg + UNIPHIER_SBC_STRIDE * i); in uniphier_system_bus_set_reg()
/linux/drivers/net/dsa/mv88e6xxx/
H A Dglobal2_scratch.c52 int base_reg, unsigned int offset, in mv88e6xxx_g2_scratch_get_bit() argument
55 int reg = base_reg + (offset / 8); in mv88e6xxx_g2_scratch_get_bit()
79 int base_reg, unsigned int offset, in mv88e6xxx_g2_scratch_set_bit() argument
82 int reg = base_reg + (offset / 8); in mv88e6xxx_g2_scratch_set_bit()
/linux/drivers/input/keyboard/
H A Dtm2-touchkey.c38 u8 base_reg; member
58 .base_reg = 0x00,
65 .base_reg = 0x00,
79 .base_reg = 0x00,
107 touchkey->variant->base_reg, data); in tm2_touchkey_led_brightness_set()
/linux/drivers/clk/tegra/
H A Dclk-tegra124.c188 .base_reg = PLLX_BASE,
222 .base_reg = PLLC_BASE,
276 .base_reg = PLLC2_BASE,
298 .base_reg = PLLC3_BASE,
357 .base_reg = PLLC4_BASE,
420 .base_reg = PLLM_BASE,
477 .base_reg = PLLE_BASE,
516 .base_reg = PLLRE_BASE,
553 .base_reg = PLLP_BASE,
582 .base_reg = PLLA_BASE,
[all …]
H A Dclk-tegra210.c785 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) { in tegra210_pllcx_set_defaults()
834 u32 val = readl_relaxed(clk_base + plla->params->base_reg); in tegra210_plla_set_defaults()
871 writel_relaxed(val, clk_base + plla->params->base_reg); in tegra210_plla_set_defaults()
890 if (readl_relaxed(clk_base + plld->params->base_reg) & in tegra210_plld_set_defaults()
940 u32 val = readl_relaxed(clk_base + plldss->params->base_reg); in plldss_defaults()
991 plldss->params->base_reg); in plldss_defaults()
1006 writel_relaxed(val, clk_base + plldss->params->base_reg); in plldss_defaults()
1059 u32 val = readl_relaxed(clk_base + pllre->params->base_reg); in tegra210_pllre_set_defaults()
1103 writel_relaxed(val, clk_base + pllre->params->base_reg); in tegra210_pllre_set_defaults()
1188 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) { in tegra210_pllx_set_defaults()
[all …]
H A Dclk-tegra114.c185 .base_reg = PLLC_BASE,
236 .base_reg = PLLC2_BASE,
258 .base_reg = PLLC3_BASE,
307 .base_reg = PLLM_BASE,
347 .base_reg = PLLP_BASE,
377 .base_reg = PLLA_BASE,
413 .base_reg = PLLD_BASE,
431 .base_reg = PLLD2_BASE,
473 .base_reg = PLLU_BASE,
502 .base_reg = PLLX_BASE,
[all …]
H A Dclk-tegra30.c360 .base_reg = PLLC_BASE,
389 .base_reg = PLLM_BASE,
410 .base_reg = PLLP_BASE,
428 .base_reg = PLLA_BASE,
445 .base_reg = PLLD_BASE,
462 .base_reg = PLLD2_BASE,
479 .base_reg = PLLU_BASE,
497 .base_reg = PLLX_BASE,
516 .base_reg = PLLE_BASE,
H A Dclk-tegra20.c284 .base_reg = PLLC_BASE,
300 .base_reg = PLLM_BASE,
316 .base_reg = PLLP_BASE,
334 .base_reg = PLLA_BASE,
350 .base_reg = PLLD_BASE,
372 .base_reg = PLLU_BASE,
389 .base_reg = PLLX_BASE,
407 .base_reg = PLLE_BASE,
/linux/tools/testing/selftests/powerpc/include/
H A Dbasic_asm.h97 .macro OP_REGS op, reg_width, start_reg, end_reg, base_reg, base_reg_offset=0, skip=0
100 \op i, (\reg_width * (i - \skip) + \base_reg_offset)(\base_reg)
/linux/drivers/base/regmap/
H A Dregmap-debugfs.c140 c->base_reg = i; in regmap_debugfs_get_dump_start()
170 return c->base_reg + (reg_offset * map->reg_stride); in regmap_debugfs_get_dump_start()
205 if (reg < c->base_reg) { in regmap_next_readable_reg()
206 ret = c->base_reg; in regmap_next_readable_reg()
403 c->base_reg, c->max_reg); in regmap_reg_ranges_read_file()
/linux/drivers/clk/visconti/
H A Dpll.h52 unsigned long base_reg; member
/linux/drivers/crypto/intel/keembay/
H A Docs-aes.h49 void __iomem *base_reg; member

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