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Searched refs:aud_1_parents (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt6795-topckgen.c32 static const char * const aud_1_parents[] = { variable
494 TOP_MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0xa0, 24, 2, 31, 0),
H A Dclk-mt8173-topckgen.c307 static const char * const aud_1_parents[] = { variable
583 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),
H A Dclk-mt8186-topckgen.c171 static const char * const aud_1_parents[] = { variable
546 aud_1_parents, 0x0080, 0x0084, 0x0088, 8, 1, 15, 0x0004, 17),
H A Dclk-mt2712.c381 static const char * const aud_1_parents[] = { variable
686 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x0a0, 24, 2, 31),
H A Dclk-mt8183.c442 static const char * const aud_1_parents[] = { variable
553 aud_1_parents, 0xe0, 0xe4, 0xe8, 0, 1, 7, 0x008, 9),
H A Dclk-mt8365.c217 static const char * const aud_1_parents[] = { variable
456 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents,
H A Dclk-mt8192.c423 static const char * const aud_1_parents[] = { variable
659 aud_1_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, 0x008, 21),
H A Dclk-mt8196-topckgen.c473 static const char * const aud_1_parents[] = { variable
813 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_AUD_1, "aud_1", aud_1_parents,