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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-nominal.dtsi7 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
13 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
19 assigned-clock-rates = <0>, <0>,
28 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
29 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
30 assigned-clock-rates = <800000000>;
34 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
36 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
38 assigned-clock-rates = <800000000>, <800000000>;
42 assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
[all …]
H A Dimx8mm-overdrive.dtsi4 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
6 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
7 assigned-clock-rates = <0>, <1000000000>;
11 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
13 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
14 assigned-clock-rates = <0>, <1000000000>;
18 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
22 assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
25 assigned-clock-rates = <750000000>,
H A Dimx8-ss-dma.dtsi34 assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
35 assigned-clock-rates = <60000000>;
52 assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
53 assigned-clock-rates = <60000000>;
70 assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
71 assigned-clock-rates = <60000000>;
88 assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
89 assigned-clock-rates = <60000000>;
102 assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
103 assigned-clock-rates = <80000000>;
[all …]
H A Dimx8mp.dtsi791 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
796 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
801 assigned-clock-rates = <0>, <0>,
852 assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
855 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
858 assigned-clock-rates = <1000000000>,
868 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
870 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
872 assigned-clock-rates = <400000000>,
888 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
[all …]
H A Dimx8mq-mnt-reform2.dts105 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
106 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
107 assigned-clock-rates = <25000000>;
175 assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
176 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
177 /delete-property/assigned-clock-rates;
235 assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
236 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
237 assigned-clock-rates = <25000000>;
274 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
[all …]
H A Dimx8ulp.dtsi303 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
304 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
370 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
371 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
372 assigned-clock-rates = <48000000>;
383 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
384 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
385 assigned-clock-rates = <48000000>;
416 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
417 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
[all …]
H A Dimx8mm-evk.dtsi463 assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
464 assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
465 assigned-clock-rates = <24000000>;
490 assigned-clocks = <&clk IMX8MM_CLK_PDM>;
491 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
492 assigned-clock-rates = <196608000>;
539 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
541 assigned-clock-rates = <10000000>, <250000000>;
542 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
554 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
[all …]
H A Dimx8mm-beacon-baseboard.dtsi200 assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
201 assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
202 assigned-clock-rates = <24000000>;
273 assigned-clocks = <&clk IMX8MM_CLK_PDM>;
274 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
275 assigned-clock-rates = <49152000>;
307 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
309 assigned-clock-rates = <10000000>, <250000000>;
310 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
319 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7ulp.dtsi154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
156 assigned-clock-rates = <24000000>;
166 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
168 assigned-clock-rates = <48000000>;
175 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
263 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
264 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
[all …]
H A Dimx7d-pico.dtsi105 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
107 assigned-clock-parents = <&clks IMX7D_CKIL>;
108 assigned-clock-rates = <0>, <32768>;
129 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
131 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
132 assigned-clock-rates = <0>, <100000000>;
286 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
288 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
289 assigned-clock-rates = <0>, <24576000>;
321 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
[all …]
H A Dimx7d-zii-rpu2.dts189 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
190 assigned-clock-rates = <884736000>;
211 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
213 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
214 assigned-clock-rates = <0>, <100000000>;
294 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
296 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
297 assigned-clock-rates = <0>, <100000000>;
457 assigned-clocks = <&cs2000>;
458 assigned-clock-rates = <24000000>;
[all …]
H A Dimx7d-cl-som-imx7.dts47 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
49 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
50 assigned-clock-rates = <0>, <100000000>;
75 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
77 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
78 assigned-clock-rates = <0>, <100000000>;
197 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
198 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
212 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
213 assigned-clock-rates = <400000000>;
H A Dimx7s-warp.dts75 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
76 assigned-clock-rates = <884736000>;
262 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
264 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
265 assigned-clock-rates = <0>, <36864000>;
272 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
273 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
280 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
281 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
297 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dbrcm,cygnus-audio.txt13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
36 assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
40 assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;
41 assigned-clock-rates = <1769470191>,
/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-clk-ccf.dtsi170 assigned-clocks = <&zynqmp_clk GEM_TSU>;
177 assigned-clocks = <&zynqmp_clk GEM_TSU>;
184 assigned-clocks = <&zynqmp_clk GEM_TSU>;
191 assigned-clocks = <&zynqmp_clk GEM_TSU>;
220 assigned-clocks = <&zynqmp_clk SDIO0_REF>;
225 assigned-clocks = <&zynqmp_clk SDIO1_REF>;
254 assigned-clocks = <&zynqmp_clk UART0_REF>;
259 assigned-clocks = <&zynqmp_clk UART1_REF>;
264 assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
273 assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos4412-odroid-common.dtsi129 assigned-clocks = <&clock CLK_FOUT_EPLL>;
130 assigned-clock-rates = <45158401>;
134 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
140 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
143 assigned-clock-rates = <0>, <0>,
211 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
213 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
214 assigned-clock-rates = <0>, <176000000>;
219 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
221 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721s2-mcu-wakeup.dtsi173 assigned-clocks = <&k3_clks 35 1>;
174 assigned-clock-parents = <&k3_clks 35 2>;
188 assigned-clocks = <&k3_clks 83 1>;
189 assigned-clock-parents = <&k3_clks 83 2>;
202 assigned-clocks = <&k3_clks 84 1>;
203 assigned-clock-parents = <&k3_clks 84 2>;
216 assigned-clocks = <&k3_clks 85 1>;
217 assigned-clock-parents = <&k3_clks 85 2>;
230 assigned-clocks = <&k3_clks 86 1>;
231 assigned-clock-parents = <&k3_clks 86 2>;
[all …]
H A Dk3-j721e-mcu-wakeup.dtsi116 assigned-clocks = <&k3_clks 35 1>;
117 assigned-clock-parents = <&k3_clks 35 2>;
131 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>;
132 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>;
145 assigned-clocks = <&k3_clks 72 1>;
146 assigned-clock-parents = <&k3_clks 72 2>;
159 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>;
160 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>;
173 assigned-clocks = <&k3_clks 74 1>;
174 assigned-clock-parents = <&k3_clks 74 2>;
[all …]
H A Dk3-am62-main.dtsi66 assigned-clocks = <&k3_clks 157 0>;
67 assigned-clock-parents = <&k3_clks 157 8>;
75 assigned-clocks = <&k3_clks 157 10>;
76 assigned-clock-parents = <&k3_clks 157 18>;
269 assigned-clocks = <&k3_clks 36 2>;
270 assigned-clock-parents = <&k3_clks 36 3>;
281 assigned-clocks = <&k3_clks 37 2>;
282 assigned-clock-parents = <&k3_clks 37 3>;
293 assigned-clocks = <&k3_clks 38 2>;
294 assigned-clock-parents = <&k3_clks 38 3>;
[all …]
H A Dk3-j7200-mcu-wakeup.dtsi47 assigned-clocks = <&k3_clks 35 1>;
48 assigned-clock-parents = <&k3_clks 35 2>;
61 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
62 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>;
74 assigned-clocks = <&k3_clks 72 1>;
75 assigned-clock-parents = <&k3_clks 72 2>;
87 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
88 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>;
100 assigned-clocks = <&k3_clks 74 1>;
101 assigned-clock-parents = <&k3_clks 74 2>;
[all …]
H A Dk3-am62a-main.dtsi67 assigned-clocks = <&k3_clks 157 0>;
68 assigned-clock-parents = <&k3_clks 157 8>;
76 assigned-clocks = <&k3_clks 157 10>;
77 assigned-clock-parents = <&k3_clks 157 18>;
300 assigned-clocks = <&k3_clks 36 2>;
301 assigned-clock-parents = <&k3_clks 36 3>;
313 assigned-clocks = <&k3_clks 37 2>;
314 assigned-clock-parents = <&k3_clks 37 3>;
325 assigned-clocks = <&k3_clks 38 2>;
326 assigned-clock-parents = <&k3_clks 38 3>;
[all …]
H A Dk3-am62p-j722s-common-main.dtsi53 assigned-clocks = <&k3_clks 157 0>;
54 assigned-clock-parents = <&k3_clks 157 16>;
62 assigned-clocks = <&k3_clks 157 18>;
63 assigned-clock-parents = <&k3_clks 157 34>;
301 assigned-clocks = <&k3_clks 36 2>;
302 assigned-clock-parents = <&k3_clks 36 3>;
314 assigned-clocks = <&k3_clks 37 2>;
315 assigned-clock-parents = <&k3_clks 37 3>;
326 assigned-clocks = <&k3_clks 38 2>;
327 assigned-clock-parents = <&k3_clks 38 3>;
[all …]
/linux/arch/mips/boot/dts/img/
H A Dpistachio.dtsi51 assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
53 assigned-clock-rates = <100000000>, <33333334>;
69 assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
71 assigned-clock-rates = <100000000>, <33333334>;
87 assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
89 assigned-clock-rates = <100000000>, <33333334>;
105 assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
107 assigned-clock-rates = <100000000>, <33333334>;
141 assigned-clocks = <&clk_core CLK_I2S_DIV>;
142 assigned-clock-rates = <12288000>;
[all …]
/linux/Documentation/process/
H A Dcve.rst8 regards to the kernel project, and CVE numbers were very often assigned
21 A list of all assigned CVEs for the Linux kernel can be found in the
24 assigned CVEs, please `subscribe
32 for CVE number assignments and have CVE numbers automatically assigned
45 should have a CVE assigned to it, please email them at <cve@kernel.org>
53 No CVEs will be automatically assigned for unfixed security issues in
57 have a CVE assigned before an issue is resolved with a commit, please
59 identifier assigned from their batch of reserved identifiers.
61 No CVEs will be assigned for any issue found in a version of the kernel
66 Disputes of assigned CVEs
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3568-fastrhino-r68s.dts30 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
31 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
32 assigned-clock-rates = <0>, <125000000>;
46 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
47 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
48 assigned-clock-rates = <0>, <125000000>;

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