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/linux/Documentation/features/
H A Darch-support.txt2 For generic kernel features that need architecture support, the
8 | ok | # feature supported by the architecture
9 |TODO| # feature not yet supported by the architecture
11 | N/A| # feature doesn't apply to the architecture
/linux/drivers/perf/arm_cspmu/
H A DKconfig10 based on ARM CoreSight PMU architecture. Note that this PMU
11 architecture does not have relationship with the ARM CoreSight
19 (PMU) devices based on ARM CoreSight PMU architecture.
26 (PMU) devices based on ARM CoreSight PMU architecture.
/linux/Documentation/mm/
H A Dmemory-model.rst16 FLATMEM and SPARSEMEM. Each architecture defines what
43 To allocate the `mem_map` array, architecture specific setup code should
48 An architecture may free parts of the `mem_map` array that do not cover the
49 actual physical pages. In such case, the architecture specific
75 `MAX_PHYSMEM_BITS` constants defined by each architecture that
77 physical address that an architecture supports, the
100 The architecture setup code should call sparse_init() to
119 To use vmemmap, an architecture has to reserve a range of virtual
122 the architecture should implement :c:func:`vmemmap_populate` method
124 virtual memory map. If an architecture does not have any special
/linux/arch/mips/jazz/
H A DKconfig9 the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
20 the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
30 the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
/linux/Documentation/arch/x86/x86_64/
H A Dmachinecheck.rst29 For more details about the x86 machine check architecture
30 see the Intel and AMD architecture manuals from their developer websites.
32 For more details about the architecture
H A Dfred.rst10 The FRED architecture defines simple new transitions that change
11 privilege level (ring transitions). The FRED architecture was
23 The new transitions defined by the FRED architecture are FRED event
31 In addition to these transitions, the FRED architecture defines a new
36 Furthermore, the FRED architecture is easy to extend for future CPU
/linux/Documentation/core-api/irq/
H A Dirqflags-tracing.rst15 CONFIG_PROVE_RWSEM_LOCKING will be offered on an architecture - these
21 state changes. But an architecture can be irq-flags-tracing enabled in a
42 - if the architecture has non-maskable interrupts then those need to be
47 implementation in an architecture: lockdep will detect that and will
/linux/drivers/clk/bcm/
H A DKconfig30 based on the ARM architecture
38 based on the MIPS architecture
47 based on the MIPS architecture.
62 based on the iProc architecture
/linux/tools/perf/pmu-events/
H A DREADME19 - To reduce JSON event duplication per architecture, platform JSONs may
21 events", defined in architecture standard JSONs.
22 Architecture standard JSONs must be located in the architecture root
44 - Set of 'PMU events tables' for all known CPUs in the architecture,
61 - A 'mapping table' that maps each CPU of the architecture, to its
86 3. _All_ known CPU tables for architecture are included in the perf
/linux/Documentation/ABI/stable/
H A Dsysfs-devices-system-cpu29 socket number, but the actual value is architecture and platform
36 architecture and platform dependent.
42 architecture and platform dependent.
48 architecture and platform dependent.
54 architecture and platform dependent. it's only used on s390.
60 architecture and platform dependent. it's only used on s390.
H A Dsyscalls7 Note that this interface is different for every architecture
8 that Linux supports. Please see the architecture-specific
/linux/Documentation/usb/
H A Dlinux.inf19 ; Decoration for x86 architecture
23 ; Decoration for x64 architecture
27 ; Decoration for ia64 architecture
/linux/Documentation/arch/arm64/
H A Dlegacy_instructions.rst7 the architecture. The infrastructure code uses undefined instruction
19 have been obsoleted in the architecture, e.g., SWP
39 architecture. Deprecated instructions should default to emulation
H A Damu.rst19 ARMv8.4 CPU architecture.
26 Version 1 of the Activity Monitors architecture implements a counter group
39 The Activity Monitors architecture provides space for up to 16 architected
40 event counters. Future versions of the architecture may use this space to
H A Dtagged-pointers.rst63 Due to architecture limitations, bits 63:60 of the fault address
67 future architecture revisions which may preserve the bits.
76 The architecture prevents the use of a tagged PC, so the upper byte will
/linux/lib/crypto/
H A DKconfig31 Declares whether the architecture provides an arch-specific
47 Declares whether the architecture provides an arch-specific
73 Declares whether the architecture provides an arch-specific
109 Declares whether the architecture provides an arch-specific
/linux/Documentation/arch/arm/samsung/
H A Dgpio.rst8 This outlines the Samsung GPIO implementation and the architecture
25 Pin configuration is specific to the Samsung architecture, with each SoC
/linux/Documentation/arch/powerpc/
H A Delf_hwcaps.rst131 The processor implements the embedded category ("BookE") architecture.
147 The processor supports the v2.05 userlevel architecture. Processors
160 The processor supports the v2.06 userlevel architecture. Processors
182 The processor supports the v2.07 userlevel architecture. Processors
209 The processor supports the v3.0B / v3.0C userlevel architecture. Processors
228 The processor supports the v3.1 userlevel architecture. Processors
H A Dassociativity.rst17 Hypervisor indicates the type/form of associativity used via "ibm,architecture-vec-5 property".
18 Bit 0 of byte 5 in the "ibm,architecture-vec-5" property indicates usage of Form 0 or Form 1.
20 bit 2 of byte 5 in the "ibm,architecture-vec-5" property is used.
57 "ibm,architecture-vec-5" property.
/linux/Documentation/arch/nios2/
H A Dnios2.rst2 Linux on the Nios II architecture
17 Nios II is a 32-bit embedded-processor architecture designed specifically for the
/linux/Documentation/core-api/
H A Dgenericirq.rst22 interrupt subsystem based for their architecture, with the help of the
67 Analysing a couple of architecture's IRQ subsystem implementations
81 and extensible. For example, an (sub)architecture can use a generic
83 (sub)architecture specific 'edge type' implementation.
118 Whenever an interrupt triggers, the low-level architecture code calls
173 The interrupt flow handlers (either pre-defined or architecture
174 specific) are assigned to specific interrupts by the architecture either
321 which have no platform-specific IRQ handling quirks. If an architecture
385 The locking of chip registers is up to the architecture that defines the
/linux/Documentation/timers/
H A Dhighres.rst48 code out of the architecture-specific areas into a generic management
49 framework, as illustrated in figure #3 (OLS slides p. 18). The architecture
76 for various event driven functionalities is hardwired into the architecture
80 architecture. Another implication of the current design is that it is necessary
81 to touch all the architecture-specific implementations in order to provide new
87 to minimize the clock event related architecture dependent code to the pure
93 Clock event devices are registered either by the architecture dependent boot
116 architecture specific timer interrupt handlers and hands the control over the
131 The conversion of an architecture has no functional impact, but allows to
135 adding the kernel/time/Kconfig file to the architecture specific Kconfig and
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dcpus.txt17 Freescale Power Architecture) defines the architecture for Freescale
18 Power CPUs. The EREF defines some architecture categories not defined
/linux/Documentation/scheduler/
H A Dmembarrier.rst14 require each architecture to have a full memory barrier after coming from
24 require each architecture to have a full memory barrier after updating rq->curr,
/linux/Documentation/ABI/testing/
H A Dsysfs-mce12 For more details about the x86 machine check architecture
13 see the Intel and AMD architecture manuals from their
16 For more details about the architecture

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