1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Xilinx AMS driver
4 *
5 * Copyright (C) 2021 Xilinx, Inc.
6 *
7 * Manish Narani <mnarani@xilinx.com>
8 * Rajnikant Bhojani <rajnikant.bhojani@xilinx.com>
9 */
10
11 #include <linux/bits.h>
12 #include <linux/bitfield.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/devm-helpers.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/iopoll.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/overflow.h>
22 #include <linux/platform_device.h>
23 #include <linux/property.h>
24 #include <linux/slab.h>
25
26 #include <linux/iio/events.h>
27 #include <linux/iio/iio.h>
28
29 /* AMS registers definitions */
30 #define AMS_ISR_0 0x010
31 #define AMS_ISR_1 0x014
32 #define AMS_IER_0 0x020
33 #define AMS_IER_1 0x024
34 #define AMS_IDR_0 0x028
35 #define AMS_IDR_1 0x02C
36 #define AMS_PS_CSTS 0x040
37 #define AMS_PL_CSTS 0x044
38
39 #define AMS_VCC_PSPLL0 0x060
40 #define AMS_VCC_PSPLL3 0x06C
41 #define AMS_VCCINT 0x078
42 #define AMS_VCCBRAM 0x07C
43 #define AMS_VCCAUX 0x080
44 #define AMS_PSDDRPLL 0x084
45 #define AMS_PSINTFPDDR 0x09C
46
47 #define AMS_VCC_PSPLL0_CH 48
48 #define AMS_VCC_PSPLL3_CH 51
49 #define AMS_VCCINT_CH 54
50 #define AMS_VCCBRAM_CH 55
51 #define AMS_VCCAUX_CH 56
52 #define AMS_PSDDRPLL_CH 57
53 #define AMS_PSINTFPDDR_CH 63
54
55 #define AMS_REG_CONFIG0 0x100
56 #define AMS_REG_CONFIG1 0x104
57 #define AMS_REG_CONFIG3 0x10C
58 #define AMS_REG_CONFIG4 0x110
59 #define AMS_REG_SEQ_CH0 0x120
60 #define AMS_REG_SEQ_CH1 0x124
61 #define AMS_REG_SEQ_CH2 0x118
62
63 #define AMS_VUSER0_MASK BIT(0)
64 #define AMS_VUSER1_MASK BIT(1)
65 #define AMS_VUSER2_MASK BIT(2)
66 #define AMS_VUSER3_MASK BIT(3)
67
68 #define AMS_TEMP 0x000
69 #define AMS_SUPPLY1 0x004
70 #define AMS_SUPPLY2 0x008
71 #define AMS_VP_VN 0x00C
72 #define AMS_VREFP 0x010
73 #define AMS_VREFN 0x014
74 #define AMS_SUPPLY3 0x018
75 #define AMS_SUPPLY4 0x034
76 #define AMS_SUPPLY5 0x038
77 #define AMS_SUPPLY6 0x03C
78 #define AMS_SUPPLY7 0x200
79 #define AMS_SUPPLY8 0x204
80 #define AMS_SUPPLY9 0x208
81 #define AMS_SUPPLY10 0x20C
82 #define AMS_VCCAMS 0x210
83 #define AMS_TEMP_REMOTE 0x214
84
85 #define AMS_REG_VAUX(x) (0x40 + 4 * (x))
86
87 #define AMS_PS_RESET_VALUE 0xFFFF
88 #define AMS_PL_RESET_VALUE 0xFFFF
89
90 #define AMS_CONF0_CHANNEL_NUM_MASK GENMASK(6, 0)
91
92 #define AMS_CONF1_SEQ_MASK GENMASK(15, 12)
93 #define AMS_CONF1_SEQ_DEFAULT FIELD_PREP(AMS_CONF1_SEQ_MASK, 0)
94 #define AMS_CONF1_SEQ_CONTINUOUS FIELD_PREP(AMS_CONF1_SEQ_MASK, 2)
95 #define AMS_CONF1_SEQ_SINGLE_CHANNEL FIELD_PREP(AMS_CONF1_SEQ_MASK, 3)
96
97 #define AMS_REG_SEQ0_MASK GENMASK(15, 0)
98 #define AMS_REG_SEQ2_MASK GENMASK(21, 16)
99 #define AMS_REG_SEQ1_MASK GENMASK_ULL(37, 22)
100
101 #define AMS_PS_SEQ_MASK GENMASK(21, 0)
102 #define AMS_PL_SEQ_MASK GENMASK_ULL(59, 22)
103
104 #define AMS_ALARM_NONE 0x000 /* not a real offset */
105 #define AMS_ALARM_TEMP 0x140
106 #define AMS_ALARM_SUPPLY1 0x144
107 #define AMS_ALARM_SUPPLY2 0x148
108 #define AMS_ALARM_SUPPLY3 0x160
109 #define AMS_ALARM_SUPPLY4 0x164
110 #define AMS_ALARM_SUPPLY5 0x168
111 #define AMS_ALARM_SUPPLY6 0x16C
112 #define AMS_ALARM_SUPPLY7 0x180
113 #define AMS_ALARM_SUPPLY8 0x184
114 #define AMS_ALARM_SUPPLY9 0x188
115 #define AMS_ALARM_SUPPLY10 0x18C
116 #define AMS_ALARM_VCCAMS 0x190
117 #define AMS_ALARM_TEMP_REMOTE 0x194
118 #define AMS_ALARM_THRESHOLD_OFF_10 0x10
119 #define AMS_ALARM_THRESHOLD_OFF_20 0x20
120
121 #define AMS_ALARM_THR_DIRECT_MASK BIT(0)
122 #define AMS_ALARM_THR_MIN 0x0000
123 #define AMS_ALARM_THR_MAX (BIT(16) - 1)
124
125 #define AMS_ALARM_MASK GENMASK_ULL(63, 0)
126 #define AMS_NO_OF_ALARMS 32
127 #define AMS_PL_ALARM_START 16
128 #define AMS_PL_ALARM_MASK GENMASK(31, 16)
129 #define AMS_ISR0_ALARM_MASK GENMASK(31, 0)
130 #define AMS_ISR1_ALARM_MASK (GENMASK(31, 29) | GENMASK(4, 0))
131 #define AMS_ISR1_EOC_MASK BIT(3)
132 #define AMS_ISR1_INTR_MASK GENMASK_ULL(63, 32)
133 #define AMS_ISR0_ALARM_2_TO_0_MASK GENMASK(2, 0)
134 #define AMS_ISR0_ALARM_6_TO_3_MASK GENMASK(6, 3)
135 #define AMS_ISR0_ALARM_12_TO_7_MASK GENMASK(13, 8)
136 #define AMS_CONF1_ALARM_2_TO_0_MASK GENMASK(3, 1)
137 #define AMS_CONF1_ALARM_6_TO_3_MASK GENMASK(11, 8)
138 #define AMS_CONF1_ALARM_12_TO_7_MASK GENMASK(5, 0)
139 #define AMS_REGCFG1_ALARM_MASK \
140 (AMS_CONF1_ALARM_2_TO_0_MASK | AMS_CONF1_ALARM_6_TO_3_MASK | BIT(0))
141 #define AMS_REGCFG3_ALARM_MASK AMS_CONF1_ALARM_12_TO_7_MASK
142
143 #define AMS_PS_CSTS_PS_READY (BIT(27) | BIT(16))
144 #define AMS_PL_CSTS_ACCESS_MASK BIT(1)
145
146 #define AMS_PL_MAX_FIXED_CHANNEL 10
147 #define AMS_PL_MAX_EXT_CHANNEL 20
148
149 #define AMS_INIT_POLL_TIME_US 200
150 #define AMS_INIT_TIMEOUT_US 10000
151 #define AMS_UNMASK_TIMEOUT_MS 500
152
153 /*
154 * Following scale and offset value is derived from
155 * UG580 (v1.7) December 20, 2016
156 */
157 #define AMS_SUPPLY_SCALE_1VOLT_mV 1000
158 #define AMS_SUPPLY_SCALE_3VOLT_mV 3000
159 #define AMS_SUPPLY_SCALE_6VOLT_mV 6000
160 #define AMS_SUPPLY_SCALE_DIV_BIT 16
161
162 #define AMS_TEMP_SCALE 509314
163 #define AMS_TEMP_SCALE_DIV_BIT 16
164 #define AMS_TEMP_OFFSET -((280230LL << 16) / 509314)
165
166 enum ams_alarm_bit {
167 AMS_ALARM_BIT_TEMP = 0,
168 AMS_ALARM_BIT_SUPPLY1 = 1,
169 AMS_ALARM_BIT_SUPPLY2 = 2,
170 AMS_ALARM_BIT_SUPPLY3 = 3,
171 AMS_ALARM_BIT_SUPPLY4 = 4,
172 AMS_ALARM_BIT_SUPPLY5 = 5,
173 AMS_ALARM_BIT_SUPPLY6 = 6,
174 AMS_ALARM_BIT_RESERVED = 7,
175 AMS_ALARM_BIT_SUPPLY7 = 8,
176 AMS_ALARM_BIT_SUPPLY8 = 9,
177 AMS_ALARM_BIT_SUPPLY9 = 10,
178 AMS_ALARM_BIT_SUPPLY10 = 11,
179 AMS_ALARM_BIT_VCCAMS = 12,
180 AMS_ALARM_BIT_TEMP_REMOTE = 13,
181 };
182
183 enum ams_seq {
184 AMS_SEQ_VCC_PSPLL = 0,
185 AMS_SEQ_VCC_PSBATT = 1,
186 AMS_SEQ_VCCINT = 2,
187 AMS_SEQ_VCCBRAM = 3,
188 AMS_SEQ_VCCAUX = 4,
189 AMS_SEQ_PSDDRPLL = 5,
190 AMS_SEQ_INTDDR = 6,
191 };
192
193 enum ams_ps_pl_seq {
194 AMS_SEQ_CALIB = 0,
195 AMS_SEQ_RSVD_1 = 1,
196 AMS_SEQ_RSVD_2 = 2,
197 AMS_SEQ_TEST = 3,
198 AMS_SEQ_RSVD_4 = 4,
199 AMS_SEQ_SUPPLY4 = 5,
200 AMS_SEQ_SUPPLY5 = 6,
201 AMS_SEQ_SUPPLY6 = 7,
202 AMS_SEQ_TEMP = 8,
203 AMS_SEQ_SUPPLY2 = 9,
204 AMS_SEQ_SUPPLY1 = 10,
205 AMS_SEQ_VP_VN = 11,
206 AMS_SEQ_VREFP = 12,
207 AMS_SEQ_VREFN = 13,
208 AMS_SEQ_SUPPLY3 = 14,
209 AMS_SEQ_CURRENT_MON = 15,
210 AMS_SEQ_SUPPLY7 = 16,
211 AMS_SEQ_SUPPLY8 = 17,
212 AMS_SEQ_SUPPLY9 = 18,
213 AMS_SEQ_SUPPLY10 = 19,
214 AMS_SEQ_VCCAMS = 20,
215 AMS_SEQ_TEMP_REMOTE = 21,
216 AMS_SEQ_MAX = 22
217 };
218
219 #define AMS_PS_SEQ_MAX AMS_SEQ_MAX
220 #define AMS_SEQ(x) (AMS_SEQ_MAX + (x))
221 #define PS_SEQ(x) (x)
222 #define PL_SEQ(x) (AMS_PS_SEQ_MAX + (x))
223 #define AMS_CTRL_SEQ_BASE (AMS_PS_SEQ_MAX * 3)
224
225 #define AMS_CHAN_TEMP(_scan_index, _addr, _name) { \
226 .type = IIO_TEMP, \
227 .indexed = 1, \
228 .address = (_addr), \
229 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
230 BIT(IIO_CHAN_INFO_SCALE) | \
231 BIT(IIO_CHAN_INFO_OFFSET), \
232 .event_spec = ams_temp_events, \
233 .scan_index = _scan_index, \
234 .num_event_specs = ARRAY_SIZE(ams_temp_events), \
235 .datasheet_name = _name, \
236 }
237
238 #define AMS_CHAN_VOLTAGE(_scan_index, _addr, _alarm, _name) { \
239 .type = IIO_VOLTAGE, \
240 .indexed = 1, \
241 .address = (_addr), \
242 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
243 BIT(IIO_CHAN_INFO_SCALE), \
244 .event_spec = (_alarm) ? ams_voltage_events : NULL, \
245 .scan_index = _scan_index, \
246 .num_event_specs = (_alarm) ? ARRAY_SIZE(ams_voltage_events) : 0, \
247 .datasheet_name = _name, \
248 }
249
250 #define AMS_PS_CHAN_TEMP(_scan_index, _addr, _name) \
251 AMS_CHAN_TEMP(PS_SEQ(_scan_index), _addr, _name)
252 #define AMS_PS_CHAN_VOLTAGE(_scan_index, _addr, _name) \
253 AMS_CHAN_VOLTAGE(PS_SEQ(_scan_index), _addr, true, _name)
254
255 #define AMS_PL_CHAN_TEMP(_scan_index, _addr, _name) \
256 AMS_CHAN_TEMP(PL_SEQ(_scan_index), _addr, _name)
257 #define AMS_PL_CHAN_VOLTAGE(_scan_index, _addr, _alarm, _name) \
258 AMS_CHAN_VOLTAGE(PL_SEQ(_scan_index), _addr, _alarm, _name)
259 #define AMS_PL_AUX_CHAN_VOLTAGE(_auxno) \
260 AMS_CHAN_VOLTAGE(PL_SEQ(AMS_SEQ(_auxno)), AMS_REG_VAUX(_auxno), false, \
261 "VAUX" #_auxno)
262 #define AMS_CTRL_CHAN_VOLTAGE(_scan_index, _addr, _name) \
263 AMS_CHAN_VOLTAGE(PL_SEQ(AMS_SEQ(AMS_SEQ(_scan_index))), _addr, false, \
264 _name)
265
266 /**
267 * struct ams - This structure contains necessary state for xilinx-ams to operate
268 * @base: physical base address of device
269 * @ps_base: physical base address of PS device
270 * @pl_base: physical base address of PL device
271 * @clk: clocks associated with the device
272 * @dev: pointer to device struct
273 * @lock: to handle multiple user interaction
274 * @intr_lock: to protect interrupt mask values
275 * @alarm_mask: alarm configuration
276 * @current_masked_alarm: currently masked due to alarm
277 * @intr_mask: interrupt configuration
278 * @ams_unmask_work: re-enables event once the event condition disappears
279 *
280 */
281 struct ams {
282 void __iomem *base;
283 void __iomem *ps_base;
284 void __iomem *pl_base;
285 struct clk *clk;
286 struct device *dev;
287 struct mutex lock;
288 spinlock_t intr_lock;
289 unsigned int alarm_mask;
290 unsigned int current_masked_alarm;
291 u64 intr_mask;
292 struct delayed_work ams_unmask_work;
293 };
294
ams_ps_update_reg(struct ams * ams,unsigned int offset,u32 mask,u32 data)295 static inline void ams_ps_update_reg(struct ams *ams, unsigned int offset,
296 u32 mask, u32 data)
297 {
298 u32 val, regval;
299
300 val = readl(ams->ps_base + offset);
301 regval = (val & ~mask) | (data & mask);
302 writel(regval, ams->ps_base + offset);
303 }
304
ams_pl_update_reg(struct ams * ams,unsigned int offset,u32 mask,u32 data)305 static inline void ams_pl_update_reg(struct ams *ams, unsigned int offset,
306 u32 mask, u32 data)
307 {
308 u32 val, regval;
309
310 val = readl(ams->pl_base + offset);
311 regval = (val & ~mask) | (data & mask);
312 writel(regval, ams->pl_base + offset);
313 }
314
ams_update_intrmask(struct ams * ams,u64 mask,u64 val)315 static void ams_update_intrmask(struct ams *ams, u64 mask, u64 val)
316 {
317 u32 regval;
318
319 ams->intr_mask = (ams->intr_mask & ~mask) | (val & mask);
320
321 regval = ~(ams->intr_mask | ams->current_masked_alarm);
322 writel(regval, ams->base + AMS_IER_0);
323
324 regval = ~(FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask));
325 writel(regval, ams->base + AMS_IER_1);
326
327 regval = ams->intr_mask | ams->current_masked_alarm;
328 writel(regval, ams->base + AMS_IDR_0);
329
330 regval = FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask);
331 writel(regval, ams->base + AMS_IDR_1);
332 }
333
ams_disable_all_alarms(struct ams * ams)334 static void ams_disable_all_alarms(struct ams *ams)
335 {
336 /* disable PS module alarm */
337 if (ams->ps_base) {
338 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK,
339 AMS_REGCFG1_ALARM_MASK);
340 ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK,
341 AMS_REGCFG3_ALARM_MASK);
342 }
343
344 /* disable PL module alarm */
345 if (ams->pl_base) {
346 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK,
347 AMS_REGCFG1_ALARM_MASK);
348 ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK,
349 AMS_REGCFG3_ALARM_MASK);
350 }
351 }
352
ams_update_ps_alarm(struct ams * ams,unsigned long alarm_mask)353 static void ams_update_ps_alarm(struct ams *ams, unsigned long alarm_mask)
354 {
355 u32 cfg;
356 u32 val;
357
358 val = FIELD_GET(AMS_ISR0_ALARM_2_TO_0_MASK, alarm_mask);
359 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_2_TO_0_MASK, val));
360
361 val = FIELD_GET(AMS_ISR0_ALARM_6_TO_3_MASK, alarm_mask);
362 cfg &= ~(FIELD_PREP(AMS_CONF1_ALARM_6_TO_3_MASK, val));
363
364 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg);
365
366 val = FIELD_GET(AMS_ISR0_ALARM_12_TO_7_MASK, alarm_mask);
367 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_12_TO_7_MASK, val));
368 ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg);
369 }
370
ams_update_pl_alarm(struct ams * ams,unsigned long alarm_mask)371 static void ams_update_pl_alarm(struct ams *ams, unsigned long alarm_mask)
372 {
373 unsigned long pl_alarm_mask;
374 u32 cfg;
375 u32 val;
376
377 pl_alarm_mask = FIELD_GET(AMS_PL_ALARM_MASK, alarm_mask);
378
379 val = FIELD_GET(AMS_ISR0_ALARM_2_TO_0_MASK, pl_alarm_mask);
380 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_2_TO_0_MASK, val));
381
382 val = FIELD_GET(AMS_ISR0_ALARM_6_TO_3_MASK, pl_alarm_mask);
383 cfg &= ~(FIELD_PREP(AMS_CONF1_ALARM_6_TO_3_MASK, val));
384
385 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg);
386
387 val = FIELD_GET(AMS_ISR0_ALARM_12_TO_7_MASK, pl_alarm_mask);
388 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_12_TO_7_MASK, val));
389 ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg);
390 }
391
ams_unmask(struct ams * ams)392 static void ams_unmask(struct ams *ams)
393 {
394 unsigned int status, unmask;
395
396 status = readl(ams->base + AMS_ISR_0);
397
398 /* Clear those bits which are not active anymore */
399 unmask = (ams->current_masked_alarm ^ status) & ams->current_masked_alarm;
400
401 /* Clear status of disabled alarm */
402 unmask |= ams->intr_mask;
403
404 ams->current_masked_alarm &= status;
405
406 /* Also clear those which are masked out anyway */
407 ams->current_masked_alarm &= ~ams->intr_mask;
408
409 /* Clear the interrupts before we unmask them */
410 writel(unmask, ams->base + AMS_ISR_0);
411
412 ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK);
413 }
414
ams_update_alarm(struct ams * ams,unsigned long alarm_mask)415 static void ams_update_alarm(struct ams *ams, unsigned long alarm_mask)
416 {
417 unsigned long flags;
418
419 if (ams->ps_base)
420 ams_update_ps_alarm(ams, alarm_mask);
421
422 if (ams->pl_base)
423 ams_update_pl_alarm(ams, alarm_mask);
424
425 spin_lock_irqsave(&ams->intr_lock, flags);
426 ams_update_intrmask(ams, AMS_ISR0_ALARM_MASK, ~alarm_mask);
427 ams_unmask(ams);
428 spin_unlock_irqrestore(&ams->intr_lock, flags);
429 }
430
ams_enable_channel_sequence(struct iio_dev * indio_dev)431 static void ams_enable_channel_sequence(struct iio_dev *indio_dev)
432 {
433 struct ams *ams = iio_priv(indio_dev);
434 unsigned long long scan_mask;
435 int i;
436 u32 regval;
437
438 /*
439 * Enable channel sequence. First 22 bits of scan_mask represent
440 * PS channels, and next remaining bits represent PL channels.
441 */
442
443 /* Run calibration of PS & PL as part of the sequence */
444 scan_mask = BIT(0) | BIT(AMS_PS_SEQ_MAX);
445 for (i = 0; i < indio_dev->num_channels; i++) {
446 const struct iio_chan_spec *chan = &indio_dev->channels[i];
447
448 if (chan->scan_index < AMS_CTRL_SEQ_BASE)
449 scan_mask |= BIT_ULL(chan->scan_index);
450 }
451
452 if (ams->ps_base) {
453 /* put sysmon in a soft reset to change the sequence */
454 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
455 AMS_CONF1_SEQ_DEFAULT);
456
457 /* configure basic channels */
458 regval = FIELD_GET(AMS_REG_SEQ0_MASK, scan_mask);
459 writel(regval, ams->ps_base + AMS_REG_SEQ_CH0);
460
461 regval = FIELD_GET(AMS_REG_SEQ2_MASK, scan_mask);
462 writel(regval, ams->ps_base + AMS_REG_SEQ_CH2);
463
464 /* set continuous sequence mode */
465 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
466 AMS_CONF1_SEQ_CONTINUOUS);
467 }
468
469 if (ams->pl_base) {
470 /* put sysmon in a soft reset to change the sequence */
471 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
472 AMS_CONF1_SEQ_DEFAULT);
473
474 /* configure basic channels */
475 scan_mask = FIELD_GET(AMS_PL_SEQ_MASK, scan_mask);
476
477 regval = FIELD_GET(AMS_REG_SEQ0_MASK, scan_mask);
478 writel(regval, ams->pl_base + AMS_REG_SEQ_CH0);
479
480 regval = FIELD_GET(AMS_REG_SEQ1_MASK, scan_mask);
481 writel(regval, ams->pl_base + AMS_REG_SEQ_CH1);
482
483 regval = FIELD_GET(AMS_REG_SEQ2_MASK, scan_mask);
484 writel(regval, ams->pl_base + AMS_REG_SEQ_CH2);
485
486 /* set continuous sequence mode */
487 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
488 AMS_CONF1_SEQ_CONTINUOUS);
489 }
490 }
491
ams_init_device(struct ams * ams)492 static int ams_init_device(struct ams *ams)
493 {
494 u32 expect = AMS_PS_CSTS_PS_READY;
495 u32 reg, value;
496 int ret;
497
498 /* reset AMS */
499 if (ams->ps_base) {
500 writel(AMS_PS_RESET_VALUE, ams->ps_base + AMS_VP_VN);
501
502 ret = readl_poll_timeout(ams->base + AMS_PS_CSTS, reg, (reg & expect),
503 AMS_INIT_POLL_TIME_US, AMS_INIT_TIMEOUT_US);
504 if (ret)
505 return ret;
506
507 /* put sysmon in a default state */
508 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
509 AMS_CONF1_SEQ_DEFAULT);
510 }
511
512 if (ams->pl_base) {
513 value = readl(ams->base + AMS_PL_CSTS);
514 if (value == 0)
515 return 0;
516
517 writel(AMS_PL_RESET_VALUE, ams->pl_base + AMS_VP_VN);
518
519 /* put sysmon in a default state */
520 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
521 AMS_CONF1_SEQ_DEFAULT);
522 }
523
524 ams_disable_all_alarms(ams);
525
526 /* Disable interrupt */
527 ams_update_intrmask(ams, AMS_ALARM_MASK, AMS_ALARM_MASK);
528
529 /* Clear any pending interrupt */
530 writel(AMS_ISR0_ALARM_MASK, ams->base + AMS_ISR_0);
531 writel(AMS_ISR1_ALARM_MASK, ams->base + AMS_ISR_1);
532
533 return 0;
534 }
535
ams_read_label(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,char * label)536 static int ams_read_label(struct iio_dev *indio_dev,
537 struct iio_chan_spec const *chan, char *label)
538 {
539 return sysfs_emit(label, "%s\n", chan->datasheet_name);
540 }
541
ams_enable_single_channel(struct ams * ams,unsigned int offset)542 static int ams_enable_single_channel(struct ams *ams, unsigned int offset)
543 {
544 u8 channel_num;
545
546 switch (offset) {
547 case AMS_VCC_PSPLL0:
548 channel_num = AMS_VCC_PSPLL0_CH;
549 break;
550 case AMS_VCC_PSPLL3:
551 channel_num = AMS_VCC_PSPLL3_CH;
552 break;
553 case AMS_VCCINT:
554 channel_num = AMS_VCCINT_CH;
555 break;
556 case AMS_VCCBRAM:
557 channel_num = AMS_VCCBRAM_CH;
558 break;
559 case AMS_VCCAUX:
560 channel_num = AMS_VCCAUX_CH;
561 break;
562 case AMS_PSDDRPLL:
563 channel_num = AMS_PSDDRPLL_CH;
564 break;
565 case AMS_PSINTFPDDR:
566 channel_num = AMS_PSINTFPDDR_CH;
567 break;
568 default:
569 return -EINVAL;
570 }
571
572 /* put sysmon in a soft reset to change the sequence */
573 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
574 AMS_CONF1_SEQ_DEFAULT);
575
576 /* write the channel number */
577 ams_ps_update_reg(ams, AMS_REG_CONFIG0, AMS_CONF0_CHANNEL_NUM_MASK,
578 channel_num);
579
580 /* set single channel, sequencer off mode */
581 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
582 AMS_CONF1_SEQ_SINGLE_CHANNEL);
583
584 return 0;
585 }
586
ams_read_vcc_reg(struct ams * ams,unsigned int offset,u32 * data)587 static int ams_read_vcc_reg(struct ams *ams, unsigned int offset, u32 *data)
588 {
589 u32 expect = AMS_ISR1_EOC_MASK;
590 u32 reg;
591 int ret;
592
593 ret = ams_enable_single_channel(ams, offset);
594 if (ret)
595 return ret;
596
597 /* clear end-of-conversion flag, wait for next conversion to complete */
598 writel(expect, ams->base + AMS_ISR_1);
599 ret = readl_poll_timeout(ams->base + AMS_ISR_1, reg, (reg & expect),
600 AMS_INIT_POLL_TIME_US, AMS_INIT_TIMEOUT_US);
601 if (ret)
602 return ret;
603
604 *data = readl(ams->base + offset);
605
606 return 0;
607 }
608
ams_get_ps_scale(int address)609 static int ams_get_ps_scale(int address)
610 {
611 int val;
612
613 switch (address) {
614 case AMS_SUPPLY1:
615 case AMS_SUPPLY2:
616 case AMS_SUPPLY3:
617 case AMS_SUPPLY4:
618 case AMS_SUPPLY9:
619 case AMS_SUPPLY10:
620 case AMS_VCCAMS:
621 val = AMS_SUPPLY_SCALE_3VOLT_mV;
622 break;
623 case AMS_SUPPLY5:
624 case AMS_SUPPLY6:
625 case AMS_SUPPLY7:
626 case AMS_SUPPLY8:
627 val = AMS_SUPPLY_SCALE_6VOLT_mV;
628 break;
629 default:
630 val = AMS_SUPPLY_SCALE_1VOLT_mV;
631 break;
632 }
633
634 return val;
635 }
636
ams_get_pl_scale(struct ams * ams,int address)637 static int ams_get_pl_scale(struct ams *ams, int address)
638 {
639 int val, regval;
640
641 switch (address) {
642 case AMS_SUPPLY1:
643 case AMS_SUPPLY2:
644 case AMS_SUPPLY3:
645 case AMS_SUPPLY4:
646 case AMS_SUPPLY5:
647 case AMS_SUPPLY6:
648 case AMS_VCCAMS:
649 case AMS_VREFP:
650 case AMS_VREFN:
651 val = AMS_SUPPLY_SCALE_3VOLT_mV;
652 break;
653 case AMS_SUPPLY7:
654 regval = readl(ams->pl_base + AMS_REG_CONFIG4);
655 if (FIELD_GET(AMS_VUSER0_MASK, regval))
656 val = AMS_SUPPLY_SCALE_6VOLT_mV;
657 else
658 val = AMS_SUPPLY_SCALE_3VOLT_mV;
659 break;
660 case AMS_SUPPLY8:
661 regval = readl(ams->pl_base + AMS_REG_CONFIG4);
662 if (FIELD_GET(AMS_VUSER1_MASK, regval))
663 val = AMS_SUPPLY_SCALE_6VOLT_mV;
664 else
665 val = AMS_SUPPLY_SCALE_3VOLT_mV;
666 break;
667 case AMS_SUPPLY9:
668 regval = readl(ams->pl_base + AMS_REG_CONFIG4);
669 if (FIELD_GET(AMS_VUSER2_MASK, regval))
670 val = AMS_SUPPLY_SCALE_6VOLT_mV;
671 else
672 val = AMS_SUPPLY_SCALE_3VOLT_mV;
673 break;
674 case AMS_SUPPLY10:
675 regval = readl(ams->pl_base + AMS_REG_CONFIG4);
676 if (FIELD_GET(AMS_VUSER3_MASK, regval))
677 val = AMS_SUPPLY_SCALE_6VOLT_mV;
678 else
679 val = AMS_SUPPLY_SCALE_3VOLT_mV;
680 break;
681 case AMS_VP_VN:
682 case AMS_REG_VAUX(0) ... AMS_REG_VAUX(15):
683 val = AMS_SUPPLY_SCALE_1VOLT_mV;
684 break;
685 default:
686 val = AMS_SUPPLY_SCALE_1VOLT_mV;
687 break;
688 }
689
690 return val;
691 }
692
ams_get_ctrl_scale(int address)693 static int ams_get_ctrl_scale(int address)
694 {
695 int val;
696
697 switch (address) {
698 case AMS_VCC_PSPLL0:
699 case AMS_VCC_PSPLL3:
700 case AMS_VCCINT:
701 case AMS_VCCBRAM:
702 case AMS_VCCAUX:
703 case AMS_PSDDRPLL:
704 case AMS_PSINTFPDDR:
705 val = AMS_SUPPLY_SCALE_3VOLT_mV;
706 break;
707 default:
708 val = AMS_SUPPLY_SCALE_1VOLT_mV;
709 break;
710 }
711
712 return val;
713 }
714
ams_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)715 static int ams_read_raw(struct iio_dev *indio_dev,
716 struct iio_chan_spec const *chan,
717 int *val, int *val2, long mask)
718 {
719 struct ams *ams = iio_priv(indio_dev);
720 int ret;
721
722 switch (mask) {
723 case IIO_CHAN_INFO_RAW: {
724 guard(mutex)(&ams->lock);
725 if (chan->scan_index >= AMS_CTRL_SEQ_BASE) {
726 ret = ams_read_vcc_reg(ams, chan->address, val);
727 if (ret)
728 return ret;
729 ams_enable_channel_sequence(indio_dev);
730 } else if (chan->scan_index >= AMS_PS_SEQ_MAX)
731 *val = readl(ams->pl_base + chan->address);
732 else
733 *val = readl(ams->ps_base + chan->address);
734
735 return IIO_VAL_INT;
736 }
737 case IIO_CHAN_INFO_SCALE:
738 switch (chan->type) {
739 case IIO_VOLTAGE:
740 if (chan->scan_index < AMS_PS_SEQ_MAX)
741 *val = ams_get_ps_scale(chan->address);
742 else if (chan->scan_index >= AMS_PS_SEQ_MAX &&
743 chan->scan_index < AMS_CTRL_SEQ_BASE)
744 *val = ams_get_pl_scale(ams, chan->address);
745 else
746 *val = ams_get_ctrl_scale(chan->address);
747
748 *val2 = AMS_SUPPLY_SCALE_DIV_BIT;
749 return IIO_VAL_FRACTIONAL_LOG2;
750 case IIO_TEMP:
751 *val = AMS_TEMP_SCALE;
752 *val2 = AMS_TEMP_SCALE_DIV_BIT;
753 return IIO_VAL_FRACTIONAL_LOG2;
754 default:
755 return -EINVAL;
756 }
757 case IIO_CHAN_INFO_OFFSET:
758 /* Only the temperature channel has an offset */
759 *val = AMS_TEMP_OFFSET;
760 return IIO_VAL_INT;
761 default:
762 return -EINVAL;
763 }
764 }
765
766 struct ams_alarm_map {
767 enum ams_ps_pl_seq scan_index;
768 unsigned int base_offset;
769 };
770
771 /*
772 * Array index matches enum ams_alarm_bit.
773 * Entries with base_offset == AMS_ALARM_NONE are unused/invalid
774 * (e.g. RESERVED) and must be skipped.
775 */
776 static const struct ams_alarm_map alarm_map[] = {
777 [AMS_ALARM_BIT_TEMP] = { AMS_SEQ_TEMP, AMS_ALARM_TEMP },
778 [AMS_ALARM_BIT_SUPPLY1] = { AMS_SEQ_SUPPLY1, AMS_ALARM_SUPPLY1 },
779 [AMS_ALARM_BIT_SUPPLY2] = { AMS_SEQ_SUPPLY2, AMS_ALARM_SUPPLY2 },
780 [AMS_ALARM_BIT_SUPPLY3] = { AMS_SEQ_SUPPLY3, AMS_ALARM_SUPPLY3 },
781 [AMS_ALARM_BIT_SUPPLY4] = { AMS_SEQ_SUPPLY4, AMS_ALARM_SUPPLY4 },
782 [AMS_ALARM_BIT_SUPPLY5] = { AMS_SEQ_SUPPLY5, AMS_ALARM_SUPPLY5 },
783 [AMS_ALARM_BIT_SUPPLY6] = { AMS_SEQ_SUPPLY6, AMS_ALARM_SUPPLY6 },
784 [AMS_ALARM_BIT_RESERVED] = { 0, AMS_ALARM_NONE },
785 [AMS_ALARM_BIT_SUPPLY7] = { AMS_SEQ_SUPPLY7, AMS_ALARM_SUPPLY7 },
786 [AMS_ALARM_BIT_SUPPLY8] = { AMS_SEQ_SUPPLY8, AMS_ALARM_SUPPLY8 },
787 [AMS_ALARM_BIT_SUPPLY9] = { AMS_SEQ_SUPPLY9, AMS_ALARM_SUPPLY9 },
788 [AMS_ALARM_BIT_SUPPLY10] = { AMS_SEQ_SUPPLY10, AMS_ALARM_SUPPLY10 },
789 [AMS_ALARM_BIT_VCCAMS] = { AMS_SEQ_VCCAMS, AMS_ALARM_VCCAMS },
790 [AMS_ALARM_BIT_TEMP_REMOTE] = { AMS_SEQ_TEMP_REMOTE, AMS_ALARM_TEMP_REMOTE },
791 };
792
ams_scan_index_to_event(int scan_index)793 static int ams_scan_index_to_event(int scan_index)
794 {
795 for (unsigned int i = 0; i < ARRAY_SIZE(alarm_map); i++) {
796 if (alarm_map[i].base_offset == AMS_ALARM_NONE)
797 continue;
798
799 if (alarm_map[i].scan_index == scan_index)
800 return i;
801 }
802
803 return -EINVAL;
804 }
805
ams_get_alarm_offset(int scan_index,enum iio_event_direction dir)806 static int ams_get_alarm_offset(int scan_index, enum iio_event_direction dir)
807 {
808 int offset, event;
809
810 if (scan_index >= AMS_PS_SEQ_MAX)
811 scan_index -= AMS_PS_SEQ_MAX;
812
813 if (dir == IIO_EV_DIR_FALLING) {
814 if (scan_index < AMS_SEQ_SUPPLY7)
815 offset = AMS_ALARM_THRESHOLD_OFF_10;
816 else
817 offset = AMS_ALARM_THRESHOLD_OFF_20;
818 } else {
819 offset = 0;
820 }
821
822 event = ams_scan_index_to_event(scan_index);
823 if (event < 0 || alarm_map[event].base_offset == AMS_ALARM_NONE)
824 return 0;
825
826 return alarm_map[event].base_offset + offset;
827 }
828
ams_event_to_channel(struct iio_dev * dev,u32 event)829 static const struct iio_chan_spec *ams_event_to_channel(struct iio_dev *dev,
830 u32 event)
831 {
832 int scan_index = 0, i;
833
834 if (event >= AMS_PL_ALARM_START) {
835 event -= AMS_PL_ALARM_START;
836 scan_index = AMS_PS_SEQ_MAX;
837 }
838
839 if (event >= ARRAY_SIZE(alarm_map))
840 return NULL;
841
842 if (alarm_map[event].base_offset == AMS_ALARM_NONE)
843 return NULL;
844
845 scan_index += alarm_map[event].scan_index;
846
847 for (i = 0; i < dev->num_channels; i++)
848 if (dev->channels[i].scan_index == scan_index)
849 break;
850
851 if (i == dev->num_channels)
852 return NULL;
853
854 return &dev->channels[i];
855 }
856
ams_get_alarm_mask(int scan_index)857 static int ams_get_alarm_mask(int scan_index)
858 {
859 int bit = 0, event;
860
861 if (scan_index >= AMS_PS_SEQ_MAX) {
862 bit = AMS_PL_ALARM_START;
863 scan_index -= AMS_PS_SEQ_MAX;
864 }
865
866 event = ams_scan_index_to_event(scan_index);
867 if (event < 0)
868 return 0;
869
870 return BIT(event + bit);
871 }
872
ams_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)873 static int ams_read_event_config(struct iio_dev *indio_dev,
874 const struct iio_chan_spec *chan,
875 enum iio_event_type type,
876 enum iio_event_direction dir)
877 {
878 struct ams *ams = iio_priv(indio_dev);
879
880 return !!(ams->alarm_mask & ams_get_alarm_mask(chan->scan_index));
881 }
882
ams_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)883 static int ams_write_event_config(struct iio_dev *indio_dev,
884 const struct iio_chan_spec *chan,
885 enum iio_event_type type,
886 enum iio_event_direction dir,
887 bool state)
888 {
889 struct ams *ams = iio_priv(indio_dev);
890 unsigned int alarm;
891
892 alarm = ams_get_alarm_mask(chan->scan_index);
893
894 guard(mutex)(&ams->lock);
895
896 if (state)
897 ams->alarm_mask |= alarm;
898 else
899 ams->alarm_mask &= ~alarm;
900
901 ams_update_alarm(ams, ams->alarm_mask);
902
903 return 0;
904 }
905
ams_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)906 static int ams_read_event_value(struct iio_dev *indio_dev,
907 const struct iio_chan_spec *chan,
908 enum iio_event_type type,
909 enum iio_event_direction dir,
910 enum iio_event_info info, int *val, int *val2)
911 {
912 struct ams *ams = iio_priv(indio_dev);
913 unsigned int offset = ams_get_alarm_offset(chan->scan_index, dir);
914
915 guard(mutex)(&ams->lock);
916
917 if (chan->scan_index >= AMS_PS_SEQ_MAX)
918 *val = readl(ams->pl_base + offset);
919 else
920 *val = readl(ams->ps_base + offset);
921
922 return IIO_VAL_INT;
923 }
924
ams_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)925 static int ams_write_event_value(struct iio_dev *indio_dev,
926 const struct iio_chan_spec *chan,
927 enum iio_event_type type,
928 enum iio_event_direction dir,
929 enum iio_event_info info, int val, int val2)
930 {
931 struct ams *ams = iio_priv(indio_dev);
932 unsigned int offset;
933
934 guard(mutex)(&ams->lock);
935
936 /* Set temperature channel threshold to direct threshold */
937 if (chan->type == IIO_TEMP) {
938 offset = ams_get_alarm_offset(chan->scan_index, IIO_EV_DIR_FALLING);
939
940 if (chan->scan_index >= AMS_PS_SEQ_MAX)
941 ams_pl_update_reg(ams, offset,
942 AMS_ALARM_THR_DIRECT_MASK,
943 AMS_ALARM_THR_DIRECT_MASK);
944 else
945 ams_ps_update_reg(ams, offset,
946 AMS_ALARM_THR_DIRECT_MASK,
947 AMS_ALARM_THR_DIRECT_MASK);
948 }
949
950 offset = ams_get_alarm_offset(chan->scan_index, dir);
951 if (chan->scan_index >= AMS_PS_SEQ_MAX)
952 writel(val, ams->pl_base + offset);
953 else
954 writel(val, ams->ps_base + offset);
955
956 return 0;
957 }
958
ams_handle_event(struct iio_dev * indio_dev,u32 event)959 static void ams_handle_event(struct iio_dev *indio_dev, u32 event)
960 {
961 const struct iio_chan_spec *chan;
962
963 chan = ams_event_to_channel(indio_dev, event);
964 if (!chan)
965 return;
966
967 if (chan->type == IIO_TEMP) {
968 /*
969 * The temperature channel only supports over-temperature
970 * events.
971 */
972 iio_push_event(indio_dev,
973 IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
974 IIO_EV_TYPE_THRESH,
975 IIO_EV_DIR_RISING),
976 iio_get_time_ns(indio_dev));
977 } else {
978 /*
979 * For other channels we don't know whether it is a upper or
980 * lower threshold event. Userspace will have to check the
981 * channel value if it wants to know.
982 */
983 iio_push_event(indio_dev,
984 IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
985 IIO_EV_TYPE_THRESH,
986 IIO_EV_DIR_EITHER),
987 iio_get_time_ns(indio_dev));
988 }
989 }
990
ams_handle_events(struct iio_dev * indio_dev,unsigned long events)991 static void ams_handle_events(struct iio_dev *indio_dev, unsigned long events)
992 {
993 unsigned int bit;
994
995 for_each_set_bit(bit, &events, AMS_NO_OF_ALARMS)
996 ams_handle_event(indio_dev, bit);
997 }
998
999 /**
1000 * ams_unmask_worker - ams alarm interrupt unmask worker
1001 * @work: work to be done
1002 *
1003 * The ZynqMP threshold interrupts are level sensitive. Since we can't make the
1004 * threshold condition go way from within the interrupt handler, this means as
1005 * soon as a threshold condition is present we would enter the interrupt handler
1006 * again and again. To work around this we mask all active threshold interrupts
1007 * in the interrupt handler and start a timer. In this timer we poll the
1008 * interrupt status and only if the interrupt is inactive we unmask it again.
1009 */
ams_unmask_worker(struct work_struct * work)1010 static void ams_unmask_worker(struct work_struct *work)
1011 {
1012 struct ams *ams = container_of(work, struct ams, ams_unmask_work.work);
1013
1014 spin_lock_irq(&ams->intr_lock);
1015 ams_unmask(ams);
1016 spin_unlock_irq(&ams->intr_lock);
1017
1018 /* If still pending some alarm re-trigger the timer */
1019 if (ams->current_masked_alarm)
1020 schedule_delayed_work(&ams->ams_unmask_work,
1021 msecs_to_jiffies(AMS_UNMASK_TIMEOUT_MS));
1022 }
1023
ams_irq(int irq,void * data)1024 static irqreturn_t ams_irq(int irq, void *data)
1025 {
1026 struct iio_dev *indio_dev = data;
1027 struct ams *ams = iio_priv(indio_dev);
1028 u32 isr0;
1029
1030 spin_lock(&ams->intr_lock);
1031
1032 isr0 = readl(ams->base + AMS_ISR_0);
1033
1034 /* Only process alarms that are not masked */
1035 isr0 &= ~((ams->intr_mask & AMS_ISR0_ALARM_MASK) | ams->current_masked_alarm);
1036 if (!isr0) {
1037 spin_unlock(&ams->intr_lock);
1038 return IRQ_NONE;
1039 }
1040
1041 /* Clear interrupt */
1042 writel(isr0, ams->base + AMS_ISR_0);
1043
1044 /* Mask the alarm interrupts until cleared */
1045 ams->current_masked_alarm |= isr0;
1046 ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK);
1047
1048 ams_handle_events(indio_dev, isr0);
1049
1050 schedule_delayed_work(&ams->ams_unmask_work,
1051 msecs_to_jiffies(AMS_UNMASK_TIMEOUT_MS));
1052
1053 spin_unlock(&ams->intr_lock);
1054
1055 return IRQ_HANDLED;
1056 }
1057
1058 static const struct iio_event_spec ams_temp_events[] = {
1059 {
1060 .type = IIO_EV_TYPE_THRESH,
1061 .dir = IIO_EV_DIR_RISING,
1062 .mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT(IIO_EV_INFO_VALUE),
1063 },
1064 };
1065
1066 static const struct iio_event_spec ams_voltage_events[] = {
1067 {
1068 .type = IIO_EV_TYPE_THRESH,
1069 .dir = IIO_EV_DIR_RISING,
1070 .mask_separate = BIT(IIO_EV_INFO_VALUE),
1071 },
1072 {
1073 .type = IIO_EV_TYPE_THRESH,
1074 .dir = IIO_EV_DIR_FALLING,
1075 .mask_separate = BIT(IIO_EV_INFO_VALUE),
1076 },
1077 {
1078 .type = IIO_EV_TYPE_THRESH,
1079 .dir = IIO_EV_DIR_EITHER,
1080 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1081 },
1082 };
1083
1084 static const struct iio_chan_spec ams_ps_channels[] = {
1085 AMS_PS_CHAN_TEMP(AMS_SEQ_TEMP, AMS_TEMP, "Temp_LPD"),
1086 AMS_PS_CHAN_TEMP(AMS_SEQ_TEMP_REMOTE, AMS_TEMP_REMOTE, "Temp_FPD"),
1087 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY1, AMS_SUPPLY1, "VCC_PSINTLP"),
1088 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY2, AMS_SUPPLY2, "VCC_PSINTFP"),
1089 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY3, AMS_SUPPLY3, "VCC_PSAUX"),
1090 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY4, AMS_SUPPLY4, "VCC_PSDDR"),
1091 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY5, AMS_SUPPLY5, "VCC_PSIO3"),
1092 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY6, AMS_SUPPLY6, "VCC_PSIO0"),
1093 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY7, AMS_SUPPLY7, "VCC_PSIO1"),
1094 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY8, AMS_SUPPLY8, "VCC_PSIO2"),
1095 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY9, AMS_SUPPLY9, "PS_MGTRAVCC"),
1096 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY10, AMS_SUPPLY10, "PS_MGTRAVTT"),
1097 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_VCCAMS, AMS_VCCAMS, "VCC_PSADC"),
1098 };
1099
1100 static const struct iio_chan_spec ams_pl_channels[] = {
1101 AMS_PL_CHAN_TEMP(AMS_SEQ_TEMP, AMS_TEMP, "Temp_PL"),
1102 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY1, AMS_SUPPLY1, true, "VCCINT"),
1103 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY2, AMS_SUPPLY2, true, "VCCAUX"),
1104 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VREFP, AMS_VREFP, false, "VREFP"),
1105 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VREFN, AMS_VREFN, false, "VREFN"),
1106 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY3, AMS_SUPPLY3, true, "VCCBRAM"),
1107 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY4, AMS_SUPPLY4, true, "VCC_PSINTLP"),
1108 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY5, AMS_SUPPLY5, true, "VCC_PSINTFP"),
1109 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY6, AMS_SUPPLY6, true, "VCC_PSAUX"),
1110 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VCCAMS, AMS_VCCAMS, true, "VCCAMS"),
1111 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VP_VN, AMS_VP_VN, false, "VP_VN"),
1112 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY7, AMS_SUPPLY7, true, "VUser0"),
1113 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY8, AMS_SUPPLY8, true, "VUser1"),
1114 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY9, AMS_SUPPLY9, true, "VUser2"),
1115 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY10, AMS_SUPPLY10, true, "VUser3"),
1116 AMS_PL_AUX_CHAN_VOLTAGE(0),
1117 AMS_PL_AUX_CHAN_VOLTAGE(1),
1118 AMS_PL_AUX_CHAN_VOLTAGE(2),
1119 AMS_PL_AUX_CHAN_VOLTAGE(3),
1120 AMS_PL_AUX_CHAN_VOLTAGE(4),
1121 AMS_PL_AUX_CHAN_VOLTAGE(5),
1122 AMS_PL_AUX_CHAN_VOLTAGE(6),
1123 AMS_PL_AUX_CHAN_VOLTAGE(7),
1124 AMS_PL_AUX_CHAN_VOLTAGE(8),
1125 AMS_PL_AUX_CHAN_VOLTAGE(9),
1126 AMS_PL_AUX_CHAN_VOLTAGE(10),
1127 AMS_PL_AUX_CHAN_VOLTAGE(11),
1128 AMS_PL_AUX_CHAN_VOLTAGE(12),
1129 AMS_PL_AUX_CHAN_VOLTAGE(13),
1130 AMS_PL_AUX_CHAN_VOLTAGE(14),
1131 AMS_PL_AUX_CHAN_VOLTAGE(15),
1132 };
1133
1134 static const struct iio_chan_spec ams_ctrl_channels[] = {
1135 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCC_PSPLL, AMS_VCC_PSPLL0, "VCC_PSPLL"),
1136 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCC_PSBATT, AMS_VCC_PSPLL3, "VCC_PSBATT"),
1137 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCINT, AMS_VCCINT, "VCCINT"),
1138 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCBRAM, AMS_VCCBRAM, "VCCBRAM"),
1139 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCAUX, AMS_VCCAUX, "VCCAUX"),
1140 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_PSDDRPLL, AMS_PSDDRPLL, "VCC_PSDDR_PLL"),
1141 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_INTDDR, AMS_PSINTFPDDR, "VCC_PSINTFP_DDR"),
1142 };
1143
ams_get_ext_chan(struct fwnode_handle * chan_node,struct iio_chan_spec * channels,int num_channels)1144 static int ams_get_ext_chan(struct fwnode_handle *chan_node,
1145 struct iio_chan_spec *channels, int num_channels)
1146 {
1147 struct iio_chan_spec *chan;
1148 struct fwnode_handle *child;
1149 unsigned int reg, ext_chan;
1150 int ret;
1151
1152 fwnode_for_each_child_node(chan_node, child) {
1153 ret = fwnode_property_read_u32(child, "reg", ®);
1154 if (ret || reg > AMS_PL_MAX_EXT_CHANNEL + 30)
1155 continue;
1156
1157 chan = &channels[num_channels];
1158 ext_chan = reg + AMS_PL_MAX_FIXED_CHANNEL - 30;
1159 memcpy(chan, &ams_pl_channels[ext_chan], sizeof(*channels));
1160
1161 if (fwnode_property_read_bool(child, "xlnx,bipolar"))
1162 chan->scan_type.sign = 's';
1163
1164 num_channels++;
1165 }
1166
1167 return num_channels;
1168 }
1169
ams_iounmap_ps(void * data)1170 static void ams_iounmap_ps(void *data)
1171 {
1172 struct ams *ams = data;
1173
1174 iounmap(ams->ps_base);
1175 }
1176
ams_iounmap_pl(void * data)1177 static void ams_iounmap_pl(void *data)
1178 {
1179 struct ams *ams = data;
1180
1181 iounmap(ams->pl_base);
1182 }
1183
ams_init_module(struct iio_dev * indio_dev,struct fwnode_handle * fwnode,struct iio_chan_spec * channels)1184 static int ams_init_module(struct iio_dev *indio_dev,
1185 struct fwnode_handle *fwnode,
1186 struct iio_chan_spec *channels)
1187 {
1188 struct device *dev = indio_dev->dev.parent;
1189 struct ams *ams = iio_priv(indio_dev);
1190 int num_channels = 0;
1191 int ret;
1192
1193 if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-ps")) {
1194 ams->ps_base = fwnode_iomap(fwnode, 0);
1195 if (!ams->ps_base)
1196 return -ENXIO;
1197 ret = devm_add_action_or_reset(dev, ams_iounmap_ps, ams);
1198 if (ret < 0)
1199 return ret;
1200
1201 /* add PS channels to iio device channels */
1202 memcpy(channels, ams_ps_channels, sizeof(ams_ps_channels));
1203 num_channels = ARRAY_SIZE(ams_ps_channels);
1204 } else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-pl")) {
1205 ams->pl_base = fwnode_iomap(fwnode, 0);
1206 if (!ams->pl_base)
1207 return -ENXIO;
1208
1209 ret = devm_add_action_or_reset(dev, ams_iounmap_pl, ams);
1210 if (ret < 0)
1211 return ret;
1212
1213 /* Copy only first 10 fix channels */
1214 memcpy(channels, ams_pl_channels, AMS_PL_MAX_FIXED_CHANNEL * sizeof(*channels));
1215 num_channels += AMS_PL_MAX_FIXED_CHANNEL;
1216 num_channels = ams_get_ext_chan(fwnode, channels,
1217 num_channels);
1218 } else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams")) {
1219 /* add AMS channels to iio device channels */
1220 memcpy(channels, ams_ctrl_channels, sizeof(ams_ctrl_channels));
1221 num_channels += ARRAY_SIZE(ams_ctrl_channels);
1222 } else {
1223 return -EINVAL;
1224 }
1225
1226 return num_channels;
1227 }
1228
ams_parse_firmware(struct iio_dev * indio_dev)1229 static int ams_parse_firmware(struct iio_dev *indio_dev)
1230 {
1231 struct ams *ams = iio_priv(indio_dev);
1232 struct iio_chan_spec *ams_channels, *dev_channels;
1233 struct device *dev = indio_dev->dev.parent;
1234 struct fwnode_handle *fwnode = dev_fwnode(dev);
1235 size_t ams_size;
1236 int ret, ch_cnt = 0, i, rising_off, falling_off;
1237 unsigned int num_channels = 0;
1238
1239 ams_size = ARRAY_SIZE(ams_ps_channels) + ARRAY_SIZE(ams_pl_channels) +
1240 ARRAY_SIZE(ams_ctrl_channels);
1241
1242 /* Initialize buffer for channel specification */
1243 ams_channels = devm_kcalloc(dev, ams_size, sizeof(*ams_channels), GFP_KERNEL);
1244 if (!ams_channels)
1245 return -ENOMEM;
1246
1247 if (fwnode_device_is_available(fwnode)) {
1248 ret = ams_init_module(indio_dev, fwnode, ams_channels);
1249 if (ret < 0)
1250 return ret;
1251
1252 num_channels += ret;
1253 }
1254
1255 device_for_each_child_node_scoped(dev, child) {
1256 ret = ams_init_module(indio_dev, child, ams_channels + num_channels);
1257 if (ret < 0)
1258 return ret;
1259
1260 num_channels += ret;
1261 }
1262
1263 for (i = 0; i < num_channels; i++) {
1264 ams_channels[i].channel = ch_cnt++;
1265
1266 if (ams_channels[i].scan_index < AMS_CTRL_SEQ_BASE) {
1267 /* set threshold to max and min for each channel */
1268 falling_off =
1269 ams_get_alarm_offset(ams_channels[i].scan_index,
1270 IIO_EV_DIR_FALLING);
1271 rising_off =
1272 ams_get_alarm_offset(ams_channels[i].scan_index,
1273 IIO_EV_DIR_RISING);
1274 if (ams_channels[i].scan_index >= AMS_PS_SEQ_MAX) {
1275 writel(AMS_ALARM_THR_MIN,
1276 ams->pl_base + falling_off);
1277 writel(AMS_ALARM_THR_MAX,
1278 ams->pl_base + rising_off);
1279 } else {
1280 writel(AMS_ALARM_THR_MIN,
1281 ams->ps_base + falling_off);
1282 writel(AMS_ALARM_THR_MAX,
1283 ams->ps_base + rising_off);
1284 }
1285 }
1286 }
1287
1288 dev_channels = devm_krealloc_array(dev, ams_channels, num_channels,
1289 sizeof(*dev_channels), GFP_KERNEL);
1290 if (!dev_channels)
1291 return -ENOMEM;
1292
1293 indio_dev->channels = dev_channels;
1294 indio_dev->num_channels = num_channels;
1295
1296 return 0;
1297 }
1298
1299 static const struct iio_info iio_ams_info = {
1300 .read_label = ams_read_label,
1301 .read_raw = &ams_read_raw,
1302 .read_event_config = &ams_read_event_config,
1303 .write_event_config = &ams_write_event_config,
1304 .read_event_value = &ams_read_event_value,
1305 .write_event_value = &ams_write_event_value,
1306 };
1307
1308 static const struct of_device_id ams_of_match_table[] = {
1309 { .compatible = "xlnx,zynqmp-ams" },
1310 { }
1311 };
1312 MODULE_DEVICE_TABLE(of, ams_of_match_table);
1313
ams_probe(struct platform_device * pdev)1314 static int ams_probe(struct platform_device *pdev)
1315 {
1316 struct iio_dev *indio_dev;
1317 struct ams *ams;
1318 int ret;
1319 int irq;
1320
1321 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*ams));
1322 if (!indio_dev)
1323 return -ENOMEM;
1324
1325 ams = iio_priv(indio_dev);
1326 mutex_init(&ams->lock);
1327 spin_lock_init(&ams->intr_lock);
1328
1329 indio_dev->name = "xilinx-ams";
1330
1331 indio_dev->info = &iio_ams_info;
1332 indio_dev->modes = INDIO_DIRECT_MODE;
1333
1334 ams->base = devm_platform_ioremap_resource(pdev, 0);
1335 if (IS_ERR(ams->base))
1336 return PTR_ERR(ams->base);
1337
1338 ams->clk = devm_clk_get_enabled(&pdev->dev, NULL);
1339 if (IS_ERR(ams->clk))
1340 return PTR_ERR(ams->clk);
1341
1342 ret = devm_delayed_work_autocancel(&pdev->dev, &ams->ams_unmask_work,
1343 ams_unmask_worker);
1344 if (ret < 0)
1345 return ret;
1346
1347 ret = ams_parse_firmware(indio_dev);
1348 if (ret)
1349 return dev_err_probe(&pdev->dev, ret, "failure in parsing DT\n");
1350
1351 ret = ams_init_device(ams);
1352 if (ret)
1353 return dev_err_probe(&pdev->dev, ret, "failed to initialize AMS\n");
1354
1355 ams_enable_channel_sequence(indio_dev);
1356
1357 irq = platform_get_irq(pdev, 0);
1358 if (irq < 0)
1359 return irq;
1360
1361 ret = devm_request_irq(&pdev->dev, irq, &ams_irq, 0, "ams-irq",
1362 indio_dev);
1363 if (ret < 0)
1364 return dev_err_probe(&pdev->dev, ret, "failed to register interrupt\n");
1365
1366 platform_set_drvdata(pdev, indio_dev);
1367
1368 return devm_iio_device_register(&pdev->dev, indio_dev);
1369 }
1370
ams_suspend(struct device * dev)1371 static int ams_suspend(struct device *dev)
1372 {
1373 struct ams *ams = iio_priv(dev_get_drvdata(dev));
1374
1375 clk_disable_unprepare(ams->clk);
1376
1377 return 0;
1378 }
1379
ams_resume(struct device * dev)1380 static int ams_resume(struct device *dev)
1381 {
1382 struct ams *ams = iio_priv(dev_get_drvdata(dev));
1383
1384 return clk_prepare_enable(ams->clk);
1385 }
1386
1387 static DEFINE_SIMPLE_DEV_PM_OPS(ams_pm_ops, ams_suspend, ams_resume);
1388
1389 static struct platform_driver ams_driver = {
1390 .probe = ams_probe,
1391 .driver = {
1392 .name = "xilinx-ams",
1393 .pm = pm_sleep_ptr(&ams_pm_ops),
1394 .of_match_table = ams_of_match_table,
1395 },
1396 };
1397 module_platform_driver(ams_driver);
1398
1399 MODULE_DESCRIPTION("Xilinx AMS driver");
1400 MODULE_LICENSE("GPL v2");
1401 MODULE_AUTHOR("Xilinx, Inc.");
1402