1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/ktime.h>
29 #include <linux/module.h>
30 #include <linux/pagemap.h>
31 #include <linux/pci.h>
32 #include <linux/dma-buf.h>
33 #include <linux/dma-fence-unwrap.h>
34 #include <linux/uaccess.h>
35
36 #include <drm/amdgpu_drm.h>
37 #include <drm/drm_drv.h>
38 #include <drm/drm_exec.h>
39 #include <drm/drm_gem_ttm_helper.h>
40 #include <drm/ttm/ttm_tt.h>
41 #include <drm/drm_syncobj.h>
42
43 #include "amdgpu.h"
44 #include "amdgpu_display.h"
45 #include "amdgpu_dma_buf.h"
46 #include "amdgpu_hmm.h"
47 #include "amdgpu_xgmi.h"
48 #include "amdgpu_vm.h"
49
50 static int
amdgpu_gem_add_input_fence(struct drm_file * filp,uint64_t syncobj_handles_array,uint32_t num_syncobj_handles)51 amdgpu_gem_add_input_fence(struct drm_file *filp,
52 uint64_t syncobj_handles_array,
53 uint32_t num_syncobj_handles)
54 {
55 struct dma_fence *fence;
56 uint32_t *syncobj_handles;
57 int ret, i;
58
59 if (!num_syncobj_handles)
60 return 0;
61
62 syncobj_handles = memdup_user(u64_to_user_ptr(syncobj_handles_array),
63 size_mul(sizeof(uint32_t), num_syncobj_handles));
64 if (IS_ERR(syncobj_handles))
65 return PTR_ERR(syncobj_handles);
66
67 for (i = 0; i < num_syncobj_handles; i++) {
68
69 if (!syncobj_handles[i]) {
70 ret = -EINVAL;
71 goto free_memdup;
72 }
73
74 ret = drm_syncobj_find_fence(filp, syncobj_handles[i], 0, 0, &fence);
75 if (ret)
76 goto free_memdup;
77
78 dma_fence_wait(fence, false);
79
80 /* TODO: optimize async handling */
81 dma_fence_put(fence);
82 }
83
84 free_memdup:
85 kfree(syncobj_handles);
86 return ret;
87 }
88
89 static int
amdgpu_gem_update_timeline_node(struct drm_file * filp,uint32_t syncobj_handle,uint64_t point,struct drm_syncobj ** syncobj,struct dma_fence_chain ** chain)90 amdgpu_gem_update_timeline_node(struct drm_file *filp,
91 uint32_t syncobj_handle,
92 uint64_t point,
93 struct drm_syncobj **syncobj,
94 struct dma_fence_chain **chain)
95 {
96 if (!syncobj_handle)
97 return 0;
98
99 /* Find the sync object */
100 *syncobj = drm_syncobj_find(filp, syncobj_handle);
101 if (!*syncobj)
102 return -ENOENT;
103
104 if (!point)
105 return 0;
106
107 /* Allocate the chain node */
108 *chain = dma_fence_chain_alloc();
109 if (!*chain) {
110 drm_syncobj_put(*syncobj);
111 *syncobj = NULL;
112 return -ENOMEM;
113 }
114
115 return 0;
116 }
117
amdgpu_gem_fault(struct vm_fault * vmf)118 static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf)
119 {
120 struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
121 struct drm_device *ddev = bo->base.dev;
122 vm_fault_t ret;
123 int idx;
124
125 ret = ttm_bo_vm_reserve(bo, vmf);
126 if (ret)
127 return ret;
128
129 if (drm_dev_enter(ddev, &idx)) {
130 ret = amdgpu_bo_fault_reserve_notify(bo);
131 if (ret) {
132 drm_dev_exit(idx);
133 goto unlock;
134 }
135
136 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
137 TTM_BO_VM_NUM_PREFAULT);
138
139 drm_dev_exit(idx);
140 } else {
141 ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot);
142 }
143 if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
144 return ret;
145
146 unlock:
147 dma_resv_unlock(bo->base.resv);
148 return ret;
149 }
150
151 static const struct vm_operations_struct amdgpu_gem_vm_ops = {
152 .fault = amdgpu_gem_fault,
153 .open = ttm_bo_vm_open,
154 .close = ttm_bo_vm_close,
155 .access = ttm_bo_vm_access
156 };
157
amdgpu_gem_object_free(struct drm_gem_object * gobj)158 static void amdgpu_gem_object_free(struct drm_gem_object *gobj)
159 {
160 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(gobj);
161
162 amdgpu_hmm_unregister(aobj);
163 ttm_bo_fini(&aobj->tbo);
164 }
165
amdgpu_gem_object_create(struct amdgpu_device * adev,unsigned long size,int alignment,u32 initial_domain,u64 flags,enum ttm_bo_type type,struct dma_resv * resv,struct drm_gem_object ** obj,int8_t xcp_id_plus1)166 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
167 int alignment, u32 initial_domain,
168 u64 flags, enum ttm_bo_type type,
169 struct dma_resv *resv,
170 struct drm_gem_object **obj, int8_t xcp_id_plus1)
171 {
172 struct amdgpu_bo *bo;
173 struct amdgpu_bo_user *ubo;
174 struct amdgpu_bo_param bp;
175 int r;
176
177 memset(&bp, 0, sizeof(bp));
178 *obj = NULL;
179 flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
180
181 bp.size = size;
182 bp.byte_align = alignment;
183 bp.type = type;
184 bp.resv = resv;
185 bp.preferred_domain = initial_domain;
186 bp.flags = flags;
187 bp.domain = initial_domain;
188 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
189 bp.xcp_id_plus1 = xcp_id_plus1;
190
191 r = amdgpu_bo_create_user(adev, &bp, &ubo);
192 if (r)
193 return r;
194
195 bo = &ubo->bo;
196 *obj = &bo->tbo.base;
197
198 return 0;
199 }
200
amdgpu_gem_force_release(struct amdgpu_device * adev)201 void amdgpu_gem_force_release(struct amdgpu_device *adev)
202 {
203 struct drm_device *ddev = adev_to_drm(adev);
204 struct drm_file *file;
205
206 mutex_lock(&ddev->filelist_mutex);
207
208 list_for_each_entry(file, &ddev->filelist, lhead) {
209 struct drm_gem_object *gobj;
210 int handle;
211
212 WARN_ONCE(1, "Still active user space clients!\n");
213 spin_lock(&file->table_lock);
214 idr_for_each_entry(&file->object_idr, gobj, handle) {
215 WARN_ONCE(1, "And also active allocations!\n");
216 drm_gem_object_put(gobj);
217 }
218 idr_destroy(&file->object_idr);
219 spin_unlock(&file->table_lock);
220 }
221
222 mutex_unlock(&ddev->filelist_mutex);
223 }
224
225 /*
226 * Call from drm_gem_handle_create which appear in both new and open ioctl
227 * case.
228 */
amdgpu_gem_object_open(struct drm_gem_object * obj,struct drm_file * file_priv)229 static int amdgpu_gem_object_open(struct drm_gem_object *obj,
230 struct drm_file *file_priv)
231 {
232 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
233 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
234 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
235 struct amdgpu_vm *vm = &fpriv->vm;
236 struct amdgpu_bo_va *bo_va;
237 struct mm_struct *mm;
238 struct drm_exec exec;
239 int r;
240
241 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
242 if (mm && mm != current->mm)
243 return -EPERM;
244
245 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
246 !amdgpu_vm_is_bo_always_valid(vm, abo))
247 return -EPERM;
248
249 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
250 drm_exec_until_all_locked(&exec) {
251 r = drm_exec_prepare_obj(&exec, &abo->tbo.base, 1);
252 drm_exec_retry_on_contention(&exec);
253 if (unlikely(r))
254 goto out_unlock;
255
256 r = amdgpu_vm_lock_pd(vm, &exec, 0);
257 drm_exec_retry_on_contention(&exec);
258 if (unlikely(r))
259 goto out_unlock;
260 }
261
262 amdgpu_vm_bo_update_shared(abo);
263 bo_va = amdgpu_vm_bo_find(vm, abo);
264 if (!bo_va) {
265 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
266 r = amdgpu_evf_mgr_attach_fence(&fpriv->evf_mgr, abo);
267 if (r)
268 goto out_unlock;
269 } else {
270 ++bo_va->ref_count;
271 }
272
273 drm_exec_fini(&exec);
274
275 /* Validate and add eviction fence to DMABuf imports with dynamic
276 * attachment in compute VMs. Re-validation will be done by
277 * amdgpu_vm_validate. Fences are on the reservation shared with the
278 * export, which is currently required to be validated and fenced
279 * already by amdgpu_amdkfd_gpuvm_restore_process_bos.
280 *
281 * Nested locking below for the case that a GEM object is opened in
282 * kfd_mem_export_dmabuf. Since the lock below is only taken for imports,
283 * but not for export, this is a different lock class that cannot lead to
284 * circular lock dependencies.
285 */
286 if (!vm->is_compute_context || !vm->process_info)
287 return 0;
288 if (!drm_gem_is_imported(obj) ||
289 !dma_buf_is_dynamic(obj->import_attach->dmabuf))
290 return 0;
291 mutex_lock_nested(&vm->process_info->lock, 1);
292 if (!WARN_ON(!vm->process_info->eviction_fence)) {
293 r = amdgpu_amdkfd_bo_validate_and_fence(abo, AMDGPU_GEM_DOMAIN_GTT,
294 &vm->process_info->eviction_fence->base);
295 if (r) {
296 struct amdgpu_task_info *ti = amdgpu_vm_get_task_info_vm(vm);
297
298 dev_warn(adev->dev, "validate_and_fence failed: %d\n", r);
299 if (ti) {
300 dev_warn(adev->dev, "pid %d\n", ti->task.pid);
301 amdgpu_vm_put_task_info(ti);
302 }
303 }
304 }
305 mutex_unlock(&vm->process_info->lock);
306 return r;
307
308 out_unlock:
309 drm_exec_fini(&exec);
310 return r;
311 }
312
amdgpu_gem_object_close(struct drm_gem_object * obj,struct drm_file * file_priv)313 static void amdgpu_gem_object_close(struct drm_gem_object *obj,
314 struct drm_file *file_priv)
315 {
316 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
317 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
318 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
319 struct amdgpu_vm *vm = &fpriv->vm;
320
321 struct dma_fence *fence = NULL;
322 struct amdgpu_bo_va *bo_va;
323 struct drm_exec exec;
324 long r;
325
326 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
327 drm_exec_until_all_locked(&exec) {
328 r = drm_exec_prepare_obj(&exec, &bo->tbo.base, 1);
329 drm_exec_retry_on_contention(&exec);
330 if (unlikely(r))
331 goto out_unlock;
332
333 r = amdgpu_vm_lock_pd(vm, &exec, 0);
334 drm_exec_retry_on_contention(&exec);
335 if (unlikely(r))
336 goto out_unlock;
337 }
338
339 if (!amdgpu_vm_is_bo_always_valid(vm, bo))
340 amdgpu_evf_mgr_detach_fence(&fpriv->evf_mgr, bo);
341
342 bo_va = amdgpu_vm_bo_find(vm, bo);
343 if (!bo_va || --bo_va->ref_count)
344 goto out_unlock;
345
346 amdgpu_vm_bo_del(adev, bo_va);
347 amdgpu_vm_bo_update_shared(bo);
348 if (!amdgpu_vm_ready(vm))
349 goto out_unlock;
350
351 r = amdgpu_vm_clear_freed(adev, vm, &fence);
352 if (unlikely(r < 0) && !drm_dev_is_unplugged(adev_to_drm(adev)))
353 dev_err(adev->dev, "failed to clear page "
354 "tables on GEM object close (%ld)\n", r);
355 if (r || !fence)
356 goto out_unlock;
357
358 amdgpu_bo_fence(bo, fence, true);
359 dma_fence_put(fence);
360
361 out_unlock:
362 if (r && !drm_dev_is_unplugged(adev_to_drm(adev)))
363 dev_err(adev->dev, "leaking bo va (%ld)\n", r);
364 drm_exec_fini(&exec);
365 }
366
amdgpu_gem_object_mmap(struct drm_gem_object * obj,struct vm_area_struct * vma)367 static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
368 {
369 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
370
371 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
372 return -EPERM;
373 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
374 return -EPERM;
375
376 /* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings
377 * for debugger access to invisible VRAM. Should have used MAP_SHARED
378 * instead. Clearing VM_MAYWRITE prevents the mapping from ever
379 * becoming writable and makes is_cow_mapping(vm_flags) false.
380 */
381 if (is_cow_mapping(vma->vm_flags) &&
382 !(vma->vm_flags & VM_ACCESS_FLAGS))
383 vm_flags_clear(vma, VM_MAYWRITE);
384
385 return drm_gem_ttm_mmap(obj, vma);
386 }
387
388 const struct drm_gem_object_funcs amdgpu_gem_object_funcs = {
389 .free = amdgpu_gem_object_free,
390 .open = amdgpu_gem_object_open,
391 .close = amdgpu_gem_object_close,
392 .export = amdgpu_gem_prime_export,
393 .vmap = drm_gem_ttm_vmap,
394 .vunmap = drm_gem_ttm_vunmap,
395 .mmap = amdgpu_gem_object_mmap,
396 .vm_ops = &amdgpu_gem_vm_ops,
397 };
398
399 /*
400 * GEM ioctls.
401 */
amdgpu_gem_create_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)402 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
403 struct drm_file *filp)
404 {
405 struct amdgpu_device *adev = drm_to_adev(dev);
406 struct amdgpu_fpriv *fpriv = filp->driver_priv;
407 struct amdgpu_vm *vm = &fpriv->vm;
408 union drm_amdgpu_gem_create *args = data;
409 uint64_t flags = args->in.domain_flags;
410 uint64_t size = args->in.bo_size;
411 struct dma_resv *resv = NULL;
412 struct drm_gem_object *gobj;
413 uint32_t handle, initial_domain;
414 int r;
415
416 /* reject invalid gem flags */
417 if (flags & ~AMDGPU_GEM_CREATE_SETTABLE_MASK)
418 return -EINVAL;
419
420 /* reject invalid gem domains */
421 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
422 return -EINVAL;
423
424 if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
425 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n");
426 return -EINVAL;
427 }
428
429 /* always clear VRAM */
430 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
431
432 /* create a gem object to contain this object in */
433 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
434 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
435 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
436 /* if gds bo is created from user space, it must be
437 * passed to bo list
438 */
439 DRM_ERROR("GDS bo cannot be per-vm-bo\n");
440 return -EINVAL;
441 }
442 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
443 }
444
445 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
446 r = amdgpu_bo_reserve(vm->root.bo, false);
447 if (r)
448 return r;
449
450 resv = vm->root.bo->tbo.base.resv;
451 }
452
453 initial_domain = (u32)(0xffffffff & args->in.domains);
454 retry:
455 r = amdgpu_gem_object_create(adev, size, args->in.alignment,
456 initial_domain,
457 flags, ttm_bo_type_device, resv, &gobj, fpriv->xcp_id + 1);
458 if (r && r != -ERESTARTSYS) {
459 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
460 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
461 goto retry;
462 }
463
464 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
465 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
466 goto retry;
467 }
468 DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n",
469 size, initial_domain, args->in.alignment, r);
470 }
471
472 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
473 if (!r) {
474 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
475
476 abo->parent = amdgpu_bo_ref(vm->root.bo);
477 }
478 amdgpu_bo_unreserve(vm->root.bo);
479 }
480 if (r)
481 return r;
482
483 r = drm_gem_handle_create(filp, gobj, &handle);
484 /* drop reference from allocate - handle holds it now */
485 drm_gem_object_put(gobj);
486 if (r)
487 return r;
488
489 memset(args, 0, sizeof(*args));
490 args->out.handle = handle;
491 return 0;
492 }
493
amdgpu_gem_userptr_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)494 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
495 struct drm_file *filp)
496 {
497 struct ttm_operation_ctx ctx = { true, false };
498 struct amdgpu_device *adev = drm_to_adev(dev);
499 struct drm_amdgpu_gem_userptr *args = data;
500 struct amdgpu_fpriv *fpriv = filp->driver_priv;
501 struct drm_gem_object *gobj;
502 struct amdgpu_hmm_range *range;
503 struct amdgpu_bo *bo;
504 uint32_t handle;
505 int r;
506
507 args->addr = untagged_addr(args->addr);
508
509 if (offset_in_page(args->addr | args->size))
510 return -EINVAL;
511
512 if (!access_ok((void __user *)(uintptr_t)args->addr, args->size))
513 return -EFAULT;
514
515 /* reject unknown flag values */
516 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
517 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
518 AMDGPU_GEM_USERPTR_REGISTER))
519 return -EINVAL;
520
521 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
522 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
523
524 /* if we want to write to it we must install a MMU notifier */
525 return -EACCES;
526 }
527
528 /* create a gem object to contain this object in */
529 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
530 0, ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1);
531 if (r)
532 return r;
533
534 bo = gem_to_amdgpu_bo(gobj);
535 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
536 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
537 r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags);
538 if (r)
539 goto release_object;
540
541 r = amdgpu_hmm_register(bo, args->addr);
542 if (r)
543 goto release_object;
544
545 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
546 range = amdgpu_hmm_range_alloc(NULL);
547 if (unlikely(!range))
548 return -ENOMEM;
549 r = amdgpu_ttm_tt_get_user_pages(bo, range);
550 if (r) {
551 amdgpu_hmm_range_free(range);
552 goto release_object;
553 }
554 r = amdgpu_bo_reserve(bo, true);
555 if (r)
556 goto user_pages_done;
557
558 amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, range);
559
560 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
561 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
562 amdgpu_bo_unreserve(bo);
563 if (r)
564 goto user_pages_done;
565 }
566
567 r = drm_gem_handle_create(filp, gobj, &handle);
568 if (r)
569 goto user_pages_done;
570
571 args->handle = handle;
572
573 user_pages_done:
574 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
575 amdgpu_hmm_range_free(range);
576 release_object:
577 drm_gem_object_put(gobj);
578
579 return r;
580 }
581
amdgpu_mode_dumb_mmap(struct drm_file * filp,struct drm_device * dev,uint32_t handle,uint64_t * offset_p)582 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
583 struct drm_device *dev,
584 uint32_t handle, uint64_t *offset_p)
585 {
586 struct drm_gem_object *gobj;
587 struct amdgpu_bo *robj;
588
589 gobj = drm_gem_object_lookup(filp, handle);
590 if (!gobj)
591 return -ENOENT;
592
593 robj = gem_to_amdgpu_bo(gobj);
594 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
595 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
596 drm_gem_object_put(gobj);
597 return -EPERM;
598 }
599 *offset_p = amdgpu_bo_mmap_offset(robj);
600 drm_gem_object_put(gobj);
601 return 0;
602 }
603
amdgpu_gem_mmap_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)604 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
605 struct drm_file *filp)
606 {
607 union drm_amdgpu_gem_mmap *args = data;
608 uint32_t handle = args->in.handle;
609
610 memset(args, 0, sizeof(*args));
611 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
612 }
613
614 /**
615 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
616 *
617 * @timeout_ns: timeout in ns
618 *
619 * Calculate the timeout in jiffies from an absolute timeout in ns.
620 */
amdgpu_gem_timeout(uint64_t timeout_ns)621 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
622 {
623 unsigned long timeout_jiffies;
624 ktime_t timeout;
625
626 /* clamp timeout if it's to large */
627 if (((int64_t)timeout_ns) < 0)
628 return MAX_SCHEDULE_TIMEOUT;
629
630 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
631 if (ktime_to_ns(timeout) < 0)
632 return 0;
633
634 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
635 /* clamp timeout to avoid unsigned-> signed overflow */
636 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT)
637 return MAX_SCHEDULE_TIMEOUT - 1;
638
639 return timeout_jiffies;
640 }
641
amdgpu_gem_wait_idle_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)642 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
643 struct drm_file *filp)
644 {
645 union drm_amdgpu_gem_wait_idle *args = data;
646 struct drm_gem_object *gobj;
647 struct amdgpu_bo *robj;
648 uint32_t handle = args->in.handle;
649 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
650 int r = 0;
651 long ret;
652
653 gobj = drm_gem_object_lookup(filp, handle);
654 if (!gobj)
655 return -ENOENT;
656
657 robj = gem_to_amdgpu_bo(gobj);
658 ret = dma_resv_wait_timeout(robj->tbo.base.resv, DMA_RESV_USAGE_READ,
659 true, timeout);
660
661 /* ret == 0 means not signaled,
662 * ret > 0 means signaled
663 * ret < 0 means interrupted before timeout
664 */
665 if (ret >= 0) {
666 memset(args, 0, sizeof(*args));
667 args->out.status = (ret == 0);
668 } else
669 r = ret;
670
671 drm_gem_object_put(gobj);
672 return r;
673 }
674
amdgpu_gem_metadata_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)675 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
676 struct drm_file *filp)
677 {
678 struct drm_amdgpu_gem_metadata *args = data;
679 struct drm_gem_object *gobj;
680 struct amdgpu_bo *robj;
681 int r = -1;
682
683 DRM_DEBUG("%d\n", args->handle);
684 gobj = drm_gem_object_lookup(filp, args->handle);
685 if (gobj == NULL)
686 return -ENOENT;
687 robj = gem_to_amdgpu_bo(gobj);
688
689 r = amdgpu_bo_reserve(robj, false);
690 if (unlikely(r != 0))
691 goto out;
692
693 /* Reject MMIO_REMAP BOs at IOCTL level: metadata/tiling does not apply. */
694 if (robj->tbo.resource &&
695 robj->tbo.resource->mem_type == AMDGPU_PL_MMIO_REMAP) {
696 DRM_WARN("metadata ioctl on MMIO_REMAP BO (handle %d)\n",
697 args->handle);
698 r = -EINVAL;
699 goto unreserve;
700 }
701
702 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
703 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
704 r = amdgpu_bo_get_metadata(robj, args->data.data,
705 sizeof(args->data.data),
706 &args->data.data_size_bytes,
707 &args->data.flags);
708 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
709 if (args->data.data_size_bytes > sizeof(args->data.data)) {
710 r = -EINVAL;
711 goto unreserve;
712 }
713 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
714 if (!r)
715 r = amdgpu_bo_set_metadata(robj, args->data.data,
716 args->data.data_size_bytes,
717 args->data.flags);
718 }
719
720 unreserve:
721 amdgpu_bo_unreserve(robj);
722 out:
723 drm_gem_object_put(gobj);
724 return r;
725 }
726
727 /**
728 * amdgpu_gem_va_update_vm -update the bo_va in its VM
729 *
730 * @adev: amdgpu_device pointer
731 * @vm: vm to update
732 * @bo_va: bo_va to update
733 * @operation: map, unmap or clear
734 *
735 * Update the bo_va directly after setting its address. Errors are not
736 * vital here, so they are not reported back to userspace.
737 *
738 * Returns resulting fence if freed BO(s) got cleared from the PT.
739 * otherwise stub fence in case of error.
740 */
741 static struct dma_fence *
amdgpu_gem_va_update_vm(struct amdgpu_device * adev,struct amdgpu_vm * vm,struct amdgpu_bo_va * bo_va,uint32_t operation)742 amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
743 struct amdgpu_vm *vm,
744 struct amdgpu_bo_va *bo_va,
745 uint32_t operation)
746 {
747 struct dma_fence *fence;
748 int r = 0;
749
750 /* If the VM is not ready return only a stub. */
751 if (!amdgpu_vm_ready(vm))
752 return dma_fence_get_stub();
753
754
755 /*
756 * First clean up any freed mappings in the VM.
757 *
758 * amdgpu_vm_clear_freed() may replace @fence with a new fence if it
759 * schedules GPU work. If nothing needs clearing, @fence can remain as
760 * the original vm->last_update.
761 */
762 r = amdgpu_vm_clear_freed(adev, vm, &vm->last_update);
763 if (r)
764 goto error;
765
766 /* For MAP/REPLACE we also need to update the BO mappings. */
767 if (operation == AMDGPU_VA_OP_MAP ||
768 operation == AMDGPU_VA_OP_REPLACE) {
769 r = amdgpu_vm_bo_update(adev, bo_va, false);
770 if (r)
771 goto error;
772 }
773
774 /* Always update PDEs after we touched the mappings. */
775 r = amdgpu_vm_update_pdes(adev, vm, false);
776 if (r)
777 goto error;
778
779 if ((operation == AMDGPU_VA_OP_MAP ||
780 operation == AMDGPU_VA_OP_REPLACE) &&
781 !amdgpu_vm_is_bo_always_valid(vm, bo_va->base.bo)) {
782
783 /*
784 * For MAP/REPLACE of non per-VM BOs we need to sync to both the
785 * bo_va->last_pt_update and vm->last_update or otherwise we
786 * potentially miss the PDE updates.
787 */
788 fence = dma_fence_unwrap_merge(vm->last_update,
789 bo_va->last_pt_update);
790 if (!fence) {
791 /* As fallback in OOM situations */
792 dma_fence_wait(vm->last_update, false);
793 dma_fence_wait(bo_va->last_pt_update, false);
794 fence = dma_fence_get_stub();
795 }
796 } else {
797 fence = dma_fence_get(vm->last_update);
798 }
799
800 return fence;
801
802 error:
803 if (r && r != -ERESTARTSYS)
804 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
805
806 return dma_fence_get(vm->last_update);
807 }
808
amdgpu_gem_va_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)809 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
810 struct drm_file *filp)
811 {
812 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
813 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
814 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK |
815 AMDGPU_VM_PAGE_NOALLOC;
816 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
817 AMDGPU_VM_PAGE_PRT;
818
819 struct drm_amdgpu_gem_va *args = data;
820 struct drm_gem_object *gobj;
821 struct amdgpu_device *adev = drm_to_adev(dev);
822 struct amdgpu_fpriv *fpriv = filp->driver_priv;
823 struct amdgpu_bo *abo;
824 struct amdgpu_bo_va *bo_va;
825 struct drm_syncobj *timeline_syncobj = NULL;
826 struct dma_fence_chain *timeline_chain = NULL;
827 struct drm_exec exec;
828 uint64_t vm_size, tmp;
829 int r = 0;
830
831 /* Validate virtual address range against reserved regions. */
832 if (args->va_address < AMDGPU_VA_RESERVED_BOTTOM) {
833 dev_dbg(dev->dev,
834 "va_address 0x%llx is in reserved area 0x%llx\n",
835 args->va_address, AMDGPU_VA_RESERVED_BOTTOM);
836 return -EINVAL;
837 }
838
839 if (args->va_address >= AMDGPU_GMC_HOLE_START &&
840 args->va_address < AMDGPU_GMC_HOLE_END) {
841 dev_dbg(dev->dev,
842 "va_address 0x%llx is in VA hole 0x%llx-0x%llx\n",
843 args->va_address, AMDGPU_GMC_HOLE_START,
844 AMDGPU_GMC_HOLE_END);
845 return -EINVAL;
846 }
847
848 args->va_address &= AMDGPU_GMC_HOLE_MASK;
849
850 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
851 vm_size -= AMDGPU_VA_RESERVED_TOP;
852 if (check_add_overflow(args->va_address, args->map_size, &tmp) || tmp > vm_size) {
853 dev_dbg(dev->dev,
854 "va_address 0x%llx is in top reserved area 0x%llx\n",
855 args->va_address + args->map_size, vm_size);
856 return -EINVAL;
857 }
858
859 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
860 dev_dbg(dev->dev, "invalid flags combination 0x%08X\n",
861 args->flags);
862 return -EINVAL;
863 }
864
865 /* Validate operation type. */
866 switch (args->operation) {
867 case AMDGPU_VA_OP_MAP:
868 case AMDGPU_VA_OP_UNMAP:
869 case AMDGPU_VA_OP_CLEAR:
870 case AMDGPU_VA_OP_REPLACE:
871 break;
872 default:
873 dev_dbg(dev->dev, "unsupported operation %d\n",
874 args->operation);
875 return -EINVAL;
876 }
877
878 if (args->flags & AMDGPU_VM_DELAY_UPDATE &&
879 args->vm_timeline_syncobj_out)
880 return -EINVAL;
881
882 if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
883 !(args->flags & AMDGPU_VM_PAGE_PRT)) {
884 gobj = drm_gem_object_lookup(filp, args->handle);
885 if (gobj == NULL)
886 return -ENOENT;
887 abo = gem_to_amdgpu_bo(gobj);
888 } else {
889 gobj = NULL;
890 abo = NULL;
891 }
892
893 /* Add input syncobj fences (if any) for synchronization. */
894 r = amdgpu_gem_add_input_fence(filp,
895 args->input_fence_syncobj_handles,
896 args->num_syncobj_handles);
897 if (r)
898 goto error_put_gobj;
899
900 drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
901 DRM_EXEC_IGNORE_DUPLICATES, 0);
902 drm_exec_until_all_locked(&exec) {
903 if (gobj) {
904 r = drm_exec_lock_obj(&exec, gobj);
905 drm_exec_retry_on_contention(&exec);
906 if (unlikely(r))
907 goto error;
908 }
909
910 r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 2);
911 drm_exec_retry_on_contention(&exec);
912 if (unlikely(r))
913 goto error;
914 }
915
916 /* Resolve the BO-VA mapping for this VM/BO combination. */
917 if (abo) {
918 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
919 if (!bo_va) {
920 r = -ENOENT;
921 goto error;
922 }
923 } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
924 bo_va = fpriv->prt_va;
925 } else {
926 bo_va = NULL;
927 }
928
929 /*
930 * Prepare the timeline syncobj node if the user requested a VM
931 * timeline update. This only allocates/looks up the syncobj and
932 * chain node; the actual fence is attached later.
933 */
934 r = amdgpu_gem_update_timeline_node(filp,
935 args->vm_timeline_syncobj_out,
936 args->vm_timeline_point,
937 &timeline_syncobj,
938 &timeline_chain);
939 if (r)
940 goto error;
941
942 switch (args->operation) {
943 case AMDGPU_VA_OP_MAP:
944 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
945 args->offset_in_bo, args->map_size,
946 args->flags);
947 break;
948 case AMDGPU_VA_OP_UNMAP:
949 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
950 break;
951
952 case AMDGPU_VA_OP_CLEAR:
953 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
954 args->va_address,
955 args->map_size);
956 break;
957 case AMDGPU_VA_OP_REPLACE:
958 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
959 args->offset_in_bo, args->map_size,
960 args->flags);
961 break;
962 default:
963 break;
964 }
965
966 /*
967 * Once the VA operation is done, update the VM and obtain the fence
968 * that represents the last relevant update for this mapping. This
969 * fence can then be exported to the user-visible VM timeline.
970 */
971 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
972 (!adev->debug_vm || timeline_syncobj)) {
973 struct dma_fence *fence;
974
975 fence = amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va,
976 args->operation);
977 if (timeline_syncobj) {
978 if (!args->vm_timeline_point) {
979 /* Replace the existing fence when no point is given. */
980 drm_syncobj_replace_fence(timeline_syncobj,
981 fence);
982 } else {
983 /* Attach the last-update fence at a specific point. */
984 drm_syncobj_add_point(timeline_syncobj,
985 timeline_chain,
986 fence,
987 args->vm_timeline_point);
988 timeline_chain = NULL;
989 }
990 }
991 dma_fence_put(fence);
992
993 }
994
995 error:
996 dma_fence_chain_free(timeline_chain);
997 if (timeline_syncobj)
998 drm_syncobj_put(timeline_syncobj);
999 drm_exec_fini(&exec);
1000 error_put_gobj:
1001 drm_gem_object_put(gobj);
1002 return r;
1003 }
1004
amdgpu_gem_op_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)1005 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1006 struct drm_file *filp)
1007 {
1008 struct drm_amdgpu_gem_op *args = data;
1009 struct drm_gem_object *gobj;
1010 struct amdgpu_vm_bo_base *base;
1011 struct amdgpu_bo *robj;
1012 struct drm_exec exec;
1013 struct amdgpu_fpriv *fpriv = filp->driver_priv;
1014 int r;
1015
1016 if (args->padding)
1017 return -EINVAL;
1018
1019 gobj = drm_gem_object_lookup(filp, args->handle);
1020 if (!gobj)
1021 return -ENOENT;
1022
1023 robj = gem_to_amdgpu_bo(gobj);
1024
1025 drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
1026 DRM_EXEC_IGNORE_DUPLICATES, 0);
1027 drm_exec_until_all_locked(&exec) {
1028 r = drm_exec_lock_obj(&exec, gobj);
1029 drm_exec_retry_on_contention(&exec);
1030 if (r)
1031 goto out_exec;
1032
1033 if (args->op == AMDGPU_GEM_OP_GET_MAPPING_INFO) {
1034 r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 0);
1035 drm_exec_retry_on_contention(&exec);
1036 if (r)
1037 goto out_exec;
1038 }
1039 }
1040
1041 switch (args->op) {
1042 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
1043 struct drm_amdgpu_gem_create_in info;
1044 void __user *out = u64_to_user_ptr(args->value);
1045
1046 info.bo_size = robj->tbo.base.size;
1047 info.alignment = robj->tbo.page_alignment << PAGE_SHIFT;
1048 info.domains = robj->preferred_domains;
1049 info.domain_flags = robj->flags;
1050 drm_exec_fini(&exec);
1051 if (copy_to_user(out, &info, sizeof(info)))
1052 r = -EFAULT;
1053 break;
1054 }
1055 case AMDGPU_GEM_OP_SET_PLACEMENT:
1056 if (drm_gem_is_imported(&robj->tbo.base) &&
1057 args->value & AMDGPU_GEM_DOMAIN_VRAM) {
1058 r = -EINVAL;
1059 goto out_exec;
1060 }
1061 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
1062 r = -EPERM;
1063 goto out_exec;
1064 }
1065 for (base = robj->vm_bo; base; base = base->next)
1066 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev),
1067 amdgpu_ttm_adev(base->vm->root.bo->tbo.bdev))) {
1068 r = -EINVAL;
1069 goto out_exec;
1070 }
1071
1072
1073 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
1074 AMDGPU_GEM_DOMAIN_GTT |
1075 AMDGPU_GEM_DOMAIN_CPU);
1076 robj->allowed_domains = robj->preferred_domains;
1077 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
1078 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
1079
1080 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
1081 amdgpu_vm_bo_invalidate(robj, true);
1082 drm_exec_fini(&exec);
1083 break;
1084 case AMDGPU_GEM_OP_GET_MAPPING_INFO: {
1085 struct amdgpu_bo_va *bo_va = amdgpu_vm_bo_find(&fpriv->vm, robj);
1086 struct drm_amdgpu_gem_vm_entry *vm_entries;
1087 struct amdgpu_bo_va_mapping *mapping;
1088 int num_mappings = 0;
1089 /*
1090 * num_entries is set as an input to the size of the user-allocated array of
1091 * drm_amdgpu_gem_vm_entry stored at args->value.
1092 * num_entries is sent back as output as the number of mappings the bo has.
1093 * If that number is larger than the size of the array, the ioctl must
1094 * be retried.
1095 */
1096 vm_entries = kvcalloc(args->num_entries, sizeof(*vm_entries), GFP_KERNEL);
1097 if (!vm_entries)
1098 return -ENOMEM;
1099
1100 amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) {
1101 if (num_mappings < args->num_entries) {
1102 vm_entries[num_mappings].addr = mapping->start * AMDGPU_GPU_PAGE_SIZE;
1103 vm_entries[num_mappings].size = (mapping->last - mapping->start + 1) * AMDGPU_GPU_PAGE_SIZE;
1104 vm_entries[num_mappings].offset = mapping->offset;
1105 vm_entries[num_mappings].flags = mapping->flags;
1106 }
1107 num_mappings += 1;
1108 }
1109
1110 amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) {
1111 if (num_mappings < args->num_entries) {
1112 vm_entries[num_mappings].addr = mapping->start * AMDGPU_GPU_PAGE_SIZE;
1113 vm_entries[num_mappings].size = (mapping->last - mapping->start + 1) * AMDGPU_GPU_PAGE_SIZE;
1114 vm_entries[num_mappings].offset = mapping->offset;
1115 vm_entries[num_mappings].flags = mapping->flags;
1116 }
1117 num_mappings += 1;
1118 }
1119
1120 drm_exec_fini(&exec);
1121
1122 if (num_mappings > 0 && num_mappings <= args->num_entries)
1123 if (copy_to_user(u64_to_user_ptr(args->value), vm_entries, num_mappings * sizeof(*vm_entries)))
1124 r = -EFAULT;
1125
1126 args->num_entries = num_mappings;
1127
1128 kvfree(vm_entries);
1129 break;
1130 }
1131 default:
1132 drm_exec_fini(&exec);
1133 r = -EINVAL;
1134 }
1135
1136 drm_gem_object_put(gobj);
1137 return r;
1138 out_exec:
1139 drm_exec_fini(&exec);
1140 drm_gem_object_put(gobj);
1141 return r;
1142 }
1143
1144 /**
1145 * amdgpu_gem_list_handles_ioctl - get information about a process' buffer objects
1146 *
1147 * @dev: drm device pointer
1148 * @data: drm_amdgpu_gem_list_handles
1149 * @filp: drm file pointer
1150 *
1151 * num_entries is set as an input to the size of the entries array.
1152 * num_entries is sent back as output as the number of bos in the process.
1153 * If that number is larger than the size of the array, the ioctl must
1154 * be retried.
1155 *
1156 * Returns:
1157 * 0 for success, -errno for errors.
1158 */
amdgpu_gem_list_handles_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)1159 int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data,
1160 struct drm_file *filp)
1161 {
1162 struct drm_amdgpu_gem_list_handles *args = data;
1163 struct drm_amdgpu_gem_list_handles_entry *bo_entries;
1164 struct drm_gem_object *gobj;
1165 int id, ret = 0;
1166 int bo_index = 0;
1167 int num_bos = 0;
1168
1169 spin_lock(&filp->table_lock);
1170 idr_for_each_entry(&filp->object_idr, gobj, id)
1171 num_bos += 1;
1172 spin_unlock(&filp->table_lock);
1173
1174 if (args->num_entries < num_bos) {
1175 args->num_entries = num_bos;
1176 return 0;
1177 }
1178
1179 if (num_bos == 0) {
1180 args->num_entries = 0;
1181 return 0;
1182 }
1183
1184 bo_entries = kvzalloc_objs(*bo_entries, num_bos);
1185 if (!bo_entries)
1186 return -ENOMEM;
1187
1188 spin_lock(&filp->table_lock);
1189 idr_for_each_entry(&filp->object_idr, gobj, id) {
1190 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
1191 struct drm_amdgpu_gem_list_handles_entry *bo_entry;
1192
1193 if (bo_index >= num_bos) {
1194 ret = -EAGAIN;
1195 break;
1196 }
1197
1198 bo_entry = &bo_entries[bo_index];
1199
1200 bo_entry->size = amdgpu_bo_size(bo);
1201 bo_entry->alloc_flags = bo->flags & AMDGPU_GEM_CREATE_SETTABLE_MASK;
1202 bo_entry->preferred_domains = bo->preferred_domains;
1203 bo_entry->gem_handle = id;
1204 bo_entry->alignment = bo->tbo.page_alignment;
1205
1206 if (bo->tbo.base.import_attach)
1207 bo_entry->flags |= AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT;
1208
1209 bo_index += 1;
1210 }
1211 spin_unlock(&filp->table_lock);
1212
1213 args->num_entries = bo_index;
1214
1215 if (!ret)
1216 if (copy_to_user(u64_to_user_ptr(args->entries), bo_entries, num_bos * sizeof(*bo_entries)))
1217 ret = -EFAULT;
1218
1219 kvfree(bo_entries);
1220
1221 return ret;
1222 }
1223
amdgpu_gem_align_pitch(struct amdgpu_device * adev,int width,int cpp,bool tiled)1224 static int amdgpu_gem_align_pitch(struct amdgpu_device *adev,
1225 int width,
1226 int cpp,
1227 bool tiled)
1228 {
1229 int aligned = width;
1230 int pitch_mask = 0;
1231
1232 switch (cpp) {
1233 case 1:
1234 pitch_mask = 255;
1235 break;
1236 case 2:
1237 pitch_mask = 127;
1238 break;
1239 case 3:
1240 case 4:
1241 pitch_mask = 63;
1242 break;
1243 }
1244
1245 aligned += pitch_mask;
1246 aligned &= ~pitch_mask;
1247 return aligned * cpp;
1248 }
1249
amdgpu_mode_dumb_create(struct drm_file * file_priv,struct drm_device * dev,struct drm_mode_create_dumb * args)1250 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
1251 struct drm_device *dev,
1252 struct drm_mode_create_dumb *args)
1253 {
1254 struct amdgpu_device *adev = drm_to_adev(dev);
1255 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1256 struct drm_gem_object *gobj;
1257 uint32_t handle;
1258 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1259 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
1260 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1261 u32 domain;
1262 int r;
1263
1264 /*
1265 * The buffer returned from this function should be cleared, but
1266 * it can only be done if the ring is enabled or we'll fail to
1267 * create the buffer.
1268 */
1269 if (adev->mman.buffer_funcs_enabled)
1270 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
1271
1272 args->pitch = amdgpu_gem_align_pitch(adev, args->width,
1273 DIV_ROUND_UP(args->bpp, 8), 0);
1274 args->size = (u64)args->pitch * args->height;
1275 args->size = ALIGN(args->size, PAGE_SIZE);
1276 domain = amdgpu_bo_get_preferred_domain(adev,
1277 amdgpu_display_supported_domains(adev, flags));
1278 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
1279 ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1);
1280 if (r)
1281 return -ENOMEM;
1282
1283 r = drm_gem_handle_create(file_priv, gobj, &handle);
1284 /* drop reference from allocate - handle holds it now */
1285 drm_gem_object_put(gobj);
1286 if (r)
1287 return r;
1288
1289 args->handle = handle;
1290 return 0;
1291 }
1292
1293 #if defined(CONFIG_DEBUG_FS)
amdgpu_debugfs_gem_info_show(struct seq_file * m,void * unused)1294 static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused)
1295 {
1296 struct amdgpu_device *adev = m->private;
1297 struct drm_device *dev = adev_to_drm(adev);
1298 struct drm_file *file;
1299 int r;
1300
1301 r = mutex_lock_interruptible(&dev->filelist_mutex);
1302 if (r)
1303 return r;
1304
1305 list_for_each_entry(file, &dev->filelist, lhead) {
1306 struct task_struct *task;
1307 struct drm_gem_object *gobj;
1308 struct pid *pid;
1309 int id;
1310
1311 /*
1312 * Although we have a valid reference on file->pid, that does
1313 * not guarantee that the task_struct who called get_pid() is
1314 * still alive (e.g. get_pid(current) => fork() => exit()).
1315 * Therefore, we need to protect this ->comm access using RCU.
1316 */
1317 rcu_read_lock();
1318 pid = rcu_dereference(file->pid);
1319 task = pid_task(pid, PIDTYPE_TGID);
1320 seq_printf(m, "pid %8d command %s:\n", pid_nr(pid),
1321 task ? task->comm : "<unknown>");
1322 rcu_read_unlock();
1323
1324 spin_lock(&file->table_lock);
1325 idr_for_each_entry(&file->object_idr, gobj, id) {
1326 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
1327
1328 amdgpu_bo_print_info(id, bo, m);
1329 }
1330 spin_unlock(&file->table_lock);
1331 }
1332
1333 mutex_unlock(&dev->filelist_mutex);
1334 return 0;
1335 }
1336
1337 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gem_info);
1338
1339 #endif
1340
amdgpu_debugfs_gem_init(struct amdgpu_device * adev)1341 void amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
1342 {
1343 #if defined(CONFIG_DEBUG_FS)
1344 struct drm_minor *minor = adev_to_drm(adev)->primary;
1345 struct dentry *root = minor->debugfs_root;
1346
1347 debugfs_create_file("amdgpu_gem_info", 0444, root, adev,
1348 &amdgpu_debugfs_gem_info_fops);
1349 #endif
1350 }
1351