1 /* 2 * Copyright (c) 2018-2021 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23 #ifndef AMDGV_SRIOV_MSG__H_ 24 #define AMDGV_SRIOV_MSG__H_ 25 26 /* unit in kilobytes */ 27 #define AMD_SRIOV_MSG_VBIOS_OFFSET 0 28 #define AMD_SRIOV_MSG_VBIOS_SIZE_KB 64 29 #define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB AMD_SRIOV_MSG_VBIOS_SIZE_KB 30 #define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB 4 31 #define AMD_SRIOV_MSG_TMR_OFFSET_KB 2048 32 #define AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB 2 33 #define AMD_SRIOV_RAS_TELEMETRY_SIZE_KB 64 34 /* 35 * layout 36 * 0 64KB 65KB 66KB 68KB 132KB 37 * | VBIOS | PF2VF | VF2PF | Bad Page | RAS Telemetry Region | ... 38 * | 64KB | 1KB | 1KB | 2KB | 64KB | ... 39 */ 40 41 #define AMD_SRIOV_MSG_SIZE_KB 1 42 #define AMD_SRIOV_MSG_PF2VF_OFFSET_KB AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB 43 #define AMD_SRIOV_MSG_VF2PF_OFFSET_KB (AMD_SRIOV_MSG_PF2VF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB) 44 #define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB (AMD_SRIOV_MSG_VF2PF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB) 45 #define AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB (AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB + AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB) 46 47 /* 48 * PF2VF history log: 49 * v1 defined in amdgim 50 * v2 current 51 * 52 * VF2PF history log: 53 * v1 defined in amdgim 54 * v2 defined in amdgim 55 * v3 current 56 */ 57 #define AMD_SRIOV_MSG_FW_VRAM_PF2VF_VER 2 58 #define AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER 3 59 60 #define AMD_SRIOV_MSG_RESERVE_UCODE 24 61 62 #define AMD_SRIOV_MSG_RESERVE_VCN_INST 4 63 64 enum amd_sriov_ucode_engine_id { 65 AMD_SRIOV_UCODE_ID_VCE = 0, 66 AMD_SRIOV_UCODE_ID_UVD, 67 AMD_SRIOV_UCODE_ID_MC, 68 AMD_SRIOV_UCODE_ID_ME, 69 AMD_SRIOV_UCODE_ID_PFP, 70 AMD_SRIOV_UCODE_ID_CE, 71 AMD_SRIOV_UCODE_ID_RLC, 72 AMD_SRIOV_UCODE_ID_RLC_SRLC, 73 AMD_SRIOV_UCODE_ID_RLC_SRLG, 74 AMD_SRIOV_UCODE_ID_RLC_SRLS, 75 AMD_SRIOV_UCODE_ID_MEC, 76 AMD_SRIOV_UCODE_ID_MEC2, 77 AMD_SRIOV_UCODE_ID_SOS, 78 AMD_SRIOV_UCODE_ID_ASD, 79 AMD_SRIOV_UCODE_ID_TA_RAS, 80 AMD_SRIOV_UCODE_ID_TA_XGMI, 81 AMD_SRIOV_UCODE_ID_SMC, 82 AMD_SRIOV_UCODE_ID_SDMA, 83 AMD_SRIOV_UCODE_ID_SDMA2, 84 AMD_SRIOV_UCODE_ID_VCN, 85 AMD_SRIOV_UCODE_ID_DMCU, 86 AMD_SRIOV_UCODE_ID__MAX 87 }; 88 89 #pragma pack(push, 1) // PF2VF / VF2PF data areas are byte packed 90 91 union amd_sriov_msg_feature_flags { 92 struct { 93 uint32_t error_log_collect : 1; 94 uint32_t host_load_ucodes : 1; 95 uint32_t host_flr_vramlost : 1; 96 uint32_t mm_bw_management : 1; 97 uint32_t pp_one_vf_mode : 1; 98 uint32_t reg_indirect_acc : 1; 99 uint32_t av1_support : 1; 100 uint32_t vcn_rb_decouple : 1; 101 uint32_t mes_info_dump_enable : 1; 102 uint32_t ras_caps : 1; 103 uint32_t ras_telemetry : 1; 104 uint32_t ras_cper : 1; 105 uint32_t reserved : 20; 106 } flags; 107 uint32_t all; 108 }; 109 110 union amd_sriov_reg_access_flags { 111 struct { 112 uint32_t vf_reg_access_ih : 1; 113 uint32_t vf_reg_access_mmhub : 1; 114 uint32_t vf_reg_access_gc : 1; 115 uint32_t reserved : 29; 116 } flags; 117 uint32_t all; 118 }; 119 120 union amd_sriov_ras_caps { 121 struct { 122 uint64_t block_umc : 1; 123 uint64_t block_sdma : 1; 124 uint64_t block_gfx : 1; 125 uint64_t block_mmhub : 1; 126 uint64_t block_athub : 1; 127 uint64_t block_pcie_bif : 1; 128 uint64_t block_hdp : 1; 129 uint64_t block_xgmi_wafl : 1; 130 uint64_t block_df : 1; 131 uint64_t block_smn : 1; 132 uint64_t block_sem : 1; 133 uint64_t block_mp0 : 1; 134 uint64_t block_mp1 : 1; 135 uint64_t block_fuse : 1; 136 uint64_t block_mca : 1; 137 uint64_t block_vcn : 1; 138 uint64_t block_jpeg : 1; 139 uint64_t block_ih : 1; 140 uint64_t block_mpio : 1; 141 uint64_t poison_propogation_mode : 1; 142 uint64_t reserved : 44; 143 } bits; 144 uint64_t all; 145 }; 146 147 union amd_sriov_msg_os_info { 148 struct { 149 uint32_t windows : 1; 150 uint32_t reserved : 31; 151 } info; 152 uint32_t all; 153 }; 154 155 struct amd_sriov_msg_uuid_info { 156 union { 157 struct { 158 uint32_t did : 16; 159 uint32_t fcn : 8; 160 uint32_t asic_7 : 8; 161 }; 162 uint32_t time_low; 163 }; 164 165 struct { 166 uint32_t time_mid : 16; 167 uint32_t time_high : 12; 168 uint32_t version : 4; 169 }; 170 171 struct { 172 struct { 173 uint8_t clk_seq_hi : 6; 174 uint8_t variant : 2; 175 }; 176 union { 177 uint8_t clk_seq_low; 178 uint8_t asic_6; 179 }; 180 uint16_t asic_4; 181 }; 182 183 uint32_t asic_0; 184 }; 185 186 struct amd_sriov_msg_pf2vf_info_header { 187 /* the total structure size in byte */ 188 uint32_t size; 189 /* version of this structure, written by the HOST */ 190 uint32_t version; 191 /* reserved */ 192 uint32_t reserved[2]; 193 }; 194 195 #define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (55) 196 struct amd_sriov_msg_pf2vf_info { 197 /* header contains size and version */ 198 struct amd_sriov_msg_pf2vf_info_header header; 199 /* use private key from mailbox 2 to create checksum */ 200 uint32_t checksum; 201 /* The features flags of the HOST driver supports */ 202 union amd_sriov_msg_feature_flags feature_flags; 203 /* (max_width * max_height * fps) / (16 * 16) */ 204 uint32_t hevc_enc_max_mb_per_second; 205 /* (max_width * max_height) / (16 * 16) */ 206 uint32_t hevc_enc_max_mb_per_frame; 207 /* (max_width * max_height * fps) / (16 * 16) */ 208 uint32_t avc_enc_max_mb_per_second; 209 /* (max_width * max_height) / (16 * 16) */ 210 uint32_t avc_enc_max_mb_per_frame; 211 /* MEC FW position in BYTE from the start of VF visible frame buffer */ 212 uint64_t mecfw_offset; 213 /* MEC FW size in BYTE */ 214 uint32_t mecfw_size; 215 /* UVD FW position in BYTE from the start of VF visible frame buffer */ 216 uint64_t uvdfw_offset; 217 /* UVD FW size in BYTE */ 218 uint32_t uvdfw_size; 219 /* VCE FW position in BYTE from the start of VF visible frame buffer */ 220 uint64_t vcefw_offset; 221 /* VCE FW size in BYTE */ 222 uint32_t vcefw_size; 223 /* Bad pages block position in BYTE */ 224 uint32_t bp_block_offset_low; 225 uint32_t bp_block_offset_high; 226 /* Bad pages block size in BYTE */ 227 uint32_t bp_block_size; 228 /* frequency for VF to update the VF2PF area in msec, 0 = manual */ 229 uint32_t vf2pf_update_interval_ms; 230 /* identification in ROCm SMI */ 231 uint64_t uuid; 232 uint32_t fcn_idx; 233 /* flags to indicate which register access method VF should use */ 234 union amd_sriov_reg_access_flags reg_access_flags; 235 /* MM BW management */ 236 struct { 237 uint32_t decode_max_dimension_pixels; 238 uint32_t decode_max_frame_pixels; 239 uint32_t encode_max_dimension_pixels; 240 uint32_t encode_max_frame_pixels; 241 } mm_bw_management[AMD_SRIOV_MSG_RESERVE_VCN_INST]; 242 /* UUID info */ 243 struct amd_sriov_msg_uuid_info uuid_info; 244 /* PCIE atomic ops support flag */ 245 uint32_t pcie_atomic_ops_support_flags; 246 /* Portion of GPU memory occupied by VF. MAX value is 65535, but set to uint32_t to maintain alignment with reserved size */ 247 uint32_t gpu_capacity; 248 /* vf bdf on host pci tree for debug only */ 249 uint32_t bdf_on_host; 250 uint32_t more_bp; //Reserved for future use. 251 union amd_sriov_ras_caps ras_en_caps; 252 union amd_sriov_ras_caps ras_telemetry_en_caps; 253 254 /* reserved */ 255 uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE]; 256 } __packed; 257 258 struct amd_sriov_msg_vf2pf_info_header { 259 /* the total structure size in byte */ 260 uint32_t size; 261 /* version of this structure, written by the guest */ 262 uint32_t version; 263 /* reserved */ 264 uint32_t reserved[2]; 265 }; 266 267 #define AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE (73) 268 struct amd_sriov_msg_vf2pf_info { 269 /* header contains size and version */ 270 struct amd_sriov_msg_vf2pf_info_header header; 271 uint32_t checksum; 272 /* driver version */ 273 uint8_t driver_version[64]; 274 /* driver certification, 1=WHQL, 0=None */ 275 uint32_t driver_cert; 276 /* guest OS type and version */ 277 union amd_sriov_msg_os_info os_info; 278 /* guest fb information in the unit of MB */ 279 uint32_t fb_usage; 280 /* guest gfx engine usage percentage */ 281 uint32_t gfx_usage; 282 /* guest gfx engine health percentage */ 283 uint32_t gfx_health; 284 /* guest compute engine usage percentage */ 285 uint32_t compute_usage; 286 /* guest compute engine health percentage */ 287 uint32_t compute_health; 288 /* guest avc engine usage percentage. 0xffff means N/A */ 289 uint32_t avc_enc_usage; 290 /* guest avc engine health percentage. 0xffff means N/A */ 291 uint32_t avc_enc_health; 292 /* guest hevc engine usage percentage. 0xffff means N/A */ 293 uint32_t hevc_enc_usage; 294 /* guest hevc engine usage percentage. 0xffff means N/A */ 295 uint32_t hevc_enc_health; 296 /* combined encode/decode usage */ 297 uint32_t encode_usage; 298 uint32_t decode_usage; 299 /* Version of PF2VF that VF understands */ 300 uint32_t pf2vf_version_required; 301 /* additional FB usage */ 302 uint32_t fb_vis_usage; 303 uint32_t fb_vis_size; 304 uint32_t fb_size; 305 /* guest ucode data, each one is 1.25 Dword */ 306 struct { 307 uint8_t id; 308 uint32_t version; 309 } ucode_info[AMD_SRIOV_MSG_RESERVE_UCODE]; 310 uint64_t dummy_page_addr; 311 /* FB allocated for guest MES to record UQ info */ 312 uint64_t mes_info_addr; 313 uint32_t mes_info_size; 314 /* reserved */ 315 uint32_t reserved[256 - AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE]; 316 } __packed; 317 318 /* mailbox message send from guest to host */ 319 enum amd_sriov_mailbox_request_message { 320 MB_REQ_MSG_REQ_GPU_INIT_ACCESS = 1, 321 MB_REQ_MSG_REL_GPU_INIT_ACCESS, 322 MB_REQ_MSG_REQ_GPU_FINI_ACCESS, 323 MB_REQ_MSG_REL_GPU_FINI_ACCESS, 324 MB_REQ_MSG_REQ_GPU_RESET_ACCESS, 325 MB_REQ_MSG_REQ_GPU_INIT_DATA, 326 MB_REQ_MSG_PSP_VF_CMD_RELAY, 327 328 MB_REQ_MSG_LOG_VF_ERROR = 200, 329 MB_REQ_MSG_READY_TO_RESET = 201, 330 MB_REQ_MSG_RAS_POISON = 202, 331 MB_REQ_RAS_ERROR_COUNT = 203, 332 MB_REQ_RAS_CPER_DUMP = 204, 333 }; 334 335 /* mailbox message send from host to guest */ 336 enum amd_sriov_mailbox_response_message { 337 MB_RES_MSG_CLR_MSG_BUF = 0, 338 MB_RES_MSG_READY_TO_ACCESS_GPU = 1, 339 MB_RES_MSG_FLR_NOTIFICATION = 2, 340 MB_RES_MSG_FLR_NOTIFICATION_COMPLETION = 3, 341 MB_RES_MSG_SUCCESS = 4, 342 MB_RES_MSG_FAIL = 5, 343 MB_RES_MSG_QUERY_ALIVE = 6, 344 MB_RES_MSG_GPU_INIT_DATA_READY = 7, 345 MB_RES_MSG_RAS_POISON_READY = 8, 346 MB_RES_MSG_PF_SOFT_FLR_NOTIFICATION = 9, 347 MB_RES_MSG_GPU_RMA = 10, 348 MB_RES_MSG_RAS_ERROR_COUNT_READY = 11, 349 MB_REQ_RAS_CPER_DUMP_READY = 14, 350 MB_RES_MSG_TEXT_MESSAGE = 255 351 }; 352 353 enum amd_sriov_ras_telemetry_gpu_block { 354 RAS_TELEMETRY_GPU_BLOCK_UMC = 0, 355 RAS_TELEMETRY_GPU_BLOCK_SDMA = 1, 356 RAS_TELEMETRY_GPU_BLOCK_GFX = 2, 357 RAS_TELEMETRY_GPU_BLOCK_MMHUB = 3, 358 RAS_TELEMETRY_GPU_BLOCK_ATHUB = 4, 359 RAS_TELEMETRY_GPU_BLOCK_PCIE_BIF = 5, 360 RAS_TELEMETRY_GPU_BLOCK_HDP = 6, 361 RAS_TELEMETRY_GPU_BLOCK_XGMI_WAFL = 7, 362 RAS_TELEMETRY_GPU_BLOCK_DF = 8, 363 RAS_TELEMETRY_GPU_BLOCK_SMN = 9, 364 RAS_TELEMETRY_GPU_BLOCK_SEM = 10, 365 RAS_TELEMETRY_GPU_BLOCK_MP0 = 11, 366 RAS_TELEMETRY_GPU_BLOCK_MP1 = 12, 367 RAS_TELEMETRY_GPU_BLOCK_FUSE = 13, 368 RAS_TELEMETRY_GPU_BLOCK_MCA = 14, 369 RAS_TELEMETRY_GPU_BLOCK_VCN = 15, 370 RAS_TELEMETRY_GPU_BLOCK_JPEG = 16, 371 RAS_TELEMETRY_GPU_BLOCK_IH = 17, 372 RAS_TELEMETRY_GPU_BLOCK_MPIO = 18, 373 RAS_TELEMETRY_GPU_BLOCK_COUNT = 19, 374 }; 375 376 struct amd_sriov_ras_telemetry_header { 377 uint32_t checksum; 378 uint32_t used_size; 379 uint32_t reserved[2]; 380 }; 381 382 struct amd_sriov_ras_telemetry_error_count { 383 struct { 384 uint32_t ce_count; 385 uint32_t ue_count; 386 uint32_t de_count; 387 uint32_t ce_overflow_count; 388 uint32_t ue_overflow_count; 389 uint32_t de_overflow_count; 390 uint32_t reserved[6]; 391 } block[RAS_TELEMETRY_GPU_BLOCK_COUNT]; 392 }; 393 394 struct amd_sriov_ras_cper_dump { 395 uint32_t more; 396 uint64_t overflow_count; 397 uint64_t count; 398 uint64_t wptr; 399 uint32_t buf[]; 400 }; 401 402 struct amdsriov_ras_telemetry { 403 struct amd_sriov_ras_telemetry_header header; 404 405 union { 406 struct amd_sriov_ras_telemetry_error_count error_count; 407 struct amd_sriov_ras_cper_dump cper_dump; 408 } body; 409 }; 410 411 /* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */ 412 enum amd_sriov_gpu_init_data_version { 413 GPU_INIT_DATA_READY_V1 = 1, 414 }; 415 416 #pragma pack(pop) // Restore previous packing option 417 418 /* checksum function between host and guest */ 419 unsigned int amd_sriov_msg_checksum(void *obj, unsigned long obj_size, unsigned int key, 420 unsigned int checksum); 421 422 /* assertion at compile time */ 423 #ifdef __linux__ 424 #define stringification(s) _stringification(s) 425 #define _stringification(s) #s 426 427 _Static_assert( 428 sizeof(struct amd_sriov_msg_vf2pf_info) == AMD_SRIOV_MSG_SIZE_KB << 10, 429 "amd_sriov_msg_vf2pf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB"); 430 431 _Static_assert( 432 sizeof(struct amd_sriov_msg_pf2vf_info) == AMD_SRIOV_MSG_SIZE_KB << 10, 433 "amd_sriov_msg_pf2vf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB"); 434 435 _Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE % 4 == 0, 436 "AMD_SRIOV_MSG_RESERVE_UCODE must be multiple of 4"); 437 438 _Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE > AMD_SRIOV_UCODE_ID__MAX, 439 "AMD_SRIOV_MSG_RESERVE_UCODE must be bigger than AMD_SRIOV_UCODE_ID__MAX"); 440 441 #undef _stringification 442 #undef stringification 443 #endif 444 445 #endif /* AMDGV_SRIOV_MSG__H_ */ 446