1 // SPDX-License-Identifier: GPL-2.0
2 /* SandyBridge-EP/IvyTown uncore support */
3 #include <asm/cpu_device_id.h>
4 #include <asm/msr.h>
5 #include "uncore.h"
6 #include "uncore_discovery.h"
7
8 /* SNB-EP pci bus to socket mapping */
9 #define SNBEP_CPUNODEID 0x40
10 #define SNBEP_GIDNIDMAP 0x54
11
12 /* SNB-EP Box level control */
13 #define SNBEP_PMON_BOX_CTL_RST_CTRL (1 << 0)
14 #define SNBEP_PMON_BOX_CTL_RST_CTRS (1 << 1)
15 #define SNBEP_PMON_BOX_CTL_FRZ (1 << 8)
16 #define SNBEP_PMON_BOX_CTL_FRZ_EN (1 << 16)
17 #define SNBEP_PMON_BOX_CTL_INT (SNBEP_PMON_BOX_CTL_RST_CTRL | \
18 SNBEP_PMON_BOX_CTL_RST_CTRS | \
19 SNBEP_PMON_BOX_CTL_FRZ_EN)
20 /* SNB-EP event control */
21 #define SNBEP_PMON_CTL_EV_SEL_MASK 0x000000ff
22 #define SNBEP_PMON_CTL_UMASK_MASK 0x0000ff00
23 #define SNBEP_PMON_CTL_RST (1 << 17)
24 #define SNBEP_PMON_CTL_EDGE_DET (1 << 18)
25 #define SNBEP_PMON_CTL_EV_SEL_EXT (1 << 21)
26 #define SNBEP_PMON_CTL_EN (1 << 22)
27 #define SNBEP_PMON_CTL_INVERT (1 << 23)
28 #define SNBEP_PMON_CTL_TRESH_MASK 0xff000000
29 #define SNBEP_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \
30 SNBEP_PMON_CTL_UMASK_MASK | \
31 SNBEP_PMON_CTL_EDGE_DET | \
32 SNBEP_PMON_CTL_INVERT | \
33 SNBEP_PMON_CTL_TRESH_MASK)
34
35 /* SNB-EP Ubox event control */
36 #define SNBEP_U_MSR_PMON_CTL_TRESH_MASK 0x1f000000
37 #define SNBEP_U_MSR_PMON_RAW_EVENT_MASK \
38 (SNBEP_PMON_CTL_EV_SEL_MASK | \
39 SNBEP_PMON_CTL_UMASK_MASK | \
40 SNBEP_PMON_CTL_EDGE_DET | \
41 SNBEP_PMON_CTL_INVERT | \
42 SNBEP_U_MSR_PMON_CTL_TRESH_MASK)
43
44 #define SNBEP_CBO_PMON_CTL_TID_EN (1 << 19)
45 #define SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \
46 SNBEP_CBO_PMON_CTL_TID_EN)
47
48 /* SNB-EP PCU event control */
49 #define SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK 0x0000c000
50 #define SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK 0x1f000000
51 #define SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT (1 << 30)
52 #define SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET (1 << 31)
53 #define SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK \
54 (SNBEP_PMON_CTL_EV_SEL_MASK | \
55 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
56 SNBEP_PMON_CTL_EDGE_DET | \
57 SNBEP_PMON_CTL_INVERT | \
58 SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \
59 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
60 SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)
61
62 #define SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK \
63 (SNBEP_PMON_RAW_EVENT_MASK | \
64 SNBEP_PMON_CTL_EV_SEL_EXT)
65
66 /* SNB-EP pci control register */
67 #define SNBEP_PCI_PMON_BOX_CTL 0xf4
68 #define SNBEP_PCI_PMON_CTL0 0xd8
69 /* SNB-EP pci counter register */
70 #define SNBEP_PCI_PMON_CTR0 0xa0
71
72 /* SNB-EP home agent register */
73 #define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH0 0x40
74 #define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH1 0x44
75 #define SNBEP_HA_PCI_PMON_BOX_OPCODEMATCH 0x48
76 /* SNB-EP memory controller register */
77 #define SNBEP_MC_CHy_PCI_PMON_FIXED_CTL 0xf0
78 #define SNBEP_MC_CHy_PCI_PMON_FIXED_CTR 0xd0
79 /* SNB-EP QPI register */
80 #define SNBEP_Q_Py_PCI_PMON_PKT_MATCH0 0x228
81 #define SNBEP_Q_Py_PCI_PMON_PKT_MATCH1 0x22c
82 #define SNBEP_Q_Py_PCI_PMON_PKT_MASK0 0x238
83 #define SNBEP_Q_Py_PCI_PMON_PKT_MASK1 0x23c
84
85 /* SNB-EP Ubox register */
86 #define SNBEP_U_MSR_PMON_CTR0 0xc16
87 #define SNBEP_U_MSR_PMON_CTL0 0xc10
88
89 #define SNBEP_U_MSR_PMON_UCLK_FIXED_CTL 0xc08
90 #define SNBEP_U_MSR_PMON_UCLK_FIXED_CTR 0xc09
91
92 /* SNB-EP Cbo register */
93 #define SNBEP_C0_MSR_PMON_CTR0 0xd16
94 #define SNBEP_C0_MSR_PMON_CTL0 0xd10
95 #define SNBEP_C0_MSR_PMON_BOX_CTL 0xd04
96 #define SNBEP_C0_MSR_PMON_BOX_FILTER 0xd14
97 #define SNBEP_CBO_MSR_OFFSET 0x20
98
99 #define SNBEP_CB0_MSR_PMON_BOX_FILTER_TID 0x1f
100 #define SNBEP_CB0_MSR_PMON_BOX_FILTER_NID 0x3fc00
101 #define SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE 0x7c0000
102 #define SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC 0xff800000
103
104 #define SNBEP_CBO_EVENT_EXTRA_REG(e, m, i) { \
105 .event = (e), \
106 .msr = SNBEP_C0_MSR_PMON_BOX_FILTER, \
107 .config_mask = (m), \
108 .idx = (i) \
109 }
110
111 /* SNB-EP PCU register */
112 #define SNBEP_PCU_MSR_PMON_CTR0 0xc36
113 #define SNBEP_PCU_MSR_PMON_CTL0 0xc30
114 #define SNBEP_PCU_MSR_PMON_BOX_CTL 0xc24
115 #define SNBEP_PCU_MSR_PMON_BOX_FILTER 0xc34
116 #define SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK 0xffffffff
117 #define SNBEP_PCU_MSR_CORE_C3_CTR 0x3fc
118 #define SNBEP_PCU_MSR_CORE_C6_CTR 0x3fd
119
120 /* IVBEP event control */
121 #define IVBEP_PMON_BOX_CTL_INT (SNBEP_PMON_BOX_CTL_RST_CTRL | \
122 SNBEP_PMON_BOX_CTL_RST_CTRS)
123 #define IVBEP_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \
124 SNBEP_PMON_CTL_UMASK_MASK | \
125 SNBEP_PMON_CTL_EDGE_DET | \
126 SNBEP_PMON_CTL_TRESH_MASK)
127 /* IVBEP Ubox */
128 #define IVBEP_U_MSR_PMON_GLOBAL_CTL 0xc00
129 #define IVBEP_U_PMON_GLOBAL_FRZ_ALL (1 << 31)
130 #define IVBEP_U_PMON_GLOBAL_UNFRZ_ALL (1 << 29)
131
132 #define IVBEP_U_MSR_PMON_RAW_EVENT_MASK \
133 (SNBEP_PMON_CTL_EV_SEL_MASK | \
134 SNBEP_PMON_CTL_UMASK_MASK | \
135 SNBEP_PMON_CTL_EDGE_DET | \
136 SNBEP_U_MSR_PMON_CTL_TRESH_MASK)
137 /* IVBEP Cbo */
138 #define IVBEP_CBO_MSR_PMON_RAW_EVENT_MASK (IVBEP_PMON_RAW_EVENT_MASK | \
139 SNBEP_CBO_PMON_CTL_TID_EN)
140
141 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_TID (0x1fULL << 0)
142 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_LINK (0xfULL << 5)
143 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_STATE (0x3fULL << 17)
144 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_NID (0xffffULL << 32)
145 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_OPC (0x1ffULL << 52)
146 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61)
147 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62)
148 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_ISOC (0x1ULL << 63)
149
150 /* IVBEP home agent */
151 #define IVBEP_HA_PCI_PMON_CTL_Q_OCC_RST (1 << 16)
152 #define IVBEP_HA_PCI_PMON_RAW_EVENT_MASK \
153 (IVBEP_PMON_RAW_EVENT_MASK | \
154 IVBEP_HA_PCI_PMON_CTL_Q_OCC_RST)
155 /* IVBEP PCU */
156 #define IVBEP_PCU_MSR_PMON_RAW_EVENT_MASK \
157 (SNBEP_PMON_CTL_EV_SEL_MASK | \
158 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
159 SNBEP_PMON_CTL_EDGE_DET | \
160 SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \
161 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
162 SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)
163 /* IVBEP QPI */
164 #define IVBEP_QPI_PCI_PMON_RAW_EVENT_MASK \
165 (IVBEP_PMON_RAW_EVENT_MASK | \
166 SNBEP_PMON_CTL_EV_SEL_EXT)
167
168 #define __BITS_VALUE(x, i, n) ((typeof(x))(((x) >> ((i) * (n))) & \
169 ((1ULL << (n)) - 1)))
170
171 /* Haswell-EP Ubox */
172 #define HSWEP_U_MSR_PMON_CTR0 0x709
173 #define HSWEP_U_MSR_PMON_CTL0 0x705
174 #define HSWEP_U_MSR_PMON_FILTER 0x707
175
176 #define HSWEP_U_MSR_PMON_UCLK_FIXED_CTL 0x703
177 #define HSWEP_U_MSR_PMON_UCLK_FIXED_CTR 0x704
178
179 #define HSWEP_U_MSR_PMON_BOX_FILTER_TID (0x1 << 0)
180 #define HSWEP_U_MSR_PMON_BOX_FILTER_CID (0x1fULL << 1)
181 #define HSWEP_U_MSR_PMON_BOX_FILTER_MASK \
182 (HSWEP_U_MSR_PMON_BOX_FILTER_TID | \
183 HSWEP_U_MSR_PMON_BOX_FILTER_CID)
184
185 /* Haswell-EP CBo */
186 #define HSWEP_C0_MSR_PMON_CTR0 0xe08
187 #define HSWEP_C0_MSR_PMON_CTL0 0xe01
188 #define HSWEP_C0_MSR_PMON_BOX_CTL 0xe00
189 #define HSWEP_C0_MSR_PMON_BOX_FILTER0 0xe05
190 #define HSWEP_CBO_MSR_OFFSET 0x10
191
192
193 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_TID (0x3fULL << 0)
194 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_LINK (0xfULL << 6)
195 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_STATE (0x7fULL << 17)
196 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_NID (0xffffULL << 32)
197 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_OPC (0x1ffULL << 52)
198 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61)
199 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62)
200 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_ISOC (0x1ULL << 63)
201
202
203 /* Haswell-EP Sbox */
204 #define HSWEP_S0_MSR_PMON_CTR0 0x726
205 #define HSWEP_S0_MSR_PMON_CTL0 0x721
206 #define HSWEP_S0_MSR_PMON_BOX_CTL 0x720
207 #define HSWEP_SBOX_MSR_OFFSET 0xa
208 #define HSWEP_S_MSR_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \
209 SNBEP_CBO_PMON_CTL_TID_EN)
210
211 /* Haswell-EP PCU */
212 #define HSWEP_PCU_MSR_PMON_CTR0 0x717
213 #define HSWEP_PCU_MSR_PMON_CTL0 0x711
214 #define HSWEP_PCU_MSR_PMON_BOX_CTL 0x710
215 #define HSWEP_PCU_MSR_PMON_BOX_FILTER 0x715
216
217 /* KNL Ubox */
218 #define KNL_U_MSR_PMON_RAW_EVENT_MASK \
219 (SNBEP_U_MSR_PMON_RAW_EVENT_MASK | \
220 SNBEP_CBO_PMON_CTL_TID_EN)
221 /* KNL CHA */
222 #define KNL_CHA_MSR_OFFSET 0xc
223 #define KNL_CHA_MSR_PMON_CTL_QOR (1 << 16)
224 #define KNL_CHA_MSR_PMON_RAW_EVENT_MASK \
225 (SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK | \
226 KNL_CHA_MSR_PMON_CTL_QOR)
227 #define KNL_CHA_MSR_PMON_BOX_FILTER_TID 0x1ff
228 #define KNL_CHA_MSR_PMON_BOX_FILTER_STATE (7 << 18)
229 #define KNL_CHA_MSR_PMON_BOX_FILTER_OP (0xfffffe2aULL << 32)
230 #define KNL_CHA_MSR_PMON_BOX_FILTER_REMOTE_NODE (0x1ULL << 32)
231 #define KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE (0x1ULL << 33)
232 #define KNL_CHA_MSR_PMON_BOX_FILTER_NNC (0x1ULL << 37)
233
234 /* KNL EDC/MC UCLK */
235 #define KNL_UCLK_MSR_PMON_CTR0_LOW 0x400
236 #define KNL_UCLK_MSR_PMON_CTL0 0x420
237 #define KNL_UCLK_MSR_PMON_BOX_CTL 0x430
238 #define KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW 0x44c
239 #define KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL 0x454
240 #define KNL_PMON_FIXED_CTL_EN 0x1
241
242 /* KNL EDC */
243 #define KNL_EDC0_ECLK_MSR_PMON_CTR0_LOW 0xa00
244 #define KNL_EDC0_ECLK_MSR_PMON_CTL0 0xa20
245 #define KNL_EDC0_ECLK_MSR_PMON_BOX_CTL 0xa30
246 #define KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_LOW 0xa3c
247 #define KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_CTL 0xa44
248
249 /* KNL MC */
250 #define KNL_MC0_CH0_MSR_PMON_CTR0_LOW 0xb00
251 #define KNL_MC0_CH0_MSR_PMON_CTL0 0xb20
252 #define KNL_MC0_CH0_MSR_PMON_BOX_CTL 0xb30
253 #define KNL_MC0_CH0_MSR_PMON_FIXED_LOW 0xb3c
254 #define KNL_MC0_CH0_MSR_PMON_FIXED_CTL 0xb44
255
256 /* KNL IRP */
257 #define KNL_IRP_PCI_PMON_BOX_CTL 0xf0
258 #define KNL_IRP_PCI_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \
259 KNL_CHA_MSR_PMON_CTL_QOR)
260 /* KNL PCU */
261 #define KNL_PCU_PMON_CTL_EV_SEL_MASK 0x0000007f
262 #define KNL_PCU_PMON_CTL_USE_OCC_CTR (1 << 7)
263 #define KNL_PCU_MSR_PMON_CTL_TRESH_MASK 0x3f000000
264 #define KNL_PCU_MSR_PMON_RAW_EVENT_MASK \
265 (KNL_PCU_PMON_CTL_EV_SEL_MASK | \
266 KNL_PCU_PMON_CTL_USE_OCC_CTR | \
267 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
268 SNBEP_PMON_CTL_EDGE_DET | \
269 SNBEP_CBO_PMON_CTL_TID_EN | \
270 SNBEP_PMON_CTL_INVERT | \
271 KNL_PCU_MSR_PMON_CTL_TRESH_MASK | \
272 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
273 SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)
274
275 /* SKX pci bus to socket mapping */
276 #define SKX_CPUNODEID 0xc0
277 #define SKX_GIDNIDMAP 0xd4
278
279 /*
280 * The CPU_BUS_NUMBER MSR returns the values of the respective CPUBUSNO CSR
281 * that BIOS programmed. MSR has package scope.
282 * | Bit | Default | Description
283 * | [63] | 00h | VALID - When set, indicates the CPU bus
284 * numbers have been initialized. (RO)
285 * |[62:48]| --- | Reserved
286 * |[47:40]| 00h | BUS_NUM_5 - Return the bus number BIOS assigned
287 * CPUBUSNO(5). (RO)
288 * |[39:32]| 00h | BUS_NUM_4 - Return the bus number BIOS assigned
289 * CPUBUSNO(4). (RO)
290 * |[31:24]| 00h | BUS_NUM_3 - Return the bus number BIOS assigned
291 * CPUBUSNO(3). (RO)
292 * |[23:16]| 00h | BUS_NUM_2 - Return the bus number BIOS assigned
293 * CPUBUSNO(2). (RO)
294 * |[15:8] | 00h | BUS_NUM_1 - Return the bus number BIOS assigned
295 * CPUBUSNO(1). (RO)
296 * | [7:0] | 00h | BUS_NUM_0 - Return the bus number BIOS assigned
297 * CPUBUSNO(0). (RO)
298 */
299 #define SKX_MSR_CPU_BUS_NUMBER 0x300
300 #define SKX_MSR_CPU_BUS_VALID_BIT (1ULL << 63)
301 #define BUS_NUM_STRIDE 8
302
303 /* SKX CHA */
304 #define SKX_CHA_MSR_PMON_BOX_FILTER_TID (0x1ffULL << 0)
305 #define SKX_CHA_MSR_PMON_BOX_FILTER_LINK (0xfULL << 9)
306 #define SKX_CHA_MSR_PMON_BOX_FILTER_STATE (0x3ffULL << 17)
307 #define SKX_CHA_MSR_PMON_BOX_FILTER_REM (0x1ULL << 32)
308 #define SKX_CHA_MSR_PMON_BOX_FILTER_LOC (0x1ULL << 33)
309 #define SKX_CHA_MSR_PMON_BOX_FILTER_ALL_OPC (0x1ULL << 35)
310 #define SKX_CHA_MSR_PMON_BOX_FILTER_NM (0x1ULL << 36)
311 #define SKX_CHA_MSR_PMON_BOX_FILTER_NOT_NM (0x1ULL << 37)
312 #define SKX_CHA_MSR_PMON_BOX_FILTER_OPC0 (0x3ffULL << 41)
313 #define SKX_CHA_MSR_PMON_BOX_FILTER_OPC1 (0x3ffULL << 51)
314 #define SKX_CHA_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61)
315 #define SKX_CHA_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62)
316 #define SKX_CHA_MSR_PMON_BOX_FILTER_ISOC (0x1ULL << 63)
317
318 /* SKX IIO */
319 #define SKX_IIO0_MSR_PMON_CTL0 0xa48
320 #define SKX_IIO0_MSR_PMON_CTR0 0xa41
321 #define SKX_IIO0_MSR_PMON_BOX_CTL 0xa40
322 #define SKX_IIO_MSR_OFFSET 0x20
323
324 #define SKX_PMON_CTL_TRESH_MASK (0xff << 24)
325 #define SKX_PMON_CTL_TRESH_MASK_EXT (0xf)
326 #define SKX_PMON_CTL_CH_MASK (0xff << 4)
327 #define SKX_PMON_CTL_FC_MASK (0x7 << 12)
328 #define SKX_IIO_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \
329 SNBEP_PMON_CTL_UMASK_MASK | \
330 SNBEP_PMON_CTL_EDGE_DET | \
331 SNBEP_PMON_CTL_INVERT | \
332 SKX_PMON_CTL_TRESH_MASK)
333 #define SKX_IIO_PMON_RAW_EVENT_MASK_EXT (SKX_PMON_CTL_TRESH_MASK_EXT | \
334 SKX_PMON_CTL_CH_MASK | \
335 SKX_PMON_CTL_FC_MASK)
336
337 /* SKX IRP */
338 #define SKX_IRP0_MSR_PMON_CTL0 0xa5b
339 #define SKX_IRP0_MSR_PMON_CTR0 0xa59
340 #define SKX_IRP0_MSR_PMON_BOX_CTL 0xa58
341 #define SKX_IRP_MSR_OFFSET 0x20
342
343 /* SKX UPI */
344 #define SKX_UPI_PCI_PMON_CTL0 0x350
345 #define SKX_UPI_PCI_PMON_CTR0 0x318
346 #define SKX_UPI_PCI_PMON_BOX_CTL 0x378
347 #define SKX_UPI_CTL_UMASK_EXT 0xffefff
348
349 /* SKX M2M */
350 #define SKX_M2M_PCI_PMON_CTL0 0x228
351 #define SKX_M2M_PCI_PMON_CTR0 0x200
352 #define SKX_M2M_PCI_PMON_BOX_CTL 0x258
353
354 /* Memory Map registers device ID */
355 #define SNR_ICX_MESH2IIO_MMAP_DID 0x9a2
356 #define SNR_ICX_SAD_CONTROL_CFG 0x3f4
357
358 /* Getting I/O stack id in SAD_COTROL_CFG notation */
359 #define SAD_CONTROL_STACK_ID(data) (((data) >> 4) & 0x7)
360
361 /* SNR Ubox */
362 #define SNR_U_MSR_PMON_CTR0 0x1f98
363 #define SNR_U_MSR_PMON_CTL0 0x1f91
364 #define SNR_U_MSR_PMON_UCLK_FIXED_CTL 0x1f93
365 #define SNR_U_MSR_PMON_UCLK_FIXED_CTR 0x1f94
366
367 /* SNR CHA */
368 #define SNR_CHA_RAW_EVENT_MASK_EXT 0x3ffffff
369 #define SNR_CHA_MSR_PMON_CTL0 0x1c01
370 #define SNR_CHA_MSR_PMON_CTR0 0x1c08
371 #define SNR_CHA_MSR_PMON_BOX_CTL 0x1c00
372 #define SNR_C0_MSR_PMON_BOX_FILTER0 0x1c05
373
374
375 /* SNR IIO */
376 #define SNR_IIO_MSR_PMON_CTL0 0x1e08
377 #define SNR_IIO_MSR_PMON_CTR0 0x1e01
378 #define SNR_IIO_MSR_PMON_BOX_CTL 0x1e00
379 #define SNR_IIO_MSR_OFFSET 0x10
380 #define SNR_IIO_PMON_RAW_EVENT_MASK_EXT 0x7ffff
381
382 /* SNR IRP */
383 #define SNR_IRP0_MSR_PMON_CTL0 0x1ea8
384 #define SNR_IRP0_MSR_PMON_CTR0 0x1ea1
385 #define SNR_IRP0_MSR_PMON_BOX_CTL 0x1ea0
386 #define SNR_IRP_MSR_OFFSET 0x10
387
388 /* SNR M2PCIE */
389 #define SNR_M2PCIE_MSR_PMON_CTL0 0x1e58
390 #define SNR_M2PCIE_MSR_PMON_CTR0 0x1e51
391 #define SNR_M2PCIE_MSR_PMON_BOX_CTL 0x1e50
392 #define SNR_M2PCIE_MSR_OFFSET 0x10
393
394 /* SNR PCU */
395 #define SNR_PCU_MSR_PMON_CTL0 0x1ef1
396 #define SNR_PCU_MSR_PMON_CTR0 0x1ef8
397 #define SNR_PCU_MSR_PMON_BOX_CTL 0x1ef0
398 #define SNR_PCU_MSR_PMON_BOX_FILTER 0x1efc
399
400 /* SNR M2M */
401 #define SNR_M2M_PCI_PMON_CTL0 0x468
402 #define SNR_M2M_PCI_PMON_CTR0 0x440
403 #define SNR_M2M_PCI_PMON_BOX_CTL 0x438
404 #define SNR_M2M_PCI_PMON_UMASK_EXT 0xff
405
406 /* SNR PCIE3 */
407 #define SNR_PCIE3_PCI_PMON_CTL0 0x508
408 #define SNR_PCIE3_PCI_PMON_CTR0 0x4e8
409 #define SNR_PCIE3_PCI_PMON_BOX_CTL 0x4e0
410
411 /* SNR IMC */
412 #define SNR_IMC_MMIO_PMON_FIXED_CTL 0x54
413 #define SNR_IMC_MMIO_PMON_FIXED_CTR 0x38
414 #define SNR_IMC_MMIO_PMON_CTL0 0x40
415 #define SNR_IMC_MMIO_PMON_CTR0 0x8
416 #define SNR_IMC_MMIO_PMON_BOX_CTL 0x22800
417 #define SNR_IMC_MMIO_OFFSET 0x4000
418 #define SNR_IMC_MMIO_SIZE 0x4000
419 #define SNR_IMC_MMIO_BASE_OFFSET 0xd0
420 #define SNR_IMC_MMIO_BASE_MASK 0x1FFFFFFF
421 #define SNR_IMC_MMIO_MEM0_OFFSET 0xd8
422 #define SNR_IMC_MMIO_MEM0_MASK 0x7FF
423
424 /* ICX CHA */
425 #define ICX_C34_MSR_PMON_CTR0 0xb68
426 #define ICX_C34_MSR_PMON_CTL0 0xb61
427 #define ICX_C34_MSR_PMON_BOX_CTL 0xb60
428 #define ICX_C34_MSR_PMON_BOX_FILTER0 0xb65
429
430 /* ICX IIO */
431 #define ICX_IIO_MSR_PMON_CTL0 0xa58
432 #define ICX_IIO_MSR_PMON_CTR0 0xa51
433 #define ICX_IIO_MSR_PMON_BOX_CTL 0xa50
434
435 /* ICX IRP */
436 #define ICX_IRP0_MSR_PMON_CTL0 0xa4d
437 #define ICX_IRP0_MSR_PMON_CTR0 0xa4b
438 #define ICX_IRP0_MSR_PMON_BOX_CTL 0xa4a
439
440 /* ICX M2PCIE */
441 #define ICX_M2PCIE_MSR_PMON_CTL0 0xa46
442 #define ICX_M2PCIE_MSR_PMON_CTR0 0xa41
443 #define ICX_M2PCIE_MSR_PMON_BOX_CTL 0xa40
444
445 /* ICX UPI */
446 #define ICX_UPI_PCI_PMON_CTL0 0x350
447 #define ICX_UPI_PCI_PMON_CTR0 0x320
448 #define ICX_UPI_PCI_PMON_BOX_CTL 0x318
449 #define ICX_UPI_CTL_UMASK_EXT 0xffffff
450 #define ICX_UBOX_DID 0x3450
451
452 /* ICX M3UPI*/
453 #define ICX_M3UPI_PCI_PMON_CTL0 0xd8
454 #define ICX_M3UPI_PCI_PMON_CTR0 0xa8
455 #define ICX_M3UPI_PCI_PMON_BOX_CTL 0xa0
456
457 /* ICX IMC */
458 #define ICX_NUMBER_IMC_CHN 3
459 #define ICX_IMC_MEM_STRIDE 0x4
460
461 /* SPR */
462 #define SPR_RAW_EVENT_MASK_EXT 0xffffff
463 #define SPR_UBOX_DID 0x3250
464
465 /* SPR CHA */
466 #define SPR_CHA_EVENT_MASK_EXT 0xffffffff
467 #define SPR_CHA_PMON_CTL_TID_EN (1 << 16)
468 #define SPR_CHA_PMON_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \
469 SPR_CHA_PMON_CTL_TID_EN)
470 #define SPR_CHA_PMON_BOX_FILTER_TID 0x3ff
471
472 #define SPR_C0_MSR_PMON_BOX_FILTER0 0x200e
473
474 /* DMR */
475 #define DMR_IMH1_HIOP_MMIO_BASE 0x1ffff6ae7000
476 #define DMR_HIOP_MMIO_SIZE 0x8000
477 #define DMR_CXLCM_PMON_CTL_INVERT BIT(21)
478 #define DMR_CXLCM_PMON_RAW_EVENT_MASK (GENERIC_PMON_RAW_EVENT_MASK | \
479 DMR_CXLCM_PMON_CTL_INVERT)
480 #define DMR_CXLCM_EVENT_MASK_EXT 0xf
481 #define DMR_HAMVF_EVENT_MASK_EXT 0xffffffff
482 #define DMR_PCIE4_EVENT_MASK_EXT 0xffffff
483
484 #define UNCORE_DMR_ITC 0x30
485
486 #define DMR_IMC_PMON_FIXED_CTR 0x18
487 #define DMR_IMC_PMON_FIXED_CTL 0x10
488
489 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
490 DEFINE_UNCORE_FORMAT_ATTR(event2, event, "config:0-6");
491 DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21");
492 DEFINE_UNCORE_FORMAT_ATTR(use_occ_ctr, use_occ_ctr, "config:7");
493 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
494 DEFINE_UNCORE_FORMAT_ATTR(umask_ext, umask, "config:8-15,32-43,45-55");
495 DEFINE_UNCORE_FORMAT_ATTR(umask_ext2, umask, "config:8-15,32-57");
496 DEFINE_UNCORE_FORMAT_ATTR(umask_ext3, umask, "config:8-15,32-39");
497 DEFINE_UNCORE_FORMAT_ATTR(umask_ext4, umask, "config:8-15,32-55");
498 DEFINE_UNCORE_FORMAT_ATTR(umask_ext5, umask, "config:8-15,32-63");
499 DEFINE_UNCORE_FORMAT_ATTR(qor, qor, "config:16");
500 DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
501 DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19");
502 DEFINE_UNCORE_FORMAT_ATTR(tid_en2, tid_en, "config:16");
503 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
504 DEFINE_UNCORE_FORMAT_ATTR(inv2, inv, "config:21");
505 DEFINE_UNCORE_FORMAT_ATTR(thresh_ext, thresh_ext, "config:32-35");
506 DEFINE_UNCORE_FORMAT_ATTR(thresh10, thresh, "config:23-32");
507 DEFINE_UNCORE_FORMAT_ATTR(thresh9_2, thresh, "config:23-31");
508 DEFINE_UNCORE_FORMAT_ATTR(thresh9, thresh, "config:24-35");
509 DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31");
510 DEFINE_UNCORE_FORMAT_ATTR(thresh6, thresh, "config:24-29");
511 DEFINE_UNCORE_FORMAT_ATTR(thresh5, thresh, "config:24-28");
512 DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
513 DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
514 DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
515 DEFINE_UNCORE_FORMAT_ATTR(occ_edge_det, occ_edge_det, "config:31");
516 DEFINE_UNCORE_FORMAT_ATTR(port_en, port_en, "config:32-35");
517 DEFINE_UNCORE_FORMAT_ATTR(rs3_sel, rs3_sel, "config:36");
518 DEFINE_UNCORE_FORMAT_ATTR(rx_sel, rx_sel, "config:37");
519 DEFINE_UNCORE_FORMAT_ATTR(tx_sel, tx_sel, "config:38");
520 DEFINE_UNCORE_FORMAT_ATTR(iep_sel, iep_sel, "config:39");
521 DEFINE_UNCORE_FORMAT_ATTR(vc_sel, vc_sel, "config:40-47");
522 DEFINE_UNCORE_FORMAT_ATTR(port_sel, port_sel, "config:48-55");
523 DEFINE_UNCORE_FORMAT_ATTR(ch_mask, ch_mask, "config:36-43");
524 DEFINE_UNCORE_FORMAT_ATTR(ch_mask2, ch_mask, "config:36-47");
525 DEFINE_UNCORE_FORMAT_ATTR(fc_mask, fc_mask, "config:44-46");
526 DEFINE_UNCORE_FORMAT_ATTR(fc_mask2, fc_mask, "config:48-50");
527 DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4");
528 DEFINE_UNCORE_FORMAT_ATTR(filter_tid2, filter_tid, "config1:0");
529 DEFINE_UNCORE_FORMAT_ATTR(filter_tid3, filter_tid, "config1:0-5");
530 DEFINE_UNCORE_FORMAT_ATTR(filter_tid4, filter_tid, "config1:0-8");
531 DEFINE_UNCORE_FORMAT_ATTR(filter_tid5, filter_tid, "config1:0-9");
532 DEFINE_UNCORE_FORMAT_ATTR(filter_cid, filter_cid, "config1:5");
533 DEFINE_UNCORE_FORMAT_ATTR(filter_link, filter_link, "config1:5-8");
534 DEFINE_UNCORE_FORMAT_ATTR(filter_link2, filter_link, "config1:6-8");
535 DEFINE_UNCORE_FORMAT_ATTR(filter_link3, filter_link, "config1:12");
536 DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17");
537 DEFINE_UNCORE_FORMAT_ATTR(filter_nid2, filter_nid, "config1:32-47");
538 DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22");
539 DEFINE_UNCORE_FORMAT_ATTR(filter_state2, filter_state, "config1:17-22");
540 DEFINE_UNCORE_FORMAT_ATTR(filter_state3, filter_state, "config1:17-23");
541 DEFINE_UNCORE_FORMAT_ATTR(filter_state4, filter_state, "config1:18-20");
542 DEFINE_UNCORE_FORMAT_ATTR(filter_state5, filter_state, "config1:17-26");
543 DEFINE_UNCORE_FORMAT_ATTR(filter_rem, filter_rem, "config1:32");
544 DEFINE_UNCORE_FORMAT_ATTR(filter_loc, filter_loc, "config1:33");
545 DEFINE_UNCORE_FORMAT_ATTR(filter_nm, filter_nm, "config1:36");
546 DEFINE_UNCORE_FORMAT_ATTR(filter_not_nm, filter_not_nm, "config1:37");
547 DEFINE_UNCORE_FORMAT_ATTR(filter_local, filter_local, "config1:33");
548 DEFINE_UNCORE_FORMAT_ATTR(filter_all_op, filter_all_op, "config1:35");
549 DEFINE_UNCORE_FORMAT_ATTR(filter_nnm, filter_nnm, "config1:37");
550 DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31");
551 DEFINE_UNCORE_FORMAT_ATTR(filter_opc2, filter_opc, "config1:52-60");
552 DEFINE_UNCORE_FORMAT_ATTR(filter_opc3, filter_opc, "config1:41-60");
553 DEFINE_UNCORE_FORMAT_ATTR(filter_opc_0, filter_opc0, "config1:41-50");
554 DEFINE_UNCORE_FORMAT_ATTR(filter_opc_1, filter_opc1, "config1:51-60");
555 DEFINE_UNCORE_FORMAT_ATTR(filter_nc, filter_nc, "config1:62");
556 DEFINE_UNCORE_FORMAT_ATTR(filter_c6, filter_c6, "config1:61");
557 DEFINE_UNCORE_FORMAT_ATTR(filter_isoc, filter_isoc, "config1:63");
558 DEFINE_UNCORE_FORMAT_ATTR(filter_band0, filter_band0, "config1:0-7");
559 DEFINE_UNCORE_FORMAT_ATTR(filter_band1, filter_band1, "config1:8-15");
560 DEFINE_UNCORE_FORMAT_ATTR(filter_band2, filter_band2, "config1:16-23");
561 DEFINE_UNCORE_FORMAT_ATTR(filter_band3, filter_band3, "config1:24-31");
562 DEFINE_UNCORE_FORMAT_ATTR(match_rds, match_rds, "config1:48-51");
563 DEFINE_UNCORE_FORMAT_ATTR(match_rnid30, match_rnid30, "config1:32-35");
564 DEFINE_UNCORE_FORMAT_ATTR(match_rnid4, match_rnid4, "config1:31");
565 DEFINE_UNCORE_FORMAT_ATTR(match_dnid, match_dnid, "config1:13-17");
566 DEFINE_UNCORE_FORMAT_ATTR(match_mc, match_mc, "config1:9-12");
567 DEFINE_UNCORE_FORMAT_ATTR(match_opc, match_opc, "config1:5-8");
568 DEFINE_UNCORE_FORMAT_ATTR(match_vnw, match_vnw, "config1:3-4");
569 DEFINE_UNCORE_FORMAT_ATTR(match0, match0, "config1:0-31");
570 DEFINE_UNCORE_FORMAT_ATTR(match1, match1, "config1:32-63");
571 DEFINE_UNCORE_FORMAT_ATTR(mask_rds, mask_rds, "config2:48-51");
572 DEFINE_UNCORE_FORMAT_ATTR(mask_rnid30, mask_rnid30, "config2:32-35");
573 DEFINE_UNCORE_FORMAT_ATTR(mask_rnid4, mask_rnid4, "config2:31");
574 DEFINE_UNCORE_FORMAT_ATTR(mask_dnid, mask_dnid, "config2:13-17");
575 DEFINE_UNCORE_FORMAT_ATTR(mask_mc, mask_mc, "config2:9-12");
576 DEFINE_UNCORE_FORMAT_ATTR(mask_opc, mask_opc, "config2:5-8");
577 DEFINE_UNCORE_FORMAT_ATTR(mask_vnw, mask_vnw, "config2:3-4");
578 DEFINE_UNCORE_FORMAT_ATTR(mask0, mask0, "config2:0-31");
579 DEFINE_UNCORE_FORMAT_ATTR(mask1, mask1, "config2:32-63");
580
snbep_uncore_pci_disable_box(struct intel_uncore_box * box)581 static void snbep_uncore_pci_disable_box(struct intel_uncore_box *box)
582 {
583 struct pci_dev *pdev = box->pci_dev;
584 int box_ctl = uncore_pci_box_ctl(box);
585 u32 config = 0;
586
587 if (!pci_read_config_dword(pdev, box_ctl, &config)) {
588 config |= SNBEP_PMON_BOX_CTL_FRZ;
589 pci_write_config_dword(pdev, box_ctl, config);
590 }
591 }
592
snbep_uncore_pci_enable_box(struct intel_uncore_box * box)593 static void snbep_uncore_pci_enable_box(struct intel_uncore_box *box)
594 {
595 struct pci_dev *pdev = box->pci_dev;
596 int box_ctl = uncore_pci_box_ctl(box);
597 u32 config = 0;
598
599 if (!pci_read_config_dword(pdev, box_ctl, &config)) {
600 config &= ~SNBEP_PMON_BOX_CTL_FRZ;
601 pci_write_config_dword(pdev, box_ctl, config);
602 }
603 }
604
snbep_uncore_pci_enable_event(struct intel_uncore_box * box,struct perf_event * event)605 static void snbep_uncore_pci_enable_event(struct intel_uncore_box *box, struct perf_event *event)
606 {
607 struct pci_dev *pdev = box->pci_dev;
608 struct hw_perf_event *hwc = &event->hw;
609
610 pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
611 }
612
snbep_uncore_pci_disable_event(struct intel_uncore_box * box,struct perf_event * event)613 static void snbep_uncore_pci_disable_event(struct intel_uncore_box *box, struct perf_event *event)
614 {
615 struct pci_dev *pdev = box->pci_dev;
616 struct hw_perf_event *hwc = &event->hw;
617
618 pci_write_config_dword(pdev, hwc->config_base, hwc->config);
619 }
620
snbep_uncore_pci_read_counter(struct intel_uncore_box * box,struct perf_event * event)621 static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box, struct perf_event *event)
622 {
623 struct pci_dev *pdev = box->pci_dev;
624 struct hw_perf_event *hwc = &event->hw;
625 u64 count = 0;
626
627 pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count);
628 pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1);
629
630 return count;
631 }
632
snbep_uncore_pci_init_box(struct intel_uncore_box * box)633 static int snbep_uncore_pci_init_box(struct intel_uncore_box *box)
634 {
635 struct pci_dev *pdev = box->pci_dev;
636 int box_ctl = uncore_pci_box_ctl(box);
637
638 return pci_write_config_dword(pdev, box_ctl, SNBEP_PMON_BOX_CTL_INT);
639 }
640
snbep_uncore_msr_disable_box(struct intel_uncore_box * box)641 static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box)
642 {
643 u64 config;
644 unsigned msr;
645
646 msr = uncore_msr_box_ctl(box);
647 if (msr) {
648 rdmsrq(msr, config);
649 config |= SNBEP_PMON_BOX_CTL_FRZ;
650 wrmsrq(msr, config);
651 }
652 }
653
snbep_uncore_msr_enable_box(struct intel_uncore_box * box)654 static void snbep_uncore_msr_enable_box(struct intel_uncore_box *box)
655 {
656 u64 config;
657 unsigned msr;
658
659 msr = uncore_msr_box_ctl(box);
660 if (msr) {
661 rdmsrq(msr, config);
662 config &= ~SNBEP_PMON_BOX_CTL_FRZ;
663 wrmsrq(msr, config);
664 }
665 }
666
snbep_uncore_msr_enable_event(struct intel_uncore_box * box,struct perf_event * event)667 static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
668 {
669 struct hw_perf_event *hwc = &event->hw;
670 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
671
672 if (reg1->idx != EXTRA_REG_NONE)
673 wrmsrq(reg1->reg, uncore_shared_reg_config(box, 0));
674
675 wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
676 }
677
snbep_uncore_msr_disable_event(struct intel_uncore_box * box,struct perf_event * event)678 static void snbep_uncore_msr_disable_event(struct intel_uncore_box *box,
679 struct perf_event *event)
680 {
681 struct hw_perf_event *hwc = &event->hw;
682
683 wrmsrq(hwc->config_base, hwc->config);
684 }
685
snbep_uncore_msr_init_box(struct intel_uncore_box * box)686 static int snbep_uncore_msr_init_box(struct intel_uncore_box *box)
687 {
688 unsigned msr = uncore_msr_box_ctl(box);
689
690 if (msr)
691 wrmsrq(msr, SNBEP_PMON_BOX_CTL_INT);
692
693 return 0;
694 }
695
696 static struct attribute *snbep_uncore_formats_attr[] = {
697 &format_attr_event.attr,
698 &format_attr_umask.attr,
699 &format_attr_edge.attr,
700 &format_attr_inv.attr,
701 &format_attr_thresh8.attr,
702 NULL,
703 };
704
705 static struct attribute *snbep_uncore_ubox_formats_attr[] = {
706 &format_attr_event.attr,
707 &format_attr_umask.attr,
708 &format_attr_edge.attr,
709 &format_attr_inv.attr,
710 &format_attr_thresh5.attr,
711 NULL,
712 };
713
714 static struct attribute *snbep_uncore_cbox_formats_attr[] = {
715 &format_attr_event.attr,
716 &format_attr_umask.attr,
717 &format_attr_edge.attr,
718 &format_attr_tid_en.attr,
719 &format_attr_inv.attr,
720 &format_attr_thresh8.attr,
721 &format_attr_filter_tid.attr,
722 &format_attr_filter_nid.attr,
723 &format_attr_filter_state.attr,
724 &format_attr_filter_opc.attr,
725 NULL,
726 };
727
728 static struct attribute *snbep_uncore_pcu_formats_attr[] = {
729 &format_attr_event.attr,
730 &format_attr_occ_sel.attr,
731 &format_attr_edge.attr,
732 &format_attr_inv.attr,
733 &format_attr_thresh5.attr,
734 &format_attr_occ_invert.attr,
735 &format_attr_occ_edge.attr,
736 &format_attr_filter_band0.attr,
737 &format_attr_filter_band1.attr,
738 &format_attr_filter_band2.attr,
739 &format_attr_filter_band3.attr,
740 NULL,
741 };
742
743 static struct attribute *snbep_uncore_qpi_formats_attr[] = {
744 &format_attr_event_ext.attr,
745 &format_attr_umask.attr,
746 &format_attr_edge.attr,
747 &format_attr_inv.attr,
748 &format_attr_thresh8.attr,
749 &format_attr_match_rds.attr,
750 &format_attr_match_rnid30.attr,
751 &format_attr_match_rnid4.attr,
752 &format_attr_match_dnid.attr,
753 &format_attr_match_mc.attr,
754 &format_attr_match_opc.attr,
755 &format_attr_match_vnw.attr,
756 &format_attr_match0.attr,
757 &format_attr_match1.attr,
758 &format_attr_mask_rds.attr,
759 &format_attr_mask_rnid30.attr,
760 &format_attr_mask_rnid4.attr,
761 &format_attr_mask_dnid.attr,
762 &format_attr_mask_mc.attr,
763 &format_attr_mask_opc.attr,
764 &format_attr_mask_vnw.attr,
765 &format_attr_mask0.attr,
766 &format_attr_mask1.attr,
767 NULL,
768 };
769
770 static struct uncore_event_desc snbep_uncore_imc_events[] = {
771 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
772 INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x03"),
773 INTEL_UNCORE_EVENT_DESC(cas_count_read.scale, "6.103515625e-5"),
774 INTEL_UNCORE_EVENT_DESC(cas_count_read.unit, "MiB"),
775 INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"),
776 INTEL_UNCORE_EVENT_DESC(cas_count_write.scale, "6.103515625e-5"),
777 INTEL_UNCORE_EVENT_DESC(cas_count_write.unit, "MiB"),
778 { /* end: all zeroes */ },
779 };
780
781 static struct uncore_event_desc snbep_uncore_qpi_events[] = {
782 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x14"),
783 INTEL_UNCORE_EVENT_DESC(txl_flits_active, "event=0x00,umask=0x06"),
784 INTEL_UNCORE_EVENT_DESC(drs_data, "event=0x102,umask=0x08"),
785 INTEL_UNCORE_EVENT_DESC(ncb_data, "event=0x103,umask=0x04"),
786 { /* end: all zeroes */ },
787 };
788
789 static const struct attribute_group snbep_uncore_format_group = {
790 .name = "format",
791 .attrs = snbep_uncore_formats_attr,
792 };
793
794 static const struct attribute_group snbep_uncore_ubox_format_group = {
795 .name = "format",
796 .attrs = snbep_uncore_ubox_formats_attr,
797 };
798
799 static const struct attribute_group snbep_uncore_cbox_format_group = {
800 .name = "format",
801 .attrs = snbep_uncore_cbox_formats_attr,
802 };
803
804 static const struct attribute_group snbep_uncore_pcu_format_group = {
805 .name = "format",
806 .attrs = snbep_uncore_pcu_formats_attr,
807 };
808
809 static const struct attribute_group snbep_uncore_qpi_format_group = {
810 .name = "format",
811 .attrs = snbep_uncore_qpi_formats_attr,
812 };
813
814 #define __SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \
815 .disable_box = snbep_uncore_msr_disable_box, \
816 .enable_box = snbep_uncore_msr_enable_box, \
817 .disable_event = snbep_uncore_msr_disable_event, \
818 .enable_event = snbep_uncore_msr_enable_event, \
819 .read_counter = uncore_msr_read_counter
820
821 #define SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \
822 __SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), \
823 .init_box = snbep_uncore_msr_init_box \
824
825 static struct intel_uncore_ops snbep_uncore_msr_ops = {
826 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
827 };
828
829 #define SNBEP_UNCORE_PCI_OPS_COMMON_INIT() \
830 .init_box = snbep_uncore_pci_init_box, \
831 .disable_box = snbep_uncore_pci_disable_box, \
832 .enable_box = snbep_uncore_pci_enable_box, \
833 .disable_event = snbep_uncore_pci_disable_event, \
834 .read_counter = snbep_uncore_pci_read_counter
835
836 static struct intel_uncore_ops snbep_uncore_pci_ops = {
837 SNBEP_UNCORE_PCI_OPS_COMMON_INIT(),
838 .enable_event = snbep_uncore_pci_enable_event, \
839 };
840
841 static struct event_constraint snbep_uncore_cbox_constraints[] = {
842 UNCORE_EVENT_CONSTRAINT(0x01, 0x1),
843 UNCORE_EVENT_CONSTRAINT(0x02, 0x3),
844 UNCORE_EVENT_CONSTRAINT_RANGE(0x04, 0x5, 0x3),
845 UNCORE_EVENT_CONSTRAINT(0x07, 0x3),
846 UNCORE_EVENT_CONSTRAINT(0x09, 0x3),
847 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
848 UNCORE_EVENT_CONSTRAINT_RANGE(0x12, 0x13, 0x3),
849 UNCORE_EVENT_CONSTRAINT_RANGE(0x1b, 0x1e, 0xc),
850 UNCORE_EVENT_CONSTRAINT(0x1f, 0xe),
851 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
852 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
853 UNCORE_EVENT_CONSTRAINT_RANGE(0x31, 0x35, 0x3),
854 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
855 UNCORE_EVENT_CONSTRAINT_RANGE(0x37, 0x39, 0x3),
856 UNCORE_EVENT_CONSTRAINT(0x3b, 0x1),
857 EVENT_CONSTRAINT_END
858 };
859
860 static struct event_constraint snbep_uncore_r2pcie_constraints[] = {
861 UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x11, 0x3),
862 UNCORE_EVENT_CONSTRAINT(0x12, 0x1),
863 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
864 UNCORE_EVENT_CONSTRAINT_RANGE(0x24, 0x26, 0x3),
865 UNCORE_EVENT_CONSTRAINT_RANGE(0x32, 0x34, 0x3),
866 EVENT_CONSTRAINT_END
867 };
868
869 static struct event_constraint snbep_uncore_r3qpi_constraints[] = {
870 UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x12, 0x3),
871 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
872 UNCORE_EVENT_CONSTRAINT_RANGE(0x20, 0x26, 0x3),
873 UNCORE_EVENT_CONSTRAINT_RANGE(0x28, 0x34, 0x3),
874 UNCORE_EVENT_CONSTRAINT_RANGE(0x36, 0x39, 0x3),
875 EVENT_CONSTRAINT_END
876 };
877
878 static struct intel_uncore_type snbep_uncore_ubox = {
879 .name = "ubox",
880 .num_counters = 2,
881 .num_boxes = 1,
882 .perf_ctr_bits = 44,
883 .fixed_ctr_bits = 48,
884 .perf_ctr = SNBEP_U_MSR_PMON_CTR0,
885 .event_ctl = SNBEP_U_MSR_PMON_CTL0,
886 .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
887 .fixed_ctr = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR,
888 .fixed_ctl = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL,
889 .ops = &snbep_uncore_msr_ops,
890 .format_group = &snbep_uncore_ubox_format_group,
891 };
892
893 static struct extra_reg snbep_uncore_cbox_extra_regs[] = {
894 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
895 SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
896 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
897 SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0x6),
898 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
899 SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0x6),
900 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
901 SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0x6),
902 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x6),
903 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x8),
904 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x8),
905 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0xa),
906 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0xa),
907 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x2),
908 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x2),
909 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x2),
910 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x2),
911 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x8),
912 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x8),
913 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0xa),
914 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0xa),
915 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x2),
916 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x2),
917 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x2),
918 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x2),
919 EVENT_EXTRA_END
920 };
921
snbep_cbox_put_constraint(struct intel_uncore_box * box,struct perf_event * event)922 static void snbep_cbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
923 {
924 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
925 struct intel_uncore_extra_reg *er = &box->shared_regs[0];
926 int i;
927
928 if (uncore_box_is_fake(box))
929 return;
930
931 for (i = 0; i < 5; i++) {
932 if (reg1->alloc & (0x1 << i))
933 atomic_sub(1 << (i * 6), &er->ref);
934 }
935 reg1->alloc = 0;
936 }
937
938 static struct event_constraint *
__snbep_cbox_get_constraint(struct intel_uncore_box * box,struct perf_event * event,u64 (* cbox_filter_mask)(int fields))939 __snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event,
940 u64 (*cbox_filter_mask)(int fields))
941 {
942 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
943 struct intel_uncore_extra_reg *er = &box->shared_regs[0];
944 int i, alloc = 0;
945 unsigned long flags;
946 u64 mask;
947
948 if (reg1->idx == EXTRA_REG_NONE)
949 return NULL;
950
951 raw_spin_lock_irqsave(&er->lock, flags);
952 for (i = 0; i < 5; i++) {
953 if (!(reg1->idx & (0x1 << i)))
954 continue;
955 if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i)))
956 continue;
957
958 mask = cbox_filter_mask(0x1 << i);
959 if (!__BITS_VALUE(atomic_read(&er->ref), i, 6) ||
960 !((reg1->config ^ er->config) & mask)) {
961 atomic_add(1 << (i * 6), &er->ref);
962 er->config &= ~mask;
963 er->config |= reg1->config & mask;
964 alloc |= (0x1 << i);
965 } else {
966 break;
967 }
968 }
969 raw_spin_unlock_irqrestore(&er->lock, flags);
970 if (i < 5)
971 goto fail;
972
973 if (!uncore_box_is_fake(box))
974 reg1->alloc |= alloc;
975
976 return NULL;
977 fail:
978 for (; i >= 0; i--) {
979 if (alloc & (0x1 << i))
980 atomic_sub(1 << (i * 6), &er->ref);
981 }
982 return &uncore_constraint_empty;
983 }
984
snbep_cbox_filter_mask(int fields)985 static u64 snbep_cbox_filter_mask(int fields)
986 {
987 u64 mask = 0;
988
989 if (fields & 0x1)
990 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_TID;
991 if (fields & 0x2)
992 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_NID;
993 if (fields & 0x4)
994 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE;
995 if (fields & 0x8)
996 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC;
997
998 return mask;
999 }
1000
1001 static struct event_constraint *
snbep_cbox_get_constraint(struct intel_uncore_box * box,struct perf_event * event)1002 snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
1003 {
1004 return __snbep_cbox_get_constraint(box, event, snbep_cbox_filter_mask);
1005 }
1006
snbep_cbox_hw_config(struct intel_uncore_box * box,struct perf_event * event)1007 static int snbep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
1008 {
1009 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1010 struct extra_reg *er;
1011 int idx = 0;
1012
1013 for (er = snbep_uncore_cbox_extra_regs; er->msr; er++) {
1014 if (er->event != (event->hw.config & er->config_mask))
1015 continue;
1016 idx |= er->idx;
1017 }
1018
1019 if (idx) {
1020 reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER +
1021 SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
1022 reg1->config = event->attr.config1 & snbep_cbox_filter_mask(idx);
1023 reg1->idx = idx;
1024 }
1025 return 0;
1026 }
1027
1028 static struct intel_uncore_ops snbep_uncore_cbox_ops = {
1029 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
1030 .hw_config = snbep_cbox_hw_config,
1031 .get_constraint = snbep_cbox_get_constraint,
1032 .put_constraint = snbep_cbox_put_constraint,
1033 };
1034
1035 static struct intel_uncore_type snbep_uncore_cbox = {
1036 .name = "cbox",
1037 .num_counters = 4,
1038 .num_boxes = 8,
1039 .perf_ctr_bits = 44,
1040 .event_ctl = SNBEP_C0_MSR_PMON_CTL0,
1041 .perf_ctr = SNBEP_C0_MSR_PMON_CTR0,
1042 .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
1043 .box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL,
1044 .msr_offset = SNBEP_CBO_MSR_OFFSET,
1045 .num_shared_regs = 1,
1046 .constraints = snbep_uncore_cbox_constraints,
1047 .ops = &snbep_uncore_cbox_ops,
1048 .format_group = &snbep_uncore_cbox_format_group,
1049 };
1050
snbep_pcu_alter_er(struct perf_event * event,int new_idx,bool modify)1051 static u64 snbep_pcu_alter_er(struct perf_event *event, int new_idx, bool modify)
1052 {
1053 struct hw_perf_event *hwc = &event->hw;
1054 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1055 u64 config = reg1->config;
1056
1057 if (new_idx > reg1->idx)
1058 config <<= 8 * (new_idx - reg1->idx);
1059 else
1060 config >>= 8 * (reg1->idx - new_idx);
1061
1062 if (modify) {
1063 hwc->config += new_idx - reg1->idx;
1064 reg1->config = config;
1065 reg1->idx = new_idx;
1066 }
1067 return config;
1068 }
1069
1070 static struct event_constraint *
snbep_pcu_get_constraint(struct intel_uncore_box * box,struct perf_event * event)1071 snbep_pcu_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
1072 {
1073 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1074 struct intel_uncore_extra_reg *er = &box->shared_regs[0];
1075 unsigned long flags;
1076 int idx = reg1->idx;
1077 u64 mask, config1 = reg1->config;
1078 bool ok = false;
1079
1080 if (reg1->idx == EXTRA_REG_NONE ||
1081 (!uncore_box_is_fake(box) && reg1->alloc))
1082 return NULL;
1083 again:
1084 mask = 0xffULL << (idx * 8);
1085 raw_spin_lock_irqsave(&er->lock, flags);
1086 if (!__BITS_VALUE(atomic_read(&er->ref), idx, 8) ||
1087 !((config1 ^ er->config) & mask)) {
1088 atomic_add(1 << (idx * 8), &er->ref);
1089 er->config &= ~mask;
1090 er->config |= config1 & mask;
1091 ok = true;
1092 }
1093 raw_spin_unlock_irqrestore(&er->lock, flags);
1094
1095 if (!ok) {
1096 idx = (idx + 1) % 4;
1097 if (idx != reg1->idx) {
1098 config1 = snbep_pcu_alter_er(event, idx, false);
1099 goto again;
1100 }
1101 return &uncore_constraint_empty;
1102 }
1103
1104 if (!uncore_box_is_fake(box)) {
1105 if (idx != reg1->idx)
1106 snbep_pcu_alter_er(event, idx, true);
1107 reg1->alloc = 1;
1108 }
1109 return NULL;
1110 }
1111
snbep_pcu_put_constraint(struct intel_uncore_box * box,struct perf_event * event)1112 static void snbep_pcu_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
1113 {
1114 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1115 struct intel_uncore_extra_reg *er = &box->shared_regs[0];
1116
1117 if (uncore_box_is_fake(box) || !reg1->alloc)
1118 return;
1119
1120 atomic_sub(1 << (reg1->idx * 8), &er->ref);
1121 reg1->alloc = 0;
1122 }
1123
snbep_pcu_hw_config(struct intel_uncore_box * box,struct perf_event * event)1124 static int snbep_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event)
1125 {
1126 struct hw_perf_event *hwc = &event->hw;
1127 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1128 int ev_sel = hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK;
1129
1130 if (ev_sel >= 0xb && ev_sel <= 0xe) {
1131 reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER;
1132 reg1->idx = ev_sel - 0xb;
1133 reg1->config = event->attr.config1 & (0xff << (reg1->idx * 8));
1134 }
1135 return 0;
1136 }
1137
1138 static struct intel_uncore_ops snbep_uncore_pcu_ops = {
1139 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
1140 .hw_config = snbep_pcu_hw_config,
1141 .get_constraint = snbep_pcu_get_constraint,
1142 .put_constraint = snbep_pcu_put_constraint,
1143 };
1144
1145 static struct intel_uncore_type snbep_uncore_pcu = {
1146 .name = "pcu",
1147 .num_counters = 4,
1148 .num_boxes = 1,
1149 .perf_ctr_bits = 48,
1150 .perf_ctr = SNBEP_PCU_MSR_PMON_CTR0,
1151 .event_ctl = SNBEP_PCU_MSR_PMON_CTL0,
1152 .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
1153 .box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL,
1154 .num_shared_regs = 1,
1155 .ops = &snbep_uncore_pcu_ops,
1156 .format_group = &snbep_uncore_pcu_format_group,
1157 };
1158
1159 static struct intel_uncore_type *snbep_msr_uncores[] = {
1160 &snbep_uncore_ubox,
1161 &snbep_uncore_cbox,
1162 &snbep_uncore_pcu,
1163 NULL,
1164 };
1165
snbep_uncore_cpu_init(void)1166 void snbep_uncore_cpu_init(void)
1167 {
1168 if (snbep_uncore_cbox.num_boxes > topology_num_cores_per_package())
1169 snbep_uncore_cbox.num_boxes = topology_num_cores_per_package();
1170 uncore_msr_uncores = snbep_msr_uncores;
1171 }
1172
1173 enum {
1174 SNBEP_PCI_QPI_PORT0_FILTER,
1175 SNBEP_PCI_QPI_PORT1_FILTER,
1176 BDX_PCI_QPI_PORT2_FILTER,
1177 };
1178
snbep_qpi_hw_config(struct intel_uncore_box * box,struct perf_event * event)1179 static int snbep_qpi_hw_config(struct intel_uncore_box *box, struct perf_event *event)
1180 {
1181 struct hw_perf_event *hwc = &event->hw;
1182 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1183 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
1184
1185 if ((hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK) == 0x38) {
1186 reg1->idx = 0;
1187 reg1->reg = SNBEP_Q_Py_PCI_PMON_PKT_MATCH0;
1188 reg1->config = event->attr.config1;
1189 reg2->reg = SNBEP_Q_Py_PCI_PMON_PKT_MASK0;
1190 reg2->config = event->attr.config2;
1191 }
1192 return 0;
1193 }
1194
snbep_qpi_enable_event(struct intel_uncore_box * box,struct perf_event * event)1195 static void snbep_qpi_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1196 {
1197 struct pci_dev *pdev = box->pci_dev;
1198 struct hw_perf_event *hwc = &event->hw;
1199 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1200 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
1201
1202 if (reg1->idx != EXTRA_REG_NONE) {
1203 int idx = box->pmu->pmu_idx + SNBEP_PCI_QPI_PORT0_FILTER;
1204 int die = box->dieid;
1205 struct pci_dev *filter_pdev = uncore_extra_pci_dev[die].dev[idx];
1206
1207 if (filter_pdev) {
1208 pci_write_config_dword(filter_pdev, reg1->reg,
1209 (u32)reg1->config);
1210 pci_write_config_dword(filter_pdev, reg1->reg + 4,
1211 (u32)(reg1->config >> 32));
1212 pci_write_config_dword(filter_pdev, reg2->reg,
1213 (u32)reg2->config);
1214 pci_write_config_dword(filter_pdev, reg2->reg + 4,
1215 (u32)(reg2->config >> 32));
1216 }
1217 }
1218
1219 pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
1220 }
1221
1222 static struct intel_uncore_ops snbep_uncore_qpi_ops = {
1223 SNBEP_UNCORE_PCI_OPS_COMMON_INIT(),
1224 .enable_event = snbep_qpi_enable_event,
1225 .hw_config = snbep_qpi_hw_config,
1226 .get_constraint = uncore_get_constraint,
1227 .put_constraint = uncore_put_constraint,
1228 };
1229
1230 #define SNBEP_UNCORE_PCI_COMMON_INIT() \
1231 .perf_ctr = SNBEP_PCI_PMON_CTR0, \
1232 .event_ctl = SNBEP_PCI_PMON_CTL0, \
1233 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, \
1234 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \
1235 .ops = &snbep_uncore_pci_ops, \
1236 .format_group = &snbep_uncore_format_group
1237
1238 static struct intel_uncore_type snbep_uncore_ha = {
1239 .name = "ha",
1240 .num_counters = 4,
1241 .num_boxes = 1,
1242 .perf_ctr_bits = 48,
1243 SNBEP_UNCORE_PCI_COMMON_INIT(),
1244 };
1245
1246 static struct intel_uncore_type snbep_uncore_imc = {
1247 .name = "imc",
1248 .num_counters = 4,
1249 .num_boxes = 4,
1250 .perf_ctr_bits = 48,
1251 .fixed_ctr_bits = 48,
1252 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
1253 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
1254 .event_descs = snbep_uncore_imc_events,
1255 SNBEP_UNCORE_PCI_COMMON_INIT(),
1256 };
1257
1258 static struct intel_uncore_type snbep_uncore_qpi = {
1259 .name = "qpi",
1260 .num_counters = 4,
1261 .num_boxes = 2,
1262 .perf_ctr_bits = 48,
1263 .perf_ctr = SNBEP_PCI_PMON_CTR0,
1264 .event_ctl = SNBEP_PCI_PMON_CTL0,
1265 .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK,
1266 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
1267 .num_shared_regs = 1,
1268 .ops = &snbep_uncore_qpi_ops,
1269 .event_descs = snbep_uncore_qpi_events,
1270 .format_group = &snbep_uncore_qpi_format_group,
1271 };
1272
1273
1274 static struct intel_uncore_type snbep_uncore_r2pcie = {
1275 .name = "r2pcie",
1276 .num_counters = 4,
1277 .num_boxes = 1,
1278 .perf_ctr_bits = 44,
1279 .constraints = snbep_uncore_r2pcie_constraints,
1280 SNBEP_UNCORE_PCI_COMMON_INIT(),
1281 };
1282
1283 static struct intel_uncore_type snbep_uncore_r3qpi = {
1284 .name = "r3qpi",
1285 .num_counters = 3,
1286 .num_boxes = 2,
1287 .perf_ctr_bits = 44,
1288 .constraints = snbep_uncore_r3qpi_constraints,
1289 SNBEP_UNCORE_PCI_COMMON_INIT(),
1290 };
1291
1292 enum {
1293 SNBEP_PCI_UNCORE_HA,
1294 SNBEP_PCI_UNCORE_IMC,
1295 SNBEP_PCI_UNCORE_QPI,
1296 SNBEP_PCI_UNCORE_R2PCIE,
1297 SNBEP_PCI_UNCORE_R3QPI,
1298 };
1299
1300 static struct intel_uncore_type *snbep_pci_uncores[] = {
1301 [SNBEP_PCI_UNCORE_HA] = &snbep_uncore_ha,
1302 [SNBEP_PCI_UNCORE_IMC] = &snbep_uncore_imc,
1303 [SNBEP_PCI_UNCORE_QPI] = &snbep_uncore_qpi,
1304 [SNBEP_PCI_UNCORE_R2PCIE] = &snbep_uncore_r2pcie,
1305 [SNBEP_PCI_UNCORE_R3QPI] = &snbep_uncore_r3qpi,
1306 NULL,
1307 };
1308
1309 static const struct pci_device_id snbep_uncore_pci_ids[] = {
1310 { /* Home Agent */
1311 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_HA),
1312 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_HA, 0),
1313 },
1314 { /* MC Channel 0 */
1315 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC0),
1316 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 0),
1317 },
1318 { /* MC Channel 1 */
1319 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC1),
1320 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 1),
1321 },
1322 { /* MC Channel 2 */
1323 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC2),
1324 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 2),
1325 },
1326 { /* MC Channel 3 */
1327 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC3),
1328 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 3),
1329 },
1330 { /* QPI Port 0 */
1331 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI0),
1332 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_QPI, 0),
1333 },
1334 { /* QPI Port 1 */
1335 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI1),
1336 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_QPI, 1),
1337 },
1338 { /* R2PCIe */
1339 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R2PCIE),
1340 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R2PCIE, 0),
1341 },
1342 { /* R3QPI Link 0 */
1343 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI0),
1344 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R3QPI, 0),
1345 },
1346 { /* R3QPI Link 1 */
1347 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI1),
1348 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R3QPI, 1),
1349 },
1350 { /* QPI Port 0 filter */
1351 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3c86),
1352 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
1353 SNBEP_PCI_QPI_PORT0_FILTER),
1354 },
1355 { /* QPI Port 0 filter */
1356 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3c96),
1357 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
1358 SNBEP_PCI_QPI_PORT1_FILTER),
1359 },
1360 { /* end: all zeroes */ }
1361 };
1362
1363 static struct pci_driver snbep_uncore_pci_driver = {
1364 .name = "snbep_uncore",
1365 .id_table = snbep_uncore_pci_ids,
1366 };
1367
1368 #define NODE_ID_MASK 0x7
1369
1370 /* Each three bits from 0 to 23 of GIDNIDMAP register correspond Node ID. */
1371 #define GIDNIDMAP(config, id) (((config) >> (3 * (id))) & 0x7)
1372
upi_nodeid_groupid(struct pci_dev * ubox_dev,int nodeid_loc,int idmap_loc,int * nodeid,int * groupid)1373 static int upi_nodeid_groupid(struct pci_dev *ubox_dev, int nodeid_loc, int idmap_loc,
1374 int *nodeid, int *groupid)
1375 {
1376 int ret;
1377
1378 /* get the Node ID of the local register */
1379 ret = pci_read_config_dword(ubox_dev, nodeid_loc, nodeid);
1380 if (ret)
1381 goto err;
1382
1383 *nodeid = *nodeid & NODE_ID_MASK;
1384 /* get the Node ID mapping */
1385 ret = pci_read_config_dword(ubox_dev, idmap_loc, groupid);
1386 if (ret)
1387 goto err;
1388 err:
1389 return ret;
1390 }
1391
topology_gidnid_map(int nodeid,u32 gidnid)1392 static int topology_gidnid_map(int nodeid, u32 gidnid)
1393 {
1394 int i, die_id = -1;
1395
1396 /*
1397 * every three bits in the Node ID mapping register maps
1398 * to a particular node.
1399 */
1400 for (i = 0; i < 8; i++) {
1401 if (nodeid == GIDNIDMAP(gidnid, i)) {
1402 if (topology_max_dies_per_package() > 1)
1403 die_id = i;
1404 else
1405 die_id = topology_phys_to_logical_pkg(i);
1406 if (die_id < 0)
1407 die_id = -ENODEV;
1408 break;
1409 }
1410 }
1411
1412 return die_id;
1413 }
1414
1415 /*
1416 * build pci bus to socket mapping
1417 */
snbep_pci2phy_map_init(int devid,int nodeid_loc,int idmap_loc,bool reverse)1418 static int snbep_pci2phy_map_init(int devid, int nodeid_loc, int idmap_loc, bool reverse)
1419 {
1420 struct pci_dev *ubox_dev = NULL;
1421 int i, bus, nodeid, segment, die_id;
1422 struct pci2phy_map *map;
1423 int err = 0;
1424 u32 config = 0;
1425
1426 while (1) {
1427 /* find the UBOX device */
1428 ubox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, ubox_dev);
1429 if (!ubox_dev)
1430 break;
1431 bus = ubox_dev->bus->number;
1432 /*
1433 * The nodeid and idmap registers only contain enough
1434 * information to handle 8 nodes. On systems with more
1435 * than 8 nodes, we need to rely on NUMA information,
1436 * filled in from BIOS supplied information, to determine
1437 * the topology.
1438 */
1439 if (nr_node_ids <= 8) {
1440 err = upi_nodeid_groupid(ubox_dev, nodeid_loc, idmap_loc,
1441 &nodeid, &config);
1442 if (err)
1443 break;
1444
1445 segment = pci_domain_nr(ubox_dev->bus);
1446 raw_spin_lock(&pci2phy_map_lock);
1447 map = __find_pci2phy_map(segment);
1448 if (!map) {
1449 raw_spin_unlock(&pci2phy_map_lock);
1450 err = -ENOMEM;
1451 break;
1452 }
1453
1454 map->pbus_to_dieid[bus] = topology_gidnid_map(nodeid, config);
1455 raw_spin_unlock(&pci2phy_map_lock);
1456 } else {
1457 segment = pci_domain_nr(ubox_dev->bus);
1458 raw_spin_lock(&pci2phy_map_lock);
1459 map = __find_pci2phy_map(segment);
1460 if (!map) {
1461 raw_spin_unlock(&pci2phy_map_lock);
1462 err = -ENOMEM;
1463 break;
1464 }
1465
1466 map->pbus_to_dieid[bus] = die_id = uncore_device_to_die(ubox_dev);
1467 raw_spin_unlock(&pci2phy_map_lock);
1468 }
1469 }
1470
1471 if (!err) {
1472 /*
1473 * For PCI bus with no UBOX device, find the next bus
1474 * that has UBOX device and use its mapping.
1475 */
1476 raw_spin_lock(&pci2phy_map_lock);
1477 list_for_each_entry(map, &pci2phy_map_head, list) {
1478 i = -1;
1479 if (reverse) {
1480 for (bus = 255; bus >= 0; bus--) {
1481 if (map->pbus_to_dieid[bus] != -1)
1482 i = map->pbus_to_dieid[bus];
1483 else
1484 map->pbus_to_dieid[bus] = i;
1485 }
1486 } else {
1487 for (bus = 0; bus <= 255; bus++) {
1488 if (map->pbus_to_dieid[bus] != -1)
1489 i = map->pbus_to_dieid[bus];
1490 else
1491 map->pbus_to_dieid[bus] = i;
1492 }
1493 }
1494 }
1495 raw_spin_unlock(&pci2phy_map_lock);
1496 }
1497
1498 pci_dev_put(ubox_dev);
1499
1500 return pcibios_err_to_errno(err);
1501 }
1502
snbep_uncore_pci_init(void)1503 int snbep_uncore_pci_init(void)
1504 {
1505 int ret = snbep_pci2phy_map_init(0x3ce0, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true);
1506 if (ret)
1507 return ret;
1508 uncore_pci_uncores = snbep_pci_uncores;
1509 uncore_pci_driver = &snbep_uncore_pci_driver;
1510 return 0;
1511 }
1512 /* end of Sandy Bridge-EP uncore support */
1513
1514 /* IvyTown uncore support */
ivbep_uncore_msr_init_box(struct intel_uncore_box * box)1515 static int ivbep_uncore_msr_init_box(struct intel_uncore_box *box)
1516 {
1517 unsigned msr = uncore_msr_box_ctl(box);
1518 if (msr)
1519 wrmsrq(msr, IVBEP_PMON_BOX_CTL_INT);
1520
1521 return 0;
1522 }
1523
ivbep_uncore_pci_init_box(struct intel_uncore_box * box)1524 static int ivbep_uncore_pci_init_box(struct intel_uncore_box *box)
1525 {
1526 struct pci_dev *pdev = box->pci_dev;
1527
1528 return pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL,
1529 IVBEP_PMON_BOX_CTL_INT);
1530 }
1531
1532 #define IVBEP_UNCORE_MSR_OPS_COMMON_INIT() \
1533 .init_box = ivbep_uncore_msr_init_box, \
1534 .disable_box = snbep_uncore_msr_disable_box, \
1535 .enable_box = snbep_uncore_msr_enable_box, \
1536 .disable_event = snbep_uncore_msr_disable_event, \
1537 .enable_event = snbep_uncore_msr_enable_event, \
1538 .read_counter = uncore_msr_read_counter
1539
1540 static struct intel_uncore_ops ivbep_uncore_msr_ops = {
1541 IVBEP_UNCORE_MSR_OPS_COMMON_INIT(),
1542 };
1543
1544 static struct intel_uncore_ops ivbep_uncore_pci_ops = {
1545 .init_box = ivbep_uncore_pci_init_box,
1546 .disable_box = snbep_uncore_pci_disable_box,
1547 .enable_box = snbep_uncore_pci_enable_box,
1548 .disable_event = snbep_uncore_pci_disable_event,
1549 .enable_event = snbep_uncore_pci_enable_event,
1550 .read_counter = snbep_uncore_pci_read_counter,
1551 };
1552
1553 #define IVBEP_UNCORE_PCI_COMMON_INIT() \
1554 .perf_ctr = SNBEP_PCI_PMON_CTR0, \
1555 .event_ctl = SNBEP_PCI_PMON_CTL0, \
1556 .event_mask = IVBEP_PMON_RAW_EVENT_MASK, \
1557 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \
1558 .ops = &ivbep_uncore_pci_ops, \
1559 .format_group = &ivbep_uncore_format_group
1560
1561 static struct attribute *ivbep_uncore_formats_attr[] = {
1562 &format_attr_event.attr,
1563 &format_attr_umask.attr,
1564 &format_attr_edge.attr,
1565 &format_attr_inv.attr,
1566 &format_attr_thresh8.attr,
1567 NULL,
1568 };
1569
1570 static struct attribute *ivbep_uncore_ubox_formats_attr[] = {
1571 &format_attr_event.attr,
1572 &format_attr_umask.attr,
1573 &format_attr_edge.attr,
1574 &format_attr_inv.attr,
1575 &format_attr_thresh5.attr,
1576 NULL,
1577 };
1578
1579 static struct attribute *ivbep_uncore_cbox_formats_attr[] = {
1580 &format_attr_event.attr,
1581 &format_attr_umask.attr,
1582 &format_attr_edge.attr,
1583 &format_attr_tid_en.attr,
1584 &format_attr_thresh8.attr,
1585 &format_attr_filter_tid.attr,
1586 &format_attr_filter_link.attr,
1587 &format_attr_filter_state2.attr,
1588 &format_attr_filter_nid2.attr,
1589 &format_attr_filter_opc2.attr,
1590 &format_attr_filter_nc.attr,
1591 &format_attr_filter_c6.attr,
1592 &format_attr_filter_isoc.attr,
1593 NULL,
1594 };
1595
1596 static struct attribute *ivbep_uncore_pcu_formats_attr[] = {
1597 &format_attr_event.attr,
1598 &format_attr_occ_sel.attr,
1599 &format_attr_edge.attr,
1600 &format_attr_thresh5.attr,
1601 &format_attr_occ_invert.attr,
1602 &format_attr_occ_edge.attr,
1603 &format_attr_filter_band0.attr,
1604 &format_attr_filter_band1.attr,
1605 &format_attr_filter_band2.attr,
1606 &format_attr_filter_band3.attr,
1607 NULL,
1608 };
1609
1610 static struct attribute *ivbep_uncore_qpi_formats_attr[] = {
1611 &format_attr_event_ext.attr,
1612 &format_attr_umask.attr,
1613 &format_attr_edge.attr,
1614 &format_attr_thresh8.attr,
1615 &format_attr_match_rds.attr,
1616 &format_attr_match_rnid30.attr,
1617 &format_attr_match_rnid4.attr,
1618 &format_attr_match_dnid.attr,
1619 &format_attr_match_mc.attr,
1620 &format_attr_match_opc.attr,
1621 &format_attr_match_vnw.attr,
1622 &format_attr_match0.attr,
1623 &format_attr_match1.attr,
1624 &format_attr_mask_rds.attr,
1625 &format_attr_mask_rnid30.attr,
1626 &format_attr_mask_rnid4.attr,
1627 &format_attr_mask_dnid.attr,
1628 &format_attr_mask_mc.attr,
1629 &format_attr_mask_opc.attr,
1630 &format_attr_mask_vnw.attr,
1631 &format_attr_mask0.attr,
1632 &format_attr_mask1.attr,
1633 NULL,
1634 };
1635
1636 static const struct attribute_group ivbep_uncore_format_group = {
1637 .name = "format",
1638 .attrs = ivbep_uncore_formats_attr,
1639 };
1640
1641 static const struct attribute_group ivbep_uncore_ubox_format_group = {
1642 .name = "format",
1643 .attrs = ivbep_uncore_ubox_formats_attr,
1644 };
1645
1646 static const struct attribute_group ivbep_uncore_cbox_format_group = {
1647 .name = "format",
1648 .attrs = ivbep_uncore_cbox_formats_attr,
1649 };
1650
1651 static const struct attribute_group ivbep_uncore_pcu_format_group = {
1652 .name = "format",
1653 .attrs = ivbep_uncore_pcu_formats_attr,
1654 };
1655
1656 static const struct attribute_group ivbep_uncore_qpi_format_group = {
1657 .name = "format",
1658 .attrs = ivbep_uncore_qpi_formats_attr,
1659 };
1660
1661 static struct intel_uncore_type ivbep_uncore_ubox = {
1662 .name = "ubox",
1663 .num_counters = 2,
1664 .num_boxes = 1,
1665 .perf_ctr_bits = 44,
1666 .fixed_ctr_bits = 48,
1667 .perf_ctr = SNBEP_U_MSR_PMON_CTR0,
1668 .event_ctl = SNBEP_U_MSR_PMON_CTL0,
1669 .event_mask = IVBEP_U_MSR_PMON_RAW_EVENT_MASK,
1670 .fixed_ctr = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR,
1671 .fixed_ctl = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL,
1672 .ops = &ivbep_uncore_msr_ops,
1673 .format_group = &ivbep_uncore_ubox_format_group,
1674 };
1675
1676 static struct extra_reg ivbep_uncore_cbox_extra_regs[] = {
1677 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
1678 SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
1679 SNBEP_CBO_EVENT_EXTRA_REG(0x1031, 0x10ff, 0x2),
1680 SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4),
1681 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0xc),
1682 SNBEP_CBO_EVENT_EXTRA_REG(0x5134, 0xffff, 0xc),
1683 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
1684 SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0xc),
1685 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
1686 SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0xc),
1687 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
1688 SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0xc),
1689 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x10),
1690 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10),
1691 SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10),
1692 SNBEP_CBO_EVENT_EXTRA_REG(0x2335, 0xffff, 0x10),
1693 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0x18),
1694 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0x18),
1695 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x8),
1696 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x8),
1697 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x8),
1698 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x8),
1699 SNBEP_CBO_EVENT_EXTRA_REG(0x8135, 0xffff, 0x10),
1700 SNBEP_CBO_EVENT_EXTRA_REG(0x8335, 0xffff, 0x10),
1701 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x10),
1702 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x10),
1703 SNBEP_CBO_EVENT_EXTRA_REG(0x2136, 0xffff, 0x10),
1704 SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10),
1705 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0x18),
1706 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0x18),
1707 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x8),
1708 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x8),
1709 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x8),
1710 SNBEP_CBO_EVENT_EXTRA_REG(0x5036, 0xffff, 0x8),
1711 SNBEP_CBO_EVENT_EXTRA_REG(0x8136, 0xffff, 0x10),
1712 SNBEP_CBO_EVENT_EXTRA_REG(0x8336, 0xffff, 0x10),
1713 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x8),
1714 EVENT_EXTRA_END
1715 };
1716
ivbep_cbox_filter_mask(int fields)1717 static u64 ivbep_cbox_filter_mask(int fields)
1718 {
1719 u64 mask = 0;
1720
1721 if (fields & 0x1)
1722 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_TID;
1723 if (fields & 0x2)
1724 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_LINK;
1725 if (fields & 0x4)
1726 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_STATE;
1727 if (fields & 0x8)
1728 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_NID;
1729 if (fields & 0x10) {
1730 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_OPC;
1731 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_NC;
1732 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_C6;
1733 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_ISOC;
1734 }
1735
1736 return mask;
1737 }
1738
1739 static struct event_constraint *
ivbep_cbox_get_constraint(struct intel_uncore_box * box,struct perf_event * event)1740 ivbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
1741 {
1742 return __snbep_cbox_get_constraint(box, event, ivbep_cbox_filter_mask);
1743 }
1744
ivbep_cbox_hw_config(struct intel_uncore_box * box,struct perf_event * event)1745 static int ivbep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
1746 {
1747 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1748 struct extra_reg *er;
1749 int idx = 0;
1750
1751 for (er = ivbep_uncore_cbox_extra_regs; er->msr; er++) {
1752 if (er->event != (event->hw.config & er->config_mask))
1753 continue;
1754 idx |= er->idx;
1755 }
1756
1757 if (idx) {
1758 reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER +
1759 SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
1760 reg1->config = event->attr.config1 & ivbep_cbox_filter_mask(idx);
1761 reg1->idx = idx;
1762 }
1763 return 0;
1764 }
1765
ivbep_cbox_enable_event(struct intel_uncore_box * box,struct perf_event * event)1766 static void ivbep_cbox_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1767 {
1768 struct hw_perf_event *hwc = &event->hw;
1769 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1770
1771 if (reg1->idx != EXTRA_REG_NONE) {
1772 u64 filter = uncore_shared_reg_config(box, 0);
1773 wrmsrq(reg1->reg, filter & 0xffffffff);
1774 wrmsrq(reg1->reg + 6, filter >> 32);
1775 }
1776
1777 wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
1778 }
1779
1780 static struct intel_uncore_ops ivbep_uncore_cbox_ops = {
1781 .init_box = ivbep_uncore_msr_init_box,
1782 .disable_box = snbep_uncore_msr_disable_box,
1783 .enable_box = snbep_uncore_msr_enable_box,
1784 .disable_event = snbep_uncore_msr_disable_event,
1785 .enable_event = ivbep_cbox_enable_event,
1786 .read_counter = uncore_msr_read_counter,
1787 .hw_config = ivbep_cbox_hw_config,
1788 .get_constraint = ivbep_cbox_get_constraint,
1789 .put_constraint = snbep_cbox_put_constraint,
1790 };
1791
1792 static struct intel_uncore_type ivbep_uncore_cbox = {
1793 .name = "cbox",
1794 .num_counters = 4,
1795 .num_boxes = 15,
1796 .perf_ctr_bits = 44,
1797 .event_ctl = SNBEP_C0_MSR_PMON_CTL0,
1798 .perf_ctr = SNBEP_C0_MSR_PMON_CTR0,
1799 .event_mask = IVBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
1800 .box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL,
1801 .msr_offset = SNBEP_CBO_MSR_OFFSET,
1802 .num_shared_regs = 1,
1803 .constraints = snbep_uncore_cbox_constraints,
1804 .ops = &ivbep_uncore_cbox_ops,
1805 .format_group = &ivbep_uncore_cbox_format_group,
1806 };
1807
1808 static struct intel_uncore_ops ivbep_uncore_pcu_ops = {
1809 IVBEP_UNCORE_MSR_OPS_COMMON_INIT(),
1810 .hw_config = snbep_pcu_hw_config,
1811 .get_constraint = snbep_pcu_get_constraint,
1812 .put_constraint = snbep_pcu_put_constraint,
1813 };
1814
1815 static struct intel_uncore_type ivbep_uncore_pcu = {
1816 .name = "pcu",
1817 .num_counters = 4,
1818 .num_boxes = 1,
1819 .perf_ctr_bits = 48,
1820 .perf_ctr = SNBEP_PCU_MSR_PMON_CTR0,
1821 .event_ctl = SNBEP_PCU_MSR_PMON_CTL0,
1822 .event_mask = IVBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
1823 .box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL,
1824 .num_shared_regs = 1,
1825 .ops = &ivbep_uncore_pcu_ops,
1826 .format_group = &ivbep_uncore_pcu_format_group,
1827 };
1828
1829 static struct intel_uncore_type *ivbep_msr_uncores[] = {
1830 &ivbep_uncore_ubox,
1831 &ivbep_uncore_cbox,
1832 &ivbep_uncore_pcu,
1833 NULL,
1834 };
1835
ivbep_uncore_cpu_init(void)1836 void ivbep_uncore_cpu_init(void)
1837 {
1838 if (ivbep_uncore_cbox.num_boxes > topology_num_cores_per_package())
1839 ivbep_uncore_cbox.num_boxes = topology_num_cores_per_package();
1840 uncore_msr_uncores = ivbep_msr_uncores;
1841 }
1842
1843 static struct intel_uncore_type ivbep_uncore_ha = {
1844 .name = "ha",
1845 .num_counters = 4,
1846 .num_boxes = 2,
1847 .perf_ctr_bits = 48,
1848 IVBEP_UNCORE_PCI_COMMON_INIT(),
1849 };
1850
1851 static struct intel_uncore_type ivbep_uncore_imc = {
1852 .name = "imc",
1853 .num_counters = 4,
1854 .num_boxes = 8,
1855 .perf_ctr_bits = 48,
1856 .fixed_ctr_bits = 48,
1857 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
1858 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
1859 .event_descs = snbep_uncore_imc_events,
1860 IVBEP_UNCORE_PCI_COMMON_INIT(),
1861 };
1862
1863 /* registers in IRP boxes are not properly aligned */
1864 static unsigned ivbep_uncore_irp_ctls[] = {0xd8, 0xdc, 0xe0, 0xe4};
1865 static unsigned ivbep_uncore_irp_ctrs[] = {0xa0, 0xb0, 0xb8, 0xc0};
1866
ivbep_uncore_irp_enable_event(struct intel_uncore_box * box,struct perf_event * event)1867 static void ivbep_uncore_irp_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1868 {
1869 struct pci_dev *pdev = box->pci_dev;
1870 struct hw_perf_event *hwc = &event->hw;
1871
1872 pci_write_config_dword(pdev, ivbep_uncore_irp_ctls[hwc->idx],
1873 hwc->config | SNBEP_PMON_CTL_EN);
1874 }
1875
ivbep_uncore_irp_disable_event(struct intel_uncore_box * box,struct perf_event * event)1876 static void ivbep_uncore_irp_disable_event(struct intel_uncore_box *box, struct perf_event *event)
1877 {
1878 struct pci_dev *pdev = box->pci_dev;
1879 struct hw_perf_event *hwc = &event->hw;
1880
1881 pci_write_config_dword(pdev, ivbep_uncore_irp_ctls[hwc->idx], hwc->config);
1882 }
1883
ivbep_uncore_irp_read_counter(struct intel_uncore_box * box,struct perf_event * event)1884 static u64 ivbep_uncore_irp_read_counter(struct intel_uncore_box *box, struct perf_event *event)
1885 {
1886 struct pci_dev *pdev = box->pci_dev;
1887 struct hw_perf_event *hwc = &event->hw;
1888 u64 count = 0;
1889
1890 pci_read_config_dword(pdev, ivbep_uncore_irp_ctrs[hwc->idx], (u32 *)&count);
1891 pci_read_config_dword(pdev, ivbep_uncore_irp_ctrs[hwc->idx] + 4, (u32 *)&count + 1);
1892
1893 return count;
1894 }
1895
1896 static struct intel_uncore_ops ivbep_uncore_irp_ops = {
1897 .init_box = ivbep_uncore_pci_init_box,
1898 .disable_box = snbep_uncore_pci_disable_box,
1899 .enable_box = snbep_uncore_pci_enable_box,
1900 .disable_event = ivbep_uncore_irp_disable_event,
1901 .enable_event = ivbep_uncore_irp_enable_event,
1902 .read_counter = ivbep_uncore_irp_read_counter,
1903 };
1904
1905 static struct intel_uncore_type ivbep_uncore_irp = {
1906 .name = "irp",
1907 .num_counters = 4,
1908 .num_boxes = 1,
1909 .perf_ctr_bits = 48,
1910 .event_mask = IVBEP_PMON_RAW_EVENT_MASK,
1911 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
1912 .ops = &ivbep_uncore_irp_ops,
1913 .format_group = &ivbep_uncore_format_group,
1914 };
1915
1916 static struct intel_uncore_ops ivbep_uncore_qpi_ops = {
1917 .init_box = ivbep_uncore_pci_init_box,
1918 .disable_box = snbep_uncore_pci_disable_box,
1919 .enable_box = snbep_uncore_pci_enable_box,
1920 .disable_event = snbep_uncore_pci_disable_event,
1921 .enable_event = snbep_qpi_enable_event,
1922 .read_counter = snbep_uncore_pci_read_counter,
1923 .hw_config = snbep_qpi_hw_config,
1924 .get_constraint = uncore_get_constraint,
1925 .put_constraint = uncore_put_constraint,
1926 };
1927
1928 static struct intel_uncore_type ivbep_uncore_qpi = {
1929 .name = "qpi",
1930 .num_counters = 4,
1931 .num_boxes = 3,
1932 .perf_ctr_bits = 48,
1933 .perf_ctr = SNBEP_PCI_PMON_CTR0,
1934 .event_ctl = SNBEP_PCI_PMON_CTL0,
1935 .event_mask = IVBEP_QPI_PCI_PMON_RAW_EVENT_MASK,
1936 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
1937 .num_shared_regs = 1,
1938 .ops = &ivbep_uncore_qpi_ops,
1939 .format_group = &ivbep_uncore_qpi_format_group,
1940 };
1941
1942 static struct intel_uncore_type ivbep_uncore_r2pcie = {
1943 .name = "r2pcie",
1944 .num_counters = 4,
1945 .num_boxes = 1,
1946 .perf_ctr_bits = 44,
1947 .constraints = snbep_uncore_r2pcie_constraints,
1948 IVBEP_UNCORE_PCI_COMMON_INIT(),
1949 };
1950
1951 static struct intel_uncore_type ivbep_uncore_r3qpi = {
1952 .name = "r3qpi",
1953 .num_counters = 3,
1954 .num_boxes = 2,
1955 .perf_ctr_bits = 44,
1956 .constraints = snbep_uncore_r3qpi_constraints,
1957 IVBEP_UNCORE_PCI_COMMON_INIT(),
1958 };
1959
1960 enum {
1961 IVBEP_PCI_UNCORE_HA,
1962 IVBEP_PCI_UNCORE_IMC,
1963 IVBEP_PCI_UNCORE_IRP,
1964 IVBEP_PCI_UNCORE_QPI,
1965 IVBEP_PCI_UNCORE_R2PCIE,
1966 IVBEP_PCI_UNCORE_R3QPI,
1967 };
1968
1969 static struct intel_uncore_type *ivbep_pci_uncores[] = {
1970 [IVBEP_PCI_UNCORE_HA] = &ivbep_uncore_ha,
1971 [IVBEP_PCI_UNCORE_IMC] = &ivbep_uncore_imc,
1972 [IVBEP_PCI_UNCORE_IRP] = &ivbep_uncore_irp,
1973 [IVBEP_PCI_UNCORE_QPI] = &ivbep_uncore_qpi,
1974 [IVBEP_PCI_UNCORE_R2PCIE] = &ivbep_uncore_r2pcie,
1975 [IVBEP_PCI_UNCORE_R3QPI] = &ivbep_uncore_r3qpi,
1976 NULL,
1977 };
1978
1979 static const struct pci_device_id ivbep_uncore_pci_ids[] = {
1980 { /* Home Agent 0 */
1981 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe30),
1982 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_HA, 0),
1983 },
1984 { /* Home Agent 1 */
1985 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe38),
1986 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_HA, 1),
1987 },
1988 { /* MC0 Channel 0 */
1989 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb4),
1990 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 0),
1991 },
1992 { /* MC0 Channel 1 */
1993 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb5),
1994 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 1),
1995 },
1996 { /* MC0 Channel 3 */
1997 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb0),
1998 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 2),
1999 },
2000 { /* MC0 Channel 4 */
2001 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb1),
2002 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 3),
2003 },
2004 { /* MC1 Channel 0 */
2005 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef4),
2006 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 4),
2007 },
2008 { /* MC1 Channel 1 */
2009 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef5),
2010 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 5),
2011 },
2012 { /* MC1 Channel 3 */
2013 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef0),
2014 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 6),
2015 },
2016 { /* MC1 Channel 4 */
2017 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef1),
2018 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 7),
2019 },
2020 { /* IRP */
2021 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe39),
2022 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IRP, 0),
2023 },
2024 { /* QPI0 Port 0 */
2025 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe32),
2026 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_QPI, 0),
2027 },
2028 { /* QPI0 Port 1 */
2029 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe33),
2030 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_QPI, 1),
2031 },
2032 { /* QPI1 Port 2 */
2033 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3a),
2034 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_QPI, 2),
2035 },
2036 { /* R2PCIe */
2037 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe34),
2038 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R2PCIE, 0),
2039 },
2040 { /* R3QPI0 Link 0 */
2041 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe36),
2042 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R3QPI, 0),
2043 },
2044 { /* R3QPI0 Link 1 */
2045 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe37),
2046 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R3QPI, 1),
2047 },
2048 { /* R3QPI1 Link 2 */
2049 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3e),
2050 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R3QPI, 2),
2051 },
2052 { /* QPI Port 0 filter */
2053 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe86),
2054 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
2055 SNBEP_PCI_QPI_PORT0_FILTER),
2056 },
2057 { /* QPI Port 0 filter */
2058 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe96),
2059 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
2060 SNBEP_PCI_QPI_PORT1_FILTER),
2061 },
2062 { /* end: all zeroes */ }
2063 };
2064
2065 static struct pci_driver ivbep_uncore_pci_driver = {
2066 .name = "ivbep_uncore",
2067 .id_table = ivbep_uncore_pci_ids,
2068 };
2069
ivbep_uncore_pci_init(void)2070 int ivbep_uncore_pci_init(void)
2071 {
2072 int ret = snbep_pci2phy_map_init(0x0e1e, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true);
2073 if (ret)
2074 return ret;
2075 uncore_pci_uncores = ivbep_pci_uncores;
2076 uncore_pci_driver = &ivbep_uncore_pci_driver;
2077 return 0;
2078 }
2079 /* end of IvyTown uncore support */
2080
2081 /* KNL uncore support */
2082 static struct attribute *knl_uncore_ubox_formats_attr[] = {
2083 &format_attr_event.attr,
2084 &format_attr_umask.attr,
2085 &format_attr_edge.attr,
2086 &format_attr_tid_en.attr,
2087 &format_attr_inv.attr,
2088 &format_attr_thresh5.attr,
2089 NULL,
2090 };
2091
2092 static const struct attribute_group knl_uncore_ubox_format_group = {
2093 .name = "format",
2094 .attrs = knl_uncore_ubox_formats_attr,
2095 };
2096
2097 static struct intel_uncore_type knl_uncore_ubox = {
2098 .name = "ubox",
2099 .num_counters = 2,
2100 .num_boxes = 1,
2101 .perf_ctr_bits = 48,
2102 .fixed_ctr_bits = 48,
2103 .perf_ctr = HSWEP_U_MSR_PMON_CTR0,
2104 .event_ctl = HSWEP_U_MSR_PMON_CTL0,
2105 .event_mask = KNL_U_MSR_PMON_RAW_EVENT_MASK,
2106 .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR,
2107 .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL,
2108 .ops = &snbep_uncore_msr_ops,
2109 .format_group = &knl_uncore_ubox_format_group,
2110 };
2111
2112 static struct attribute *knl_uncore_cha_formats_attr[] = {
2113 &format_attr_event.attr,
2114 &format_attr_umask.attr,
2115 &format_attr_qor.attr,
2116 &format_attr_edge.attr,
2117 &format_attr_tid_en.attr,
2118 &format_attr_inv.attr,
2119 &format_attr_thresh8.attr,
2120 &format_attr_filter_tid4.attr,
2121 &format_attr_filter_link3.attr,
2122 &format_attr_filter_state4.attr,
2123 &format_attr_filter_local.attr,
2124 &format_attr_filter_all_op.attr,
2125 &format_attr_filter_nnm.attr,
2126 &format_attr_filter_opc3.attr,
2127 &format_attr_filter_nc.attr,
2128 &format_attr_filter_isoc.attr,
2129 NULL,
2130 };
2131
2132 static const struct attribute_group knl_uncore_cha_format_group = {
2133 .name = "format",
2134 .attrs = knl_uncore_cha_formats_attr,
2135 };
2136
2137 static struct event_constraint knl_uncore_cha_constraints[] = {
2138 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
2139 UNCORE_EVENT_CONSTRAINT(0x1f, 0x1),
2140 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
2141 EVENT_CONSTRAINT_END
2142 };
2143
2144 static struct extra_reg knl_uncore_cha_extra_regs[] = {
2145 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
2146 SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
2147 SNBEP_CBO_EVENT_EXTRA_REG(0x3d, 0xff, 0x2),
2148 SNBEP_CBO_EVENT_EXTRA_REG(0x35, 0xff, 0x4),
2149 SNBEP_CBO_EVENT_EXTRA_REG(0x36, 0xff, 0x4),
2150 EVENT_EXTRA_END
2151 };
2152
knl_cha_filter_mask(int fields)2153 static u64 knl_cha_filter_mask(int fields)
2154 {
2155 u64 mask = 0;
2156
2157 if (fields & 0x1)
2158 mask |= KNL_CHA_MSR_PMON_BOX_FILTER_TID;
2159 if (fields & 0x2)
2160 mask |= KNL_CHA_MSR_PMON_BOX_FILTER_STATE;
2161 if (fields & 0x4)
2162 mask |= KNL_CHA_MSR_PMON_BOX_FILTER_OP;
2163 return mask;
2164 }
2165
2166 static struct event_constraint *
knl_cha_get_constraint(struct intel_uncore_box * box,struct perf_event * event)2167 knl_cha_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
2168 {
2169 return __snbep_cbox_get_constraint(box, event, knl_cha_filter_mask);
2170 }
2171
knl_cha_hw_config(struct intel_uncore_box * box,struct perf_event * event)2172 static int knl_cha_hw_config(struct intel_uncore_box *box,
2173 struct perf_event *event)
2174 {
2175 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
2176 struct extra_reg *er;
2177 int idx = 0;
2178
2179 for (er = knl_uncore_cha_extra_regs; er->msr; er++) {
2180 if (er->event != (event->hw.config & er->config_mask))
2181 continue;
2182 idx |= er->idx;
2183 }
2184
2185 if (idx) {
2186 reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 +
2187 KNL_CHA_MSR_OFFSET * box->pmu->pmu_idx;
2188 reg1->config = event->attr.config1 & knl_cha_filter_mask(idx);
2189
2190 reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_REMOTE_NODE;
2191 reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE;
2192 reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_NNC;
2193 reg1->idx = idx;
2194 }
2195 return 0;
2196 }
2197
2198 static void hswep_cbox_enable_event(struct intel_uncore_box *box,
2199 struct perf_event *event);
2200
2201 static struct intel_uncore_ops knl_uncore_cha_ops = {
2202 .init_box = snbep_uncore_msr_init_box,
2203 .disable_box = snbep_uncore_msr_disable_box,
2204 .enable_box = snbep_uncore_msr_enable_box,
2205 .disable_event = snbep_uncore_msr_disable_event,
2206 .enable_event = hswep_cbox_enable_event,
2207 .read_counter = uncore_msr_read_counter,
2208 .hw_config = knl_cha_hw_config,
2209 .get_constraint = knl_cha_get_constraint,
2210 .put_constraint = snbep_cbox_put_constraint,
2211 };
2212
2213 static struct intel_uncore_type knl_uncore_cha = {
2214 .name = "cha",
2215 .num_counters = 4,
2216 .num_boxes = 38,
2217 .perf_ctr_bits = 48,
2218 .event_ctl = HSWEP_C0_MSR_PMON_CTL0,
2219 .perf_ctr = HSWEP_C0_MSR_PMON_CTR0,
2220 .event_mask = KNL_CHA_MSR_PMON_RAW_EVENT_MASK,
2221 .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL,
2222 .msr_offset = KNL_CHA_MSR_OFFSET,
2223 .num_shared_regs = 1,
2224 .constraints = knl_uncore_cha_constraints,
2225 .ops = &knl_uncore_cha_ops,
2226 .format_group = &knl_uncore_cha_format_group,
2227 };
2228
2229 static struct attribute *knl_uncore_pcu_formats_attr[] = {
2230 &format_attr_event2.attr,
2231 &format_attr_use_occ_ctr.attr,
2232 &format_attr_occ_sel.attr,
2233 &format_attr_edge.attr,
2234 &format_attr_tid_en.attr,
2235 &format_attr_inv.attr,
2236 &format_attr_thresh6.attr,
2237 &format_attr_occ_invert.attr,
2238 &format_attr_occ_edge_det.attr,
2239 NULL,
2240 };
2241
2242 static const struct attribute_group knl_uncore_pcu_format_group = {
2243 .name = "format",
2244 .attrs = knl_uncore_pcu_formats_attr,
2245 };
2246
2247 static struct intel_uncore_type knl_uncore_pcu = {
2248 .name = "pcu",
2249 .num_counters = 4,
2250 .num_boxes = 1,
2251 .perf_ctr_bits = 48,
2252 .perf_ctr = HSWEP_PCU_MSR_PMON_CTR0,
2253 .event_ctl = HSWEP_PCU_MSR_PMON_CTL0,
2254 .event_mask = KNL_PCU_MSR_PMON_RAW_EVENT_MASK,
2255 .box_ctl = HSWEP_PCU_MSR_PMON_BOX_CTL,
2256 .ops = &snbep_uncore_msr_ops,
2257 .format_group = &knl_uncore_pcu_format_group,
2258 };
2259
2260 static struct intel_uncore_type *knl_msr_uncores[] = {
2261 &knl_uncore_ubox,
2262 &knl_uncore_cha,
2263 &knl_uncore_pcu,
2264 NULL,
2265 };
2266
knl_uncore_cpu_init(void)2267 void knl_uncore_cpu_init(void)
2268 {
2269 uncore_msr_uncores = knl_msr_uncores;
2270 }
2271
knl_uncore_imc_enable_box(struct intel_uncore_box * box)2272 static void knl_uncore_imc_enable_box(struct intel_uncore_box *box)
2273 {
2274 struct pci_dev *pdev = box->pci_dev;
2275 int box_ctl = uncore_pci_box_ctl(box);
2276
2277 pci_write_config_dword(pdev, box_ctl, 0);
2278 }
2279
knl_uncore_imc_enable_event(struct intel_uncore_box * box,struct perf_event * event)2280 static void knl_uncore_imc_enable_event(struct intel_uncore_box *box,
2281 struct perf_event *event)
2282 {
2283 struct pci_dev *pdev = box->pci_dev;
2284 struct hw_perf_event *hwc = &event->hw;
2285
2286 if ((event->attr.config & SNBEP_PMON_CTL_EV_SEL_MASK)
2287 == UNCORE_FIXED_EVENT)
2288 pci_write_config_dword(pdev, hwc->config_base,
2289 hwc->config | KNL_PMON_FIXED_CTL_EN);
2290 else
2291 pci_write_config_dword(pdev, hwc->config_base,
2292 hwc->config | SNBEP_PMON_CTL_EN);
2293 }
2294
2295 static struct intel_uncore_ops knl_uncore_imc_ops = {
2296 .init_box = snbep_uncore_pci_init_box,
2297 .disable_box = snbep_uncore_pci_disable_box,
2298 .enable_box = knl_uncore_imc_enable_box,
2299 .read_counter = snbep_uncore_pci_read_counter,
2300 .enable_event = knl_uncore_imc_enable_event,
2301 .disable_event = snbep_uncore_pci_disable_event,
2302 };
2303
2304 static struct intel_uncore_type knl_uncore_imc_uclk = {
2305 .name = "imc_uclk",
2306 .num_counters = 4,
2307 .num_boxes = 2,
2308 .perf_ctr_bits = 48,
2309 .fixed_ctr_bits = 48,
2310 .perf_ctr = KNL_UCLK_MSR_PMON_CTR0_LOW,
2311 .event_ctl = KNL_UCLK_MSR_PMON_CTL0,
2312 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
2313 .fixed_ctr = KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW,
2314 .fixed_ctl = KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL,
2315 .box_ctl = KNL_UCLK_MSR_PMON_BOX_CTL,
2316 .ops = &knl_uncore_imc_ops,
2317 .format_group = &snbep_uncore_format_group,
2318 };
2319
2320 static struct intel_uncore_type knl_uncore_imc_dclk = {
2321 .name = "imc",
2322 .num_counters = 4,
2323 .num_boxes = 6,
2324 .perf_ctr_bits = 48,
2325 .fixed_ctr_bits = 48,
2326 .perf_ctr = KNL_MC0_CH0_MSR_PMON_CTR0_LOW,
2327 .event_ctl = KNL_MC0_CH0_MSR_PMON_CTL0,
2328 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
2329 .fixed_ctr = KNL_MC0_CH0_MSR_PMON_FIXED_LOW,
2330 .fixed_ctl = KNL_MC0_CH0_MSR_PMON_FIXED_CTL,
2331 .box_ctl = KNL_MC0_CH0_MSR_PMON_BOX_CTL,
2332 .ops = &knl_uncore_imc_ops,
2333 .format_group = &snbep_uncore_format_group,
2334 };
2335
2336 static struct intel_uncore_type knl_uncore_edc_uclk = {
2337 .name = "edc_uclk",
2338 .num_counters = 4,
2339 .num_boxes = 8,
2340 .perf_ctr_bits = 48,
2341 .fixed_ctr_bits = 48,
2342 .perf_ctr = KNL_UCLK_MSR_PMON_CTR0_LOW,
2343 .event_ctl = KNL_UCLK_MSR_PMON_CTL0,
2344 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
2345 .fixed_ctr = KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW,
2346 .fixed_ctl = KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL,
2347 .box_ctl = KNL_UCLK_MSR_PMON_BOX_CTL,
2348 .ops = &knl_uncore_imc_ops,
2349 .format_group = &snbep_uncore_format_group,
2350 };
2351
2352 static struct intel_uncore_type knl_uncore_edc_eclk = {
2353 .name = "edc_eclk",
2354 .num_counters = 4,
2355 .num_boxes = 8,
2356 .perf_ctr_bits = 48,
2357 .fixed_ctr_bits = 48,
2358 .perf_ctr = KNL_EDC0_ECLK_MSR_PMON_CTR0_LOW,
2359 .event_ctl = KNL_EDC0_ECLK_MSR_PMON_CTL0,
2360 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
2361 .fixed_ctr = KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_LOW,
2362 .fixed_ctl = KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_CTL,
2363 .box_ctl = KNL_EDC0_ECLK_MSR_PMON_BOX_CTL,
2364 .ops = &knl_uncore_imc_ops,
2365 .format_group = &snbep_uncore_format_group,
2366 };
2367
2368 static struct event_constraint knl_uncore_m2pcie_constraints[] = {
2369 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
2370 EVENT_CONSTRAINT_END
2371 };
2372
2373 static struct intel_uncore_type knl_uncore_m2pcie = {
2374 .name = "m2pcie",
2375 .num_counters = 4,
2376 .num_boxes = 1,
2377 .perf_ctr_bits = 48,
2378 .constraints = knl_uncore_m2pcie_constraints,
2379 SNBEP_UNCORE_PCI_COMMON_INIT(),
2380 };
2381
2382 static struct attribute *knl_uncore_irp_formats_attr[] = {
2383 &format_attr_event.attr,
2384 &format_attr_umask.attr,
2385 &format_attr_qor.attr,
2386 &format_attr_edge.attr,
2387 &format_attr_inv.attr,
2388 &format_attr_thresh8.attr,
2389 NULL,
2390 };
2391
2392 static const struct attribute_group knl_uncore_irp_format_group = {
2393 .name = "format",
2394 .attrs = knl_uncore_irp_formats_attr,
2395 };
2396
2397 static struct intel_uncore_type knl_uncore_irp = {
2398 .name = "irp",
2399 .num_counters = 2,
2400 .num_boxes = 1,
2401 .perf_ctr_bits = 48,
2402 .perf_ctr = SNBEP_PCI_PMON_CTR0,
2403 .event_ctl = SNBEP_PCI_PMON_CTL0,
2404 .event_mask = KNL_IRP_PCI_PMON_RAW_EVENT_MASK,
2405 .box_ctl = KNL_IRP_PCI_PMON_BOX_CTL,
2406 .ops = &snbep_uncore_pci_ops,
2407 .format_group = &knl_uncore_irp_format_group,
2408 };
2409
2410 enum {
2411 KNL_PCI_UNCORE_MC_UCLK,
2412 KNL_PCI_UNCORE_MC_DCLK,
2413 KNL_PCI_UNCORE_EDC_UCLK,
2414 KNL_PCI_UNCORE_EDC_ECLK,
2415 KNL_PCI_UNCORE_M2PCIE,
2416 KNL_PCI_UNCORE_IRP,
2417 };
2418
2419 static struct intel_uncore_type *knl_pci_uncores[] = {
2420 [KNL_PCI_UNCORE_MC_UCLK] = &knl_uncore_imc_uclk,
2421 [KNL_PCI_UNCORE_MC_DCLK] = &knl_uncore_imc_dclk,
2422 [KNL_PCI_UNCORE_EDC_UCLK] = &knl_uncore_edc_uclk,
2423 [KNL_PCI_UNCORE_EDC_ECLK] = &knl_uncore_edc_eclk,
2424 [KNL_PCI_UNCORE_M2PCIE] = &knl_uncore_m2pcie,
2425 [KNL_PCI_UNCORE_IRP] = &knl_uncore_irp,
2426 NULL,
2427 };
2428
2429 /*
2430 * KNL uses a common PCI device ID for multiple instances of an Uncore PMU
2431 * device type. prior to KNL, each instance of a PMU device type had a unique
2432 * device ID.
2433 *
2434 * PCI Device ID Uncore PMU Devices
2435 * ----------------------------------
2436 * 0x7841 MC0 UClk, MC1 UClk
2437 * 0x7843 MC0 DClk CH 0, MC0 DClk CH 1, MC0 DClk CH 2,
2438 * MC1 DClk CH 0, MC1 DClk CH 1, MC1 DClk CH 2
2439 * 0x7833 EDC0 UClk, EDC1 UClk, EDC2 UClk, EDC3 UClk,
2440 * EDC4 UClk, EDC5 UClk, EDC6 UClk, EDC7 UClk
2441 * 0x7835 EDC0 EClk, EDC1 EClk, EDC2 EClk, EDC3 EClk,
2442 * EDC4 EClk, EDC5 EClk, EDC6 EClk, EDC7 EClk
2443 * 0x7817 M2PCIe
2444 * 0x7814 IRP
2445 */
2446
2447 static const struct pci_device_id knl_uncore_pci_ids[] = {
2448 { /* MC0 UClk */
2449 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7841),
2450 .driver_data = UNCORE_PCI_DEV_FULL_DATA(10, 0, KNL_PCI_UNCORE_MC_UCLK, 0),
2451 },
2452 { /* MC1 UClk */
2453 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7841),
2454 .driver_data = UNCORE_PCI_DEV_FULL_DATA(11, 0, KNL_PCI_UNCORE_MC_UCLK, 1),
2455 },
2456 { /* MC0 DClk CH 0 */
2457 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843),
2458 .driver_data = UNCORE_PCI_DEV_FULL_DATA(8, 2, KNL_PCI_UNCORE_MC_DCLK, 0),
2459 },
2460 { /* MC0 DClk CH 1 */
2461 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843),
2462 .driver_data = UNCORE_PCI_DEV_FULL_DATA(8, 3, KNL_PCI_UNCORE_MC_DCLK, 1),
2463 },
2464 { /* MC0 DClk CH 2 */
2465 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843),
2466 .driver_data = UNCORE_PCI_DEV_FULL_DATA(8, 4, KNL_PCI_UNCORE_MC_DCLK, 2),
2467 },
2468 { /* MC1 DClk CH 0 */
2469 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843),
2470 .driver_data = UNCORE_PCI_DEV_FULL_DATA(9, 2, KNL_PCI_UNCORE_MC_DCLK, 3),
2471 },
2472 { /* MC1 DClk CH 1 */
2473 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843),
2474 .driver_data = UNCORE_PCI_DEV_FULL_DATA(9, 3, KNL_PCI_UNCORE_MC_DCLK, 4),
2475 },
2476 { /* MC1 DClk CH 2 */
2477 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843),
2478 .driver_data = UNCORE_PCI_DEV_FULL_DATA(9, 4, KNL_PCI_UNCORE_MC_DCLK, 5),
2479 },
2480 { /* EDC0 UClk */
2481 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833),
2482 .driver_data = UNCORE_PCI_DEV_FULL_DATA(15, 0, KNL_PCI_UNCORE_EDC_UCLK, 0),
2483 },
2484 { /* EDC1 UClk */
2485 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833),
2486 .driver_data = UNCORE_PCI_DEV_FULL_DATA(16, 0, KNL_PCI_UNCORE_EDC_UCLK, 1),
2487 },
2488 { /* EDC2 UClk */
2489 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833),
2490 .driver_data = UNCORE_PCI_DEV_FULL_DATA(17, 0, KNL_PCI_UNCORE_EDC_UCLK, 2),
2491 },
2492 { /* EDC3 UClk */
2493 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833),
2494 .driver_data = UNCORE_PCI_DEV_FULL_DATA(18, 0, KNL_PCI_UNCORE_EDC_UCLK, 3),
2495 },
2496 { /* EDC4 UClk */
2497 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833),
2498 .driver_data = UNCORE_PCI_DEV_FULL_DATA(19, 0, KNL_PCI_UNCORE_EDC_UCLK, 4),
2499 },
2500 { /* EDC5 UClk */
2501 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833),
2502 .driver_data = UNCORE_PCI_DEV_FULL_DATA(20, 0, KNL_PCI_UNCORE_EDC_UCLK, 5),
2503 },
2504 { /* EDC6 UClk */
2505 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833),
2506 .driver_data = UNCORE_PCI_DEV_FULL_DATA(21, 0, KNL_PCI_UNCORE_EDC_UCLK, 6),
2507 },
2508 { /* EDC7 UClk */
2509 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833),
2510 .driver_data = UNCORE_PCI_DEV_FULL_DATA(22, 0, KNL_PCI_UNCORE_EDC_UCLK, 7),
2511 },
2512 { /* EDC0 EClk */
2513 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835),
2514 .driver_data = UNCORE_PCI_DEV_FULL_DATA(24, 2, KNL_PCI_UNCORE_EDC_ECLK, 0),
2515 },
2516 { /* EDC1 EClk */
2517 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835),
2518 .driver_data = UNCORE_PCI_DEV_FULL_DATA(25, 2, KNL_PCI_UNCORE_EDC_ECLK, 1),
2519 },
2520 { /* EDC2 EClk */
2521 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835),
2522 .driver_data = UNCORE_PCI_DEV_FULL_DATA(26, 2, KNL_PCI_UNCORE_EDC_ECLK, 2),
2523 },
2524 { /* EDC3 EClk */
2525 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835),
2526 .driver_data = UNCORE_PCI_DEV_FULL_DATA(27, 2, KNL_PCI_UNCORE_EDC_ECLK, 3),
2527 },
2528 { /* EDC4 EClk */
2529 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835),
2530 .driver_data = UNCORE_PCI_DEV_FULL_DATA(28, 2, KNL_PCI_UNCORE_EDC_ECLK, 4),
2531 },
2532 { /* EDC5 EClk */
2533 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835),
2534 .driver_data = UNCORE_PCI_DEV_FULL_DATA(29, 2, KNL_PCI_UNCORE_EDC_ECLK, 5),
2535 },
2536 { /* EDC6 EClk */
2537 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835),
2538 .driver_data = UNCORE_PCI_DEV_FULL_DATA(30, 2, KNL_PCI_UNCORE_EDC_ECLK, 6),
2539 },
2540 { /* EDC7 EClk */
2541 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835),
2542 .driver_data = UNCORE_PCI_DEV_FULL_DATA(31, 2, KNL_PCI_UNCORE_EDC_ECLK, 7),
2543 },
2544 { /* M2PCIe */
2545 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7817),
2546 .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_M2PCIE, 0),
2547 },
2548 { /* IRP */
2549 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7814),
2550 .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_IRP, 0),
2551 },
2552 { /* end: all zeroes */ }
2553 };
2554
2555 static struct pci_driver knl_uncore_pci_driver = {
2556 .name = "knl_uncore",
2557 .id_table = knl_uncore_pci_ids,
2558 };
2559
knl_uncore_pci_init(void)2560 int knl_uncore_pci_init(void)
2561 {
2562 int ret;
2563
2564 /* All KNL PCI based PMON units are on the same PCI bus except IRP */
2565 ret = snb_pci2phy_map_init(0x7814); /* IRP */
2566 if (ret)
2567 return ret;
2568 ret = snb_pci2phy_map_init(0x7817); /* M2PCIe */
2569 if (ret)
2570 return ret;
2571 uncore_pci_uncores = knl_pci_uncores;
2572 uncore_pci_driver = &knl_uncore_pci_driver;
2573 return 0;
2574 }
2575
2576 /* end of KNL uncore support */
2577
2578 /* Haswell-EP uncore support */
2579 static struct attribute *hswep_uncore_ubox_formats_attr[] = {
2580 &format_attr_event.attr,
2581 &format_attr_umask.attr,
2582 &format_attr_edge.attr,
2583 &format_attr_inv.attr,
2584 &format_attr_thresh5.attr,
2585 &format_attr_filter_tid2.attr,
2586 &format_attr_filter_cid.attr,
2587 NULL,
2588 };
2589
2590 static const struct attribute_group hswep_uncore_ubox_format_group = {
2591 .name = "format",
2592 .attrs = hswep_uncore_ubox_formats_attr,
2593 };
2594
hswep_ubox_hw_config(struct intel_uncore_box * box,struct perf_event * event)2595 static int hswep_ubox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
2596 {
2597 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
2598 reg1->reg = HSWEP_U_MSR_PMON_FILTER;
2599 reg1->config = event->attr.config1 & HSWEP_U_MSR_PMON_BOX_FILTER_MASK;
2600 reg1->idx = 0;
2601 return 0;
2602 }
2603
2604 static struct intel_uncore_ops hswep_uncore_ubox_ops = {
2605 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
2606 .hw_config = hswep_ubox_hw_config,
2607 .get_constraint = uncore_get_constraint,
2608 .put_constraint = uncore_put_constraint,
2609 };
2610
2611 static struct intel_uncore_type hswep_uncore_ubox = {
2612 .name = "ubox",
2613 .num_counters = 2,
2614 .num_boxes = 1,
2615 .perf_ctr_bits = 44,
2616 .fixed_ctr_bits = 48,
2617 .perf_ctr = HSWEP_U_MSR_PMON_CTR0,
2618 .event_ctl = HSWEP_U_MSR_PMON_CTL0,
2619 .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
2620 .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR,
2621 .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL,
2622 .num_shared_regs = 1,
2623 .ops = &hswep_uncore_ubox_ops,
2624 .format_group = &hswep_uncore_ubox_format_group,
2625 };
2626
2627 static struct attribute *hswep_uncore_cbox_formats_attr[] = {
2628 &format_attr_event.attr,
2629 &format_attr_umask.attr,
2630 &format_attr_edge.attr,
2631 &format_attr_tid_en.attr,
2632 &format_attr_thresh8.attr,
2633 &format_attr_filter_tid3.attr,
2634 &format_attr_filter_link2.attr,
2635 &format_attr_filter_state3.attr,
2636 &format_attr_filter_nid2.attr,
2637 &format_attr_filter_opc2.attr,
2638 &format_attr_filter_nc.attr,
2639 &format_attr_filter_c6.attr,
2640 &format_attr_filter_isoc.attr,
2641 NULL,
2642 };
2643
2644 static const struct attribute_group hswep_uncore_cbox_format_group = {
2645 .name = "format",
2646 .attrs = hswep_uncore_cbox_formats_attr,
2647 };
2648
2649 static struct event_constraint hswep_uncore_cbox_constraints[] = {
2650 UNCORE_EVENT_CONSTRAINT(0x01, 0x1),
2651 UNCORE_EVENT_CONSTRAINT(0x09, 0x1),
2652 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
2653 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
2654 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
2655 UNCORE_EVENT_CONSTRAINT(0x3b, 0x1),
2656 UNCORE_EVENT_CONSTRAINT(0x3e, 0x1),
2657 EVENT_CONSTRAINT_END
2658 };
2659
2660 static struct extra_reg hswep_uncore_cbox_extra_regs[] = {
2661 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
2662 SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
2663 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
2664 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
2665 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
2666 SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4),
2667 SNBEP_CBO_EVENT_EXTRA_REG(0x2134, 0xffff, 0x4),
2668 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x4),
2669 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x8),
2670 SNBEP_CBO_EVENT_EXTRA_REG(0x4028, 0x40ff, 0x8),
2671 SNBEP_CBO_EVENT_EXTRA_REG(0x4032, 0x40ff, 0x8),
2672 SNBEP_CBO_EVENT_EXTRA_REG(0x4029, 0x40ff, 0x8),
2673 SNBEP_CBO_EVENT_EXTRA_REG(0x4033, 0x40ff, 0x8),
2674 SNBEP_CBO_EVENT_EXTRA_REG(0x402A, 0x40ff, 0x8),
2675 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x12),
2676 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10),
2677 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0x18),
2678 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x8),
2679 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x8),
2680 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x8),
2681 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0x18),
2682 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x8),
2683 SNBEP_CBO_EVENT_EXTRA_REG(0x2335, 0xffff, 0x10),
2684 SNBEP_CBO_EVENT_EXTRA_REG(0x8335, 0xffff, 0x10),
2685 SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10),
2686 SNBEP_CBO_EVENT_EXTRA_REG(0x8135, 0xffff, 0x10),
2687 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x10),
2688 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x10),
2689 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0x18),
2690 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x8),
2691 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x8),
2692 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0x18),
2693 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x8),
2694 SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10),
2695 SNBEP_CBO_EVENT_EXTRA_REG(0x8336, 0xffff, 0x10),
2696 SNBEP_CBO_EVENT_EXTRA_REG(0x2136, 0xffff, 0x10),
2697 SNBEP_CBO_EVENT_EXTRA_REG(0x8136, 0xffff, 0x10),
2698 SNBEP_CBO_EVENT_EXTRA_REG(0x5036, 0xffff, 0x8),
2699 EVENT_EXTRA_END
2700 };
2701
hswep_cbox_filter_mask(int fields)2702 static u64 hswep_cbox_filter_mask(int fields)
2703 {
2704 u64 mask = 0;
2705 if (fields & 0x1)
2706 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_TID;
2707 if (fields & 0x2)
2708 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_LINK;
2709 if (fields & 0x4)
2710 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_STATE;
2711 if (fields & 0x8)
2712 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_NID;
2713 if (fields & 0x10) {
2714 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_OPC;
2715 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_NC;
2716 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_C6;
2717 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_ISOC;
2718 }
2719 return mask;
2720 }
2721
2722 static struct event_constraint *
hswep_cbox_get_constraint(struct intel_uncore_box * box,struct perf_event * event)2723 hswep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
2724 {
2725 return __snbep_cbox_get_constraint(box, event, hswep_cbox_filter_mask);
2726 }
2727
hswep_cbox_hw_config(struct intel_uncore_box * box,struct perf_event * event)2728 static int hswep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
2729 {
2730 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
2731 struct extra_reg *er;
2732 int idx = 0;
2733
2734 for (er = hswep_uncore_cbox_extra_regs; er->msr; er++) {
2735 if (er->event != (event->hw.config & er->config_mask))
2736 continue;
2737 idx |= er->idx;
2738 }
2739
2740 if (idx) {
2741 reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 +
2742 HSWEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
2743 reg1->config = event->attr.config1 & hswep_cbox_filter_mask(idx);
2744 reg1->idx = idx;
2745 }
2746 return 0;
2747 }
2748
hswep_cbox_enable_event(struct intel_uncore_box * box,struct perf_event * event)2749 static void hswep_cbox_enable_event(struct intel_uncore_box *box,
2750 struct perf_event *event)
2751 {
2752 struct hw_perf_event *hwc = &event->hw;
2753 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2754
2755 if (reg1->idx != EXTRA_REG_NONE) {
2756 u64 filter = uncore_shared_reg_config(box, 0);
2757 wrmsrq(reg1->reg, filter & 0xffffffff);
2758 wrmsrq(reg1->reg + 1, filter >> 32);
2759 }
2760
2761 wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
2762 }
2763
2764 static struct intel_uncore_ops hswep_uncore_cbox_ops = {
2765 .init_box = snbep_uncore_msr_init_box,
2766 .disable_box = snbep_uncore_msr_disable_box,
2767 .enable_box = snbep_uncore_msr_enable_box,
2768 .disable_event = snbep_uncore_msr_disable_event,
2769 .enable_event = hswep_cbox_enable_event,
2770 .read_counter = uncore_msr_read_counter,
2771 .hw_config = hswep_cbox_hw_config,
2772 .get_constraint = hswep_cbox_get_constraint,
2773 .put_constraint = snbep_cbox_put_constraint,
2774 };
2775
2776 static struct intel_uncore_type hswep_uncore_cbox = {
2777 .name = "cbox",
2778 .num_counters = 4,
2779 .num_boxes = 18,
2780 .perf_ctr_bits = 48,
2781 .event_ctl = HSWEP_C0_MSR_PMON_CTL0,
2782 .perf_ctr = HSWEP_C0_MSR_PMON_CTR0,
2783 .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
2784 .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL,
2785 .msr_offset = HSWEP_CBO_MSR_OFFSET,
2786 .num_shared_regs = 1,
2787 .constraints = hswep_uncore_cbox_constraints,
2788 .ops = &hswep_uncore_cbox_ops,
2789 .format_group = &hswep_uncore_cbox_format_group,
2790 };
2791
2792 /*
2793 * Write SBOX Initialization register bit by bit to avoid spurious #GPs
2794 */
hswep_uncore_sbox_msr_init_box(struct intel_uncore_box * box)2795 static int hswep_uncore_sbox_msr_init_box(struct intel_uncore_box *box)
2796 {
2797 unsigned msr = uncore_msr_box_ctl(box);
2798
2799 if (msr) {
2800 u64 init = SNBEP_PMON_BOX_CTL_INT;
2801 u64 flags = 0;
2802 int i;
2803
2804 for_each_set_bit(i, (unsigned long *)&init, 64) {
2805 flags |= (1ULL << i);
2806 wrmsrq(msr, flags);
2807 }
2808 }
2809
2810 return 0;
2811 }
2812
2813 static struct intel_uncore_ops hswep_uncore_sbox_msr_ops = {
2814 __SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
2815 .init_box = hswep_uncore_sbox_msr_init_box
2816 };
2817
2818 static struct attribute *hswep_uncore_sbox_formats_attr[] = {
2819 &format_attr_event.attr,
2820 &format_attr_umask.attr,
2821 &format_attr_edge.attr,
2822 &format_attr_tid_en.attr,
2823 &format_attr_inv.attr,
2824 &format_attr_thresh8.attr,
2825 NULL,
2826 };
2827
2828 static const struct attribute_group hswep_uncore_sbox_format_group = {
2829 .name = "format",
2830 .attrs = hswep_uncore_sbox_formats_attr,
2831 };
2832
2833 static struct intel_uncore_type hswep_uncore_sbox = {
2834 .name = "sbox",
2835 .num_counters = 4,
2836 .num_boxes = 4,
2837 .perf_ctr_bits = 44,
2838 .event_ctl = HSWEP_S0_MSR_PMON_CTL0,
2839 .perf_ctr = HSWEP_S0_MSR_PMON_CTR0,
2840 .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK,
2841 .box_ctl = HSWEP_S0_MSR_PMON_BOX_CTL,
2842 .msr_offset = HSWEP_SBOX_MSR_OFFSET,
2843 .ops = &hswep_uncore_sbox_msr_ops,
2844 .format_group = &hswep_uncore_sbox_format_group,
2845 };
2846
hswep_pcu_hw_config(struct intel_uncore_box * box,struct perf_event * event)2847 static int hswep_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event)
2848 {
2849 struct hw_perf_event *hwc = &event->hw;
2850 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2851 int ev_sel = hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK;
2852
2853 if (ev_sel >= 0xb && ev_sel <= 0xe) {
2854 reg1->reg = HSWEP_PCU_MSR_PMON_BOX_FILTER;
2855 reg1->idx = ev_sel - 0xb;
2856 reg1->config = event->attr.config1 & (0xff << reg1->idx);
2857 }
2858 return 0;
2859 }
2860
2861 static struct intel_uncore_ops hswep_uncore_pcu_ops = {
2862 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
2863 .hw_config = hswep_pcu_hw_config,
2864 .get_constraint = snbep_pcu_get_constraint,
2865 .put_constraint = snbep_pcu_put_constraint,
2866 };
2867
2868 static struct intel_uncore_type hswep_uncore_pcu = {
2869 .name = "pcu",
2870 .num_counters = 4,
2871 .num_boxes = 1,
2872 .perf_ctr_bits = 48,
2873 .perf_ctr = HSWEP_PCU_MSR_PMON_CTR0,
2874 .event_ctl = HSWEP_PCU_MSR_PMON_CTL0,
2875 .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
2876 .box_ctl = HSWEP_PCU_MSR_PMON_BOX_CTL,
2877 .num_shared_regs = 1,
2878 .ops = &hswep_uncore_pcu_ops,
2879 .format_group = &snbep_uncore_pcu_format_group,
2880 };
2881
2882 static struct intel_uncore_type *hswep_msr_uncores[] = {
2883 &hswep_uncore_ubox,
2884 &hswep_uncore_cbox,
2885 &hswep_uncore_sbox,
2886 &hswep_uncore_pcu,
2887 NULL,
2888 };
2889
2890 #define HSWEP_PCU_DID 0x2fc0
2891 #define HSWEP_PCU_CAPID4_OFFET 0x94
2892 #define hswep_get_chop(_cap) (((_cap) >> 6) & 0x3)
2893
hswep_has_limit_sbox(unsigned int device)2894 static bool hswep_has_limit_sbox(unsigned int device)
2895 {
2896 struct pci_dev *dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2897 u32 capid4;
2898
2899 if (!dev)
2900 return false;
2901
2902 pci_read_config_dword(dev, HSWEP_PCU_CAPID4_OFFET, &capid4);
2903 pci_dev_put(dev);
2904 if (!hswep_get_chop(capid4))
2905 return true;
2906
2907 return false;
2908 }
2909
hswep_uncore_cpu_init(void)2910 void hswep_uncore_cpu_init(void)
2911 {
2912 if (hswep_uncore_cbox.num_boxes > topology_num_cores_per_package())
2913 hswep_uncore_cbox.num_boxes = topology_num_cores_per_package();
2914
2915 /* Detect 6-8 core systems with only two SBOXes */
2916 if (hswep_has_limit_sbox(HSWEP_PCU_DID))
2917 hswep_uncore_sbox.num_boxes = 2;
2918
2919 uncore_msr_uncores = hswep_msr_uncores;
2920 }
2921
2922 static struct intel_uncore_type hswep_uncore_ha = {
2923 .name = "ha",
2924 .num_counters = 4,
2925 .num_boxes = 2,
2926 .perf_ctr_bits = 48,
2927 SNBEP_UNCORE_PCI_COMMON_INIT(),
2928 };
2929
2930 static struct uncore_event_desc hswep_uncore_imc_events[] = {
2931 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x00,umask=0x00"),
2932 INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x03"),
2933 INTEL_UNCORE_EVENT_DESC(cas_count_read.scale, "6.103515625e-5"),
2934 INTEL_UNCORE_EVENT_DESC(cas_count_read.unit, "MiB"),
2935 INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"),
2936 INTEL_UNCORE_EVENT_DESC(cas_count_write.scale, "6.103515625e-5"),
2937 INTEL_UNCORE_EVENT_DESC(cas_count_write.unit, "MiB"),
2938 { /* end: all zeroes */ },
2939 };
2940
2941 static struct intel_uncore_type hswep_uncore_imc = {
2942 .name = "imc",
2943 .num_counters = 4,
2944 .num_boxes = 8,
2945 .perf_ctr_bits = 48,
2946 .fixed_ctr_bits = 48,
2947 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
2948 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
2949 .event_descs = hswep_uncore_imc_events,
2950 SNBEP_UNCORE_PCI_COMMON_INIT(),
2951 };
2952
2953 static unsigned hswep_uncore_irp_ctrs[] = {0xa0, 0xa8, 0xb0, 0xb8};
2954
hswep_uncore_irp_read_counter(struct intel_uncore_box * box,struct perf_event * event)2955 static u64 hswep_uncore_irp_read_counter(struct intel_uncore_box *box, struct perf_event *event)
2956 {
2957 struct pci_dev *pdev = box->pci_dev;
2958 struct hw_perf_event *hwc = &event->hw;
2959 u64 count = 0;
2960
2961 pci_read_config_dword(pdev, hswep_uncore_irp_ctrs[hwc->idx], (u32 *)&count);
2962 pci_read_config_dword(pdev, hswep_uncore_irp_ctrs[hwc->idx] + 4, (u32 *)&count + 1);
2963
2964 return count;
2965 }
2966
2967 static struct intel_uncore_ops hswep_uncore_irp_ops = {
2968 .init_box = snbep_uncore_pci_init_box,
2969 .disable_box = snbep_uncore_pci_disable_box,
2970 .enable_box = snbep_uncore_pci_enable_box,
2971 .disable_event = ivbep_uncore_irp_disable_event,
2972 .enable_event = ivbep_uncore_irp_enable_event,
2973 .read_counter = hswep_uncore_irp_read_counter,
2974 };
2975
2976 static struct intel_uncore_type hswep_uncore_irp = {
2977 .name = "irp",
2978 .num_counters = 4,
2979 .num_boxes = 1,
2980 .perf_ctr_bits = 48,
2981 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
2982 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
2983 .ops = &hswep_uncore_irp_ops,
2984 .format_group = &snbep_uncore_format_group,
2985 };
2986
2987 static struct intel_uncore_type hswep_uncore_qpi = {
2988 .name = "qpi",
2989 .num_counters = 4,
2990 .num_boxes = 3,
2991 .perf_ctr_bits = 48,
2992 .perf_ctr = SNBEP_PCI_PMON_CTR0,
2993 .event_ctl = SNBEP_PCI_PMON_CTL0,
2994 .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK,
2995 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
2996 .num_shared_regs = 1,
2997 .ops = &snbep_uncore_qpi_ops,
2998 .format_group = &snbep_uncore_qpi_format_group,
2999 };
3000
3001 static struct event_constraint hswep_uncore_r2pcie_constraints[] = {
3002 UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x11, 0x3),
3003 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
3004 UNCORE_EVENT_CONSTRAINT_RANGE(0x23, 0x25, 0x1),
3005 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
3006 UNCORE_EVENT_CONSTRAINT(0x27, 0x1),
3007 UNCORE_EVENT_CONSTRAINT_RANGE(0x28, 0x29, 0x3),
3008 UNCORE_EVENT_CONSTRAINT(0x2a, 0x1),
3009 UNCORE_EVENT_CONSTRAINT_RANGE(0x2b, 0x2d, 0x3),
3010 UNCORE_EVENT_CONSTRAINT_RANGE(0x32, 0x35, 0x3),
3011 EVENT_CONSTRAINT_END
3012 };
3013
3014 static struct intel_uncore_type hswep_uncore_r2pcie = {
3015 .name = "r2pcie",
3016 .num_counters = 4,
3017 .num_boxes = 1,
3018 .perf_ctr_bits = 48,
3019 .constraints = hswep_uncore_r2pcie_constraints,
3020 SNBEP_UNCORE_PCI_COMMON_INIT(),
3021 };
3022
3023 static struct event_constraint hswep_uncore_r3qpi_constraints[] = {
3024 UNCORE_EVENT_CONSTRAINT(0x01, 0x3),
3025 UNCORE_EVENT_CONSTRAINT_RANGE(0x7, 0x0a, 0x7),
3026 UNCORE_EVENT_CONSTRAINT(0x0e, 0x7),
3027 UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x12, 0x3),
3028 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
3029 UNCORE_EVENT_CONSTRAINT_RANGE(0x14, 0x15, 0x3),
3030 UNCORE_EVENT_CONSTRAINT_RANGE(0x1f, 0x23, 0x3),
3031 UNCORE_EVENT_CONSTRAINT_RANGE(0x25, 0x26, 0x3),
3032 UNCORE_EVENT_CONSTRAINT_RANGE(0x28, 0x29, 0x3),
3033 UNCORE_EVENT_CONSTRAINT_RANGE(0x2c, 0x2f, 0x3),
3034 UNCORE_EVENT_CONSTRAINT_RANGE(0x31, 0x34, 0x3),
3035 UNCORE_EVENT_CONSTRAINT_RANGE(0x36, 0x39, 0x3),
3036 EVENT_CONSTRAINT_END
3037 };
3038
3039 static struct intel_uncore_type hswep_uncore_r3qpi = {
3040 .name = "r3qpi",
3041 .num_counters = 3,
3042 .num_boxes = 3,
3043 .perf_ctr_bits = 44,
3044 .constraints = hswep_uncore_r3qpi_constraints,
3045 SNBEP_UNCORE_PCI_COMMON_INIT(),
3046 };
3047
3048 enum {
3049 HSWEP_PCI_UNCORE_HA,
3050 HSWEP_PCI_UNCORE_IMC,
3051 HSWEP_PCI_UNCORE_IRP,
3052 HSWEP_PCI_UNCORE_QPI,
3053 HSWEP_PCI_UNCORE_R2PCIE,
3054 HSWEP_PCI_UNCORE_R3QPI,
3055 };
3056
3057 static struct intel_uncore_type *hswep_pci_uncores[] = {
3058 [HSWEP_PCI_UNCORE_HA] = &hswep_uncore_ha,
3059 [HSWEP_PCI_UNCORE_IMC] = &hswep_uncore_imc,
3060 [HSWEP_PCI_UNCORE_IRP] = &hswep_uncore_irp,
3061 [HSWEP_PCI_UNCORE_QPI] = &hswep_uncore_qpi,
3062 [HSWEP_PCI_UNCORE_R2PCIE] = &hswep_uncore_r2pcie,
3063 [HSWEP_PCI_UNCORE_R3QPI] = &hswep_uncore_r3qpi,
3064 NULL,
3065 };
3066
3067 static const struct pci_device_id hswep_uncore_pci_ids[] = {
3068 { /* Home Agent 0 */
3069 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f30),
3070 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_HA, 0),
3071 },
3072 { /* Home Agent 1 */
3073 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f38),
3074 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_HA, 1),
3075 },
3076 { /* MC0 Channel 0 */
3077 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb0),
3078 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 0),
3079 },
3080 { /* MC0 Channel 1 */
3081 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb1),
3082 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 1),
3083 },
3084 { /* MC0 Channel 2 */
3085 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb4),
3086 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 2),
3087 },
3088 { /* MC0 Channel 3 */
3089 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb5),
3090 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 3),
3091 },
3092 { /* MC1 Channel 0 */
3093 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd0),
3094 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 4),
3095 },
3096 { /* MC1 Channel 1 */
3097 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd1),
3098 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 5),
3099 },
3100 { /* MC1 Channel 2 */
3101 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd4),
3102 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 6),
3103 },
3104 { /* MC1 Channel 3 */
3105 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd5),
3106 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 7),
3107 },
3108 { /* IRP */
3109 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f39),
3110 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IRP, 0),
3111 },
3112 { /* QPI0 Port 0 */
3113 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f32),
3114 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_QPI, 0),
3115 },
3116 { /* QPI0 Port 1 */
3117 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f33),
3118 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_QPI, 1),
3119 },
3120 { /* QPI1 Port 2 */
3121 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f3a),
3122 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_QPI, 2),
3123 },
3124 { /* R2PCIe */
3125 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f34),
3126 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R2PCIE, 0),
3127 },
3128 { /* R3QPI0 Link 0 */
3129 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f36),
3130 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R3QPI, 0),
3131 },
3132 { /* R3QPI0 Link 1 */
3133 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f37),
3134 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R3QPI, 1),
3135 },
3136 { /* R3QPI1 Link 2 */
3137 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f3e),
3138 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R3QPI, 2),
3139 },
3140 { /* QPI Port 0 filter */
3141 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f86),
3142 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
3143 SNBEP_PCI_QPI_PORT0_FILTER),
3144 },
3145 { /* QPI Port 1 filter */
3146 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f96),
3147 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
3148 SNBEP_PCI_QPI_PORT1_FILTER),
3149 },
3150 { /* end: all zeroes */ }
3151 };
3152
3153 static struct pci_driver hswep_uncore_pci_driver = {
3154 .name = "hswep_uncore",
3155 .id_table = hswep_uncore_pci_ids,
3156 };
3157
hswep_uncore_pci_init(void)3158 int hswep_uncore_pci_init(void)
3159 {
3160 int ret = snbep_pci2phy_map_init(0x2f1e, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true);
3161 if (ret)
3162 return ret;
3163 uncore_pci_uncores = hswep_pci_uncores;
3164 uncore_pci_driver = &hswep_uncore_pci_driver;
3165 return 0;
3166 }
3167 /* end of Haswell-EP uncore support */
3168
3169 /* BDX uncore support */
3170
3171 static struct intel_uncore_type bdx_uncore_ubox = {
3172 .name = "ubox",
3173 .num_counters = 2,
3174 .num_boxes = 1,
3175 .perf_ctr_bits = 48,
3176 .fixed_ctr_bits = 48,
3177 .perf_ctr = HSWEP_U_MSR_PMON_CTR0,
3178 .event_ctl = HSWEP_U_MSR_PMON_CTL0,
3179 .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
3180 .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR,
3181 .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL,
3182 .num_shared_regs = 1,
3183 .ops = &ivbep_uncore_msr_ops,
3184 .format_group = &ivbep_uncore_ubox_format_group,
3185 };
3186
3187 static struct event_constraint bdx_uncore_cbox_constraints[] = {
3188 UNCORE_EVENT_CONSTRAINT(0x09, 0x3),
3189 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
3190 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
3191 UNCORE_EVENT_CONSTRAINT(0x3e, 0x1),
3192 EVENT_CONSTRAINT_END
3193 };
3194
3195 static struct intel_uncore_type bdx_uncore_cbox = {
3196 .name = "cbox",
3197 .num_counters = 4,
3198 .num_boxes = 24,
3199 .perf_ctr_bits = 48,
3200 .event_ctl = HSWEP_C0_MSR_PMON_CTL0,
3201 .perf_ctr = HSWEP_C0_MSR_PMON_CTR0,
3202 .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
3203 .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL,
3204 .msr_offset = HSWEP_CBO_MSR_OFFSET,
3205 .num_shared_regs = 1,
3206 .constraints = bdx_uncore_cbox_constraints,
3207 .ops = &hswep_uncore_cbox_ops,
3208 .format_group = &hswep_uncore_cbox_format_group,
3209 };
3210
3211 static struct intel_uncore_type bdx_uncore_sbox = {
3212 .name = "sbox",
3213 .num_counters = 4,
3214 .num_boxes = 4,
3215 .perf_ctr_bits = 48,
3216 .event_ctl = HSWEP_S0_MSR_PMON_CTL0,
3217 .perf_ctr = HSWEP_S0_MSR_PMON_CTR0,
3218 .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK,
3219 .box_ctl = HSWEP_S0_MSR_PMON_BOX_CTL,
3220 .msr_offset = HSWEP_SBOX_MSR_OFFSET,
3221 .ops = &hswep_uncore_sbox_msr_ops,
3222 .format_group = &hswep_uncore_sbox_format_group,
3223 };
3224
3225 #define BDX_MSR_UNCORE_SBOX 3
3226
3227 static struct intel_uncore_type *bdx_msr_uncores[] = {
3228 &bdx_uncore_ubox,
3229 &bdx_uncore_cbox,
3230 &hswep_uncore_pcu,
3231 &bdx_uncore_sbox,
3232 NULL,
3233 };
3234
3235 /* Bit 7 'Use Occupancy' is not available for counter 0 on BDX */
3236 static struct event_constraint bdx_uncore_pcu_constraints[] = {
3237 EVENT_CONSTRAINT(0x80, 0xe, 0x80),
3238 EVENT_CONSTRAINT_END
3239 };
3240
3241 #define BDX_PCU_DID 0x6fc0
3242
bdx_uncore_cpu_init(void)3243 void bdx_uncore_cpu_init(void)
3244 {
3245 if (bdx_uncore_cbox.num_boxes > topology_num_cores_per_package())
3246 bdx_uncore_cbox.num_boxes = topology_num_cores_per_package();
3247 uncore_msr_uncores = bdx_msr_uncores;
3248
3249 /* Detect systems with no SBOXes */
3250 if (boot_cpu_data.x86_vfm == INTEL_BROADWELL_D || hswep_has_limit_sbox(BDX_PCU_DID))
3251 uncore_msr_uncores[BDX_MSR_UNCORE_SBOX] = NULL;
3252
3253 hswep_uncore_pcu.constraints = bdx_uncore_pcu_constraints;
3254 }
3255
3256 static struct intel_uncore_type bdx_uncore_ha = {
3257 .name = "ha",
3258 .num_counters = 4,
3259 .num_boxes = 2,
3260 .perf_ctr_bits = 48,
3261 SNBEP_UNCORE_PCI_COMMON_INIT(),
3262 };
3263
3264 static struct intel_uncore_type bdx_uncore_imc = {
3265 .name = "imc",
3266 .num_counters = 4,
3267 .num_boxes = 8,
3268 .perf_ctr_bits = 48,
3269 .fixed_ctr_bits = 48,
3270 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
3271 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
3272 .event_descs = hswep_uncore_imc_events,
3273 SNBEP_UNCORE_PCI_COMMON_INIT(),
3274 };
3275
3276 static struct intel_uncore_type bdx_uncore_irp = {
3277 .name = "irp",
3278 .num_counters = 4,
3279 .num_boxes = 1,
3280 .perf_ctr_bits = 48,
3281 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
3282 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
3283 .ops = &hswep_uncore_irp_ops,
3284 .format_group = &snbep_uncore_format_group,
3285 };
3286
3287 static struct intel_uncore_type bdx_uncore_qpi = {
3288 .name = "qpi",
3289 .num_counters = 4,
3290 .num_boxes = 3,
3291 .perf_ctr_bits = 48,
3292 .perf_ctr = SNBEP_PCI_PMON_CTR0,
3293 .event_ctl = SNBEP_PCI_PMON_CTL0,
3294 .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK,
3295 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
3296 .num_shared_regs = 1,
3297 .ops = &snbep_uncore_qpi_ops,
3298 .format_group = &snbep_uncore_qpi_format_group,
3299 };
3300
3301 static struct event_constraint bdx_uncore_r2pcie_constraints[] = {
3302 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
3303 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
3304 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
3305 UNCORE_EVENT_CONSTRAINT(0x23, 0x1),
3306 UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
3307 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
3308 UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
3309 UNCORE_EVENT_CONSTRAINT_RANGE(0x2c, 0x2d, 0x3),
3310 EVENT_CONSTRAINT_END
3311 };
3312
3313 static struct intel_uncore_type bdx_uncore_r2pcie = {
3314 .name = "r2pcie",
3315 .num_counters = 4,
3316 .num_boxes = 1,
3317 .perf_ctr_bits = 48,
3318 .constraints = bdx_uncore_r2pcie_constraints,
3319 SNBEP_UNCORE_PCI_COMMON_INIT(),
3320 };
3321
3322 static struct event_constraint bdx_uncore_r3qpi_constraints[] = {
3323 UNCORE_EVENT_CONSTRAINT(0x01, 0x7),
3324 UNCORE_EVENT_CONSTRAINT_RANGE(0x07, 0x0a, 0x7),
3325 UNCORE_EVENT_CONSTRAINT(0x0e, 0x7),
3326 UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x11, 0x3),
3327 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
3328 UNCORE_EVENT_CONSTRAINT_RANGE(0x14, 0x15, 0x3),
3329 UNCORE_EVENT_CONSTRAINT_RANGE(0x1f, 0x23, 0x3),
3330 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
3331 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
3332 UNCORE_EVENT_CONSTRAINT_RANGE(0x28, 0x29, 0x3),
3333 UNCORE_EVENT_CONSTRAINT_RANGE(0x2c, 0x2f, 0x3),
3334 UNCORE_EVENT_CONSTRAINT_RANGE(0x33, 0x34, 0x3),
3335 UNCORE_EVENT_CONSTRAINT_RANGE(0x36, 0x39, 0x3),
3336 EVENT_CONSTRAINT_END
3337 };
3338
3339 static struct intel_uncore_type bdx_uncore_r3qpi = {
3340 .name = "r3qpi",
3341 .num_counters = 3,
3342 .num_boxes = 3,
3343 .perf_ctr_bits = 48,
3344 .constraints = bdx_uncore_r3qpi_constraints,
3345 SNBEP_UNCORE_PCI_COMMON_INIT(),
3346 };
3347
3348 enum {
3349 BDX_PCI_UNCORE_HA,
3350 BDX_PCI_UNCORE_IMC,
3351 BDX_PCI_UNCORE_IRP,
3352 BDX_PCI_UNCORE_QPI,
3353 BDX_PCI_UNCORE_R2PCIE,
3354 BDX_PCI_UNCORE_R3QPI,
3355 };
3356
3357 static struct intel_uncore_type *bdx_pci_uncores[] = {
3358 [BDX_PCI_UNCORE_HA] = &bdx_uncore_ha,
3359 [BDX_PCI_UNCORE_IMC] = &bdx_uncore_imc,
3360 [BDX_PCI_UNCORE_IRP] = &bdx_uncore_irp,
3361 [BDX_PCI_UNCORE_QPI] = &bdx_uncore_qpi,
3362 [BDX_PCI_UNCORE_R2PCIE] = &bdx_uncore_r2pcie,
3363 [BDX_PCI_UNCORE_R3QPI] = &bdx_uncore_r3qpi,
3364 NULL,
3365 };
3366
3367 static const struct pci_device_id bdx_uncore_pci_ids[] = {
3368 { /* Home Agent 0 */
3369 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f30),
3370 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_HA, 0),
3371 },
3372 { /* Home Agent 1 */
3373 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f38),
3374 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_HA, 1),
3375 },
3376 { /* MC0 Channel 0 */
3377 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb0),
3378 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 0),
3379 },
3380 { /* MC0 Channel 1 */
3381 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb1),
3382 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 1),
3383 },
3384 { /* MC0 Channel 2 */
3385 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb4),
3386 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 2),
3387 },
3388 { /* MC0 Channel 3 */
3389 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb5),
3390 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 3),
3391 },
3392 { /* MC1 Channel 0 */
3393 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd0),
3394 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 4),
3395 },
3396 { /* MC1 Channel 1 */
3397 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd1),
3398 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 5),
3399 },
3400 { /* MC1 Channel 2 */
3401 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd4),
3402 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 6),
3403 },
3404 { /* MC1 Channel 3 */
3405 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd5),
3406 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 7),
3407 },
3408 { /* IRP */
3409 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f39),
3410 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IRP, 0),
3411 },
3412 { /* QPI0 Port 0 */
3413 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f32),
3414 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_QPI, 0),
3415 },
3416 { /* QPI0 Port 1 */
3417 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f33),
3418 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_QPI, 1),
3419 },
3420 { /* QPI1 Port 2 */
3421 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f3a),
3422 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_QPI, 2),
3423 },
3424 { /* R2PCIe */
3425 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f34),
3426 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R2PCIE, 0),
3427 },
3428 { /* R3QPI0 Link 0 */
3429 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f36),
3430 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R3QPI, 0),
3431 },
3432 { /* R3QPI0 Link 1 */
3433 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f37),
3434 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R3QPI, 1),
3435 },
3436 { /* R3QPI1 Link 2 */
3437 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f3e),
3438 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R3QPI, 2),
3439 },
3440 { /* QPI Port 0 filter */
3441 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f86),
3442 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
3443 SNBEP_PCI_QPI_PORT0_FILTER),
3444 },
3445 { /* QPI Port 1 filter */
3446 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f96),
3447 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
3448 SNBEP_PCI_QPI_PORT1_FILTER),
3449 },
3450 { /* QPI Port 2 filter */
3451 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f46),
3452 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
3453 BDX_PCI_QPI_PORT2_FILTER),
3454 },
3455 { /* end: all zeroes */ }
3456 };
3457
3458 static struct pci_driver bdx_uncore_pci_driver = {
3459 .name = "bdx_uncore",
3460 .id_table = bdx_uncore_pci_ids,
3461 };
3462
bdx_uncore_pci_init(void)3463 int bdx_uncore_pci_init(void)
3464 {
3465 int ret = snbep_pci2phy_map_init(0x6f1e, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true);
3466
3467 if (ret)
3468 return ret;
3469 uncore_pci_uncores = bdx_pci_uncores;
3470 uncore_pci_driver = &bdx_uncore_pci_driver;
3471 return 0;
3472 }
3473
3474 /* end of BDX uncore support */
3475
3476 /* SKX uncore support */
3477
3478 static struct intel_uncore_type skx_uncore_ubox = {
3479 .name = "ubox",
3480 .num_counters = 2,
3481 .num_boxes = 1,
3482 .perf_ctr_bits = 48,
3483 .fixed_ctr_bits = 48,
3484 .perf_ctr = HSWEP_U_MSR_PMON_CTR0,
3485 .event_ctl = HSWEP_U_MSR_PMON_CTL0,
3486 .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
3487 .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR,
3488 .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL,
3489 .ops = &ivbep_uncore_msr_ops,
3490 .format_group = &ivbep_uncore_ubox_format_group,
3491 };
3492
3493 static struct attribute *skx_uncore_cha_formats_attr[] = {
3494 &format_attr_event.attr,
3495 &format_attr_umask.attr,
3496 &format_attr_edge.attr,
3497 &format_attr_tid_en.attr,
3498 &format_attr_inv.attr,
3499 &format_attr_thresh8.attr,
3500 &format_attr_filter_tid4.attr,
3501 &format_attr_filter_state5.attr,
3502 &format_attr_filter_rem.attr,
3503 &format_attr_filter_loc.attr,
3504 &format_attr_filter_nm.attr,
3505 &format_attr_filter_all_op.attr,
3506 &format_attr_filter_not_nm.attr,
3507 &format_attr_filter_opc_0.attr,
3508 &format_attr_filter_opc_1.attr,
3509 &format_attr_filter_nc.attr,
3510 &format_attr_filter_isoc.attr,
3511 NULL,
3512 };
3513
3514 static const struct attribute_group skx_uncore_chabox_format_group = {
3515 .name = "format",
3516 .attrs = skx_uncore_cha_formats_attr,
3517 };
3518
3519 static struct event_constraint skx_uncore_chabox_constraints[] = {
3520 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
3521 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
3522 EVENT_CONSTRAINT_END
3523 };
3524
3525 static struct extra_reg skx_uncore_cha_extra_regs[] = {
3526 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
3527 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
3528 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
3529 SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4),
3530 SNBEP_CBO_EVENT_EXTRA_REG(0x3134, 0xffff, 0x4),
3531 SNBEP_CBO_EVENT_EXTRA_REG(0x9134, 0xffff, 0x4),
3532 SNBEP_CBO_EVENT_EXTRA_REG(0x35, 0xff, 0x8),
3533 SNBEP_CBO_EVENT_EXTRA_REG(0x36, 0xff, 0x8),
3534 SNBEP_CBO_EVENT_EXTRA_REG(0x38, 0xff, 0x3),
3535 EVENT_EXTRA_END
3536 };
3537
skx_cha_filter_mask(int fields)3538 static u64 skx_cha_filter_mask(int fields)
3539 {
3540 u64 mask = 0;
3541
3542 if (fields & 0x1)
3543 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_TID;
3544 if (fields & 0x2)
3545 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_LINK;
3546 if (fields & 0x4)
3547 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_STATE;
3548 if (fields & 0x8) {
3549 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_REM;
3550 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_LOC;
3551 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_ALL_OPC;
3552 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_NM;
3553 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_NOT_NM;
3554 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_OPC0;
3555 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_OPC1;
3556 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_NC;
3557 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_ISOC;
3558 }
3559 return mask;
3560 }
3561
3562 static struct event_constraint *
skx_cha_get_constraint(struct intel_uncore_box * box,struct perf_event * event)3563 skx_cha_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
3564 {
3565 return __snbep_cbox_get_constraint(box, event, skx_cha_filter_mask);
3566 }
3567
skx_cha_hw_config(struct intel_uncore_box * box,struct perf_event * event)3568 static int skx_cha_hw_config(struct intel_uncore_box *box, struct perf_event *event)
3569 {
3570 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
3571 struct extra_reg *er;
3572 int idx = 0;
3573 /* Any of the CHA events may be filtered by Thread/Core-ID.*/
3574 if (event->hw.config & SNBEP_CBO_PMON_CTL_TID_EN)
3575 idx = SKX_CHA_MSR_PMON_BOX_FILTER_TID;
3576
3577 for (er = skx_uncore_cha_extra_regs; er->msr; er++) {
3578 if (er->event != (event->hw.config & er->config_mask))
3579 continue;
3580 idx |= er->idx;
3581 }
3582
3583 if (idx) {
3584 reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 +
3585 HSWEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
3586 reg1->config = event->attr.config1 & skx_cha_filter_mask(idx);
3587 reg1->idx = idx;
3588 }
3589 return 0;
3590 }
3591
3592 static struct intel_uncore_ops skx_uncore_chabox_ops = {
3593 /* There is no frz_en for chabox ctl */
3594 .init_box = ivbep_uncore_msr_init_box,
3595 .disable_box = snbep_uncore_msr_disable_box,
3596 .enable_box = snbep_uncore_msr_enable_box,
3597 .disable_event = snbep_uncore_msr_disable_event,
3598 .enable_event = hswep_cbox_enable_event,
3599 .read_counter = uncore_msr_read_counter,
3600 .hw_config = skx_cha_hw_config,
3601 .get_constraint = skx_cha_get_constraint,
3602 .put_constraint = snbep_cbox_put_constraint,
3603 };
3604
3605 static struct intel_uncore_type skx_uncore_chabox = {
3606 .name = "cha",
3607 .num_counters = 4,
3608 .perf_ctr_bits = 48,
3609 .event_ctl = HSWEP_C0_MSR_PMON_CTL0,
3610 .perf_ctr = HSWEP_C0_MSR_PMON_CTR0,
3611 .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK,
3612 .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL,
3613 .msr_offset = HSWEP_CBO_MSR_OFFSET,
3614 .num_shared_regs = 1,
3615 .constraints = skx_uncore_chabox_constraints,
3616 .ops = &skx_uncore_chabox_ops,
3617 .format_group = &skx_uncore_chabox_format_group,
3618 };
3619
3620 static struct attribute *skx_uncore_iio_formats_attr[] = {
3621 &format_attr_event.attr,
3622 &format_attr_umask.attr,
3623 &format_attr_edge.attr,
3624 &format_attr_inv.attr,
3625 &format_attr_thresh9.attr,
3626 &format_attr_ch_mask.attr,
3627 &format_attr_fc_mask.attr,
3628 NULL,
3629 };
3630
3631 static const struct attribute_group skx_uncore_iio_format_group = {
3632 .name = "format",
3633 .attrs = skx_uncore_iio_formats_attr,
3634 };
3635
3636 static struct event_constraint skx_uncore_iio_constraints[] = {
3637 UNCORE_EVENT_CONSTRAINT(0x83, 0x3),
3638 UNCORE_EVENT_CONSTRAINT(0x88, 0xc),
3639 UNCORE_EVENT_CONSTRAINT(0x95, 0xc),
3640 UNCORE_EVENT_CONSTRAINT(0xc0, 0xc),
3641 UNCORE_EVENT_CONSTRAINT(0xc5, 0xc),
3642 UNCORE_EVENT_CONSTRAINT_RANGE(0xd4, 0xd5, 0xc),
3643 EVENT_CONSTRAINT_END
3644 };
3645
skx_iio_enable_event(struct intel_uncore_box * box,struct perf_event * event)3646 static void skx_iio_enable_event(struct intel_uncore_box *box,
3647 struct perf_event *event)
3648 {
3649 struct hw_perf_event *hwc = &event->hw;
3650
3651 wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
3652 }
3653
3654 static struct intel_uncore_ops skx_uncore_iio_ops = {
3655 .init_box = ivbep_uncore_msr_init_box,
3656 .disable_box = snbep_uncore_msr_disable_box,
3657 .enable_box = snbep_uncore_msr_enable_box,
3658 .disable_event = snbep_uncore_msr_disable_event,
3659 .enable_event = skx_iio_enable_event,
3660 .read_counter = uncore_msr_read_counter,
3661 };
3662
pmu_topology(struct intel_uncore_pmu * pmu,int die)3663 static struct intel_uncore_topology *pmu_topology(struct intel_uncore_pmu *pmu, int die)
3664 {
3665 int idx;
3666
3667 for (idx = 0; idx < pmu->type->num_boxes; idx++) {
3668 if (pmu->type->topology[die][idx].pmu_idx == pmu->pmu_idx)
3669 return &pmu->type->topology[die][idx];
3670 }
3671
3672 return NULL;
3673 }
3674
3675 static umode_t
pmu_iio_mapping_visible(struct kobject * kobj,struct attribute * attr,int die,int zero_bus_pmu)3676 pmu_iio_mapping_visible(struct kobject *kobj, struct attribute *attr,
3677 int die, int zero_bus_pmu)
3678 {
3679 struct intel_uncore_pmu *pmu = dev_to_uncore_pmu(kobj_to_dev(kobj));
3680 struct intel_uncore_topology *pmut = pmu_topology(pmu, die);
3681
3682 return (pmut && !pmut->iio->pci_bus_no && pmu->pmu_idx != zero_bus_pmu) ? 0 : attr->mode;
3683 }
3684
3685 static umode_t
skx_iio_mapping_visible(struct kobject * kobj,struct attribute * attr,int die)3686 skx_iio_mapping_visible(struct kobject *kobj, struct attribute *attr, int die)
3687 {
3688 /* Root bus 0x00 is valid only for pmu_idx = 0. */
3689 return pmu_iio_mapping_visible(kobj, attr, die, 0);
3690 }
3691
skx_iio_mapping_show(struct device * dev,struct device_attribute * attr,char * buf)3692 static ssize_t skx_iio_mapping_show(struct device *dev,
3693 struct device_attribute *attr, char *buf)
3694 {
3695 struct intel_uncore_pmu *pmu = dev_to_uncore_pmu(dev);
3696 struct dev_ext_attribute *ea = to_dev_ext_attribute(attr);
3697 long die = (long)ea->var;
3698 struct intel_uncore_topology *pmut = pmu_topology(pmu, die);
3699
3700 return sprintf(buf, "%04x:%02x\n", pmut ? pmut->iio->segment : 0,
3701 pmut ? pmut->iio->pci_bus_no : 0);
3702 }
3703
skx_msr_cpu_bus_read(int cpu,u64 * topology)3704 static int skx_msr_cpu_bus_read(int cpu, u64 *topology)
3705 {
3706 u64 msr_value;
3707
3708 if (rdmsrq_on_cpu(cpu, SKX_MSR_CPU_BUS_NUMBER, &msr_value) ||
3709 !(msr_value & SKX_MSR_CPU_BUS_VALID_BIT))
3710 return -ENXIO;
3711
3712 *topology = msr_value;
3713
3714 return 0;
3715 }
3716
3717 enum {
3718 IIO_TOPOLOGY_TYPE,
3719 UPI_TOPOLOGY_TYPE,
3720 TOPOLOGY_MAX
3721 };
3722
3723 static const size_t topology_size[TOPOLOGY_MAX] = {
3724 sizeof(*((struct intel_uncore_topology *)NULL)->iio),
3725 sizeof(*((struct intel_uncore_topology *)NULL)->upi)
3726 };
3727
pmu_alloc_topology(struct intel_uncore_type * type,int topology_type)3728 static int pmu_alloc_topology(struct intel_uncore_type *type, int topology_type)
3729 {
3730 int die, idx;
3731 struct intel_uncore_topology **topology;
3732
3733 if (!type->num_boxes)
3734 return -EPERM;
3735
3736 topology = kzalloc_objs(*topology, uncore_max_dies());
3737 if (!topology)
3738 goto err;
3739
3740 for (die = 0; die < uncore_max_dies(); die++) {
3741 topology[die] = kzalloc_objs(**topology, type->num_boxes);
3742 if (!topology[die])
3743 goto clear;
3744 for (idx = 0; idx < type->num_boxes; idx++) {
3745 topology[die][idx].untyped = kcalloc(type->num_boxes,
3746 topology_size[topology_type],
3747 GFP_KERNEL);
3748 if (!topology[die][idx].untyped)
3749 goto clear;
3750 }
3751 }
3752
3753 type->topology = topology;
3754
3755 return 0;
3756 clear:
3757 for (; die >= 0; die--) {
3758 for (idx = 0; idx < type->num_boxes; idx++)
3759 kfree(topology[die][idx].untyped);
3760 kfree(topology[die]);
3761 }
3762 kfree(topology);
3763 err:
3764 return -ENOMEM;
3765 }
3766
pmu_free_topology(struct intel_uncore_type * type)3767 static void pmu_free_topology(struct intel_uncore_type *type)
3768 {
3769 int die, idx;
3770
3771 if (type->topology) {
3772 for (die = 0; die < uncore_max_dies(); die++) {
3773 for (idx = 0; idx < type->num_boxes; idx++)
3774 kfree(type->topology[die][idx].untyped);
3775 kfree(type->topology[die]);
3776 }
3777 kfree(type->topology);
3778 type->topology = NULL;
3779 }
3780 }
3781
skx_pmu_get_topology(struct intel_uncore_type * type,int (* topology_cb)(struct intel_uncore_type *,int,int,u64))3782 static int skx_pmu_get_topology(struct intel_uncore_type *type,
3783 int (*topology_cb)(struct intel_uncore_type*, int, int, u64))
3784 {
3785 int die, ret = -ENODEV;
3786 u64 cpu_bus_msr;
3787 int cpu;
3788
3789 cpus_read_lock();
3790 for (die = 0; die < uncore_max_dies(); die++) {
3791 cpu = uncore_die_to_cpu(die);
3792 if (cpu == -1)
3793 continue;
3794
3795 ret = skx_msr_cpu_bus_read(cpu, &cpu_bus_msr);
3796 if (ret)
3797 break;
3798
3799 ret = uncore_die_to_segment(die);
3800 if (ret < 0)
3801 break;
3802
3803 ret = topology_cb(type, ret, die, cpu_bus_msr);
3804 if (ret)
3805 break;
3806 }
3807 cpus_read_unlock();
3808
3809 return ret;
3810 }
3811
skx_iio_topology_cb(struct intel_uncore_type * type,int segment,int die,u64 cpu_bus_msr)3812 static int skx_iio_topology_cb(struct intel_uncore_type *type, int segment,
3813 int die, u64 cpu_bus_msr)
3814 {
3815 int idx;
3816 struct intel_uncore_topology *t;
3817
3818 for (idx = 0; idx < type->num_boxes; idx++) {
3819 t = &type->topology[die][idx];
3820 t->pmu_idx = idx;
3821 t->iio->segment = segment;
3822 t->iio->pci_bus_no = (cpu_bus_msr >> (idx * BUS_NUM_STRIDE)) & 0xff;
3823 }
3824
3825 return 0;
3826 }
3827
skx_iio_get_topology(struct intel_uncore_type * type)3828 static int skx_iio_get_topology(struct intel_uncore_type *type)
3829 {
3830 return skx_pmu_get_topology(type, skx_iio_topology_cb);
3831 }
3832
3833 static struct attribute_group skx_iio_mapping_group = {
3834 .is_visible = skx_iio_mapping_visible,
3835 };
3836
3837 static const struct attribute_group *skx_iio_attr_update[] = {
3838 &skx_iio_mapping_group,
3839 NULL,
3840 };
3841
pmu_clear_mapping_attr(const struct attribute_group ** groups,struct attribute_group * ag)3842 static void pmu_clear_mapping_attr(const struct attribute_group **groups,
3843 struct attribute_group *ag)
3844 {
3845 int i;
3846
3847 for (i = 0; groups[i]; i++) {
3848 if (groups[i] == ag) {
3849 for (i++; groups[i]; i++)
3850 groups[i - 1] = groups[i];
3851 groups[i - 1] = NULL;
3852 break;
3853 }
3854 }
3855 }
3856
3857 static void
pmu_set_mapping(struct intel_uncore_type * type,struct attribute_group * ag,ssize_t (* show)(struct device *,struct device_attribute *,char *),int topology_type)3858 pmu_set_mapping(struct intel_uncore_type *type, struct attribute_group *ag,
3859 ssize_t (*show)(struct device*, struct device_attribute*, char*),
3860 int topology_type)
3861 {
3862 char buf[64];
3863 int ret;
3864 long die = -1;
3865 struct attribute **attrs = NULL;
3866 struct dev_ext_attribute *eas = NULL;
3867
3868 ret = pmu_alloc_topology(type, topology_type);
3869 if (ret < 0)
3870 goto clear_attr_update;
3871
3872 ret = type->get_topology(type);
3873 if (ret < 0)
3874 goto clear_topology;
3875
3876 /* One more for NULL. */
3877 attrs = kzalloc_objs(*attrs, (uncore_max_dies() + 1));
3878 if (!attrs)
3879 goto clear_topology;
3880
3881 eas = kzalloc_objs(*eas, uncore_max_dies());
3882 if (!eas)
3883 goto clear_attrs;
3884
3885 for (die = 0; die < uncore_max_dies(); die++) {
3886 snprintf(buf, sizeof(buf), "die%ld", die);
3887 sysfs_attr_init(&eas[die].attr.attr);
3888 eas[die].attr.attr.name = kstrdup(buf, GFP_KERNEL);
3889 if (!eas[die].attr.attr.name)
3890 goto err;
3891 eas[die].attr.attr.mode = 0444;
3892 eas[die].attr.show = show;
3893 eas[die].attr.store = NULL;
3894 eas[die].var = (void *)die;
3895 attrs[die] = &eas[die].attr.attr;
3896 }
3897 ag->attrs = attrs;
3898
3899 return;
3900 err:
3901 for (; die >= 0; die--)
3902 kfree(eas[die].attr.attr.name);
3903 kfree(eas);
3904 clear_attrs:
3905 kfree(attrs);
3906 clear_topology:
3907 pmu_free_topology(type);
3908 clear_attr_update:
3909 pmu_clear_mapping_attr(type->attr_update, ag);
3910 }
3911
3912 static void
pmu_cleanup_mapping(struct intel_uncore_type * type,struct attribute_group * ag)3913 pmu_cleanup_mapping(struct intel_uncore_type *type, struct attribute_group *ag)
3914 {
3915 struct attribute **attr = ag->attrs;
3916
3917 if (!attr)
3918 return;
3919
3920 for (; *attr; attr++)
3921 kfree((*attr)->name);
3922 kfree(attr_to_ext_attr(*ag->attrs));
3923 kfree(ag->attrs);
3924 ag->attrs = NULL;
3925 pmu_free_topology(type);
3926 }
3927
3928 static void
pmu_iio_set_mapping(struct intel_uncore_type * type,struct attribute_group * ag)3929 pmu_iio_set_mapping(struct intel_uncore_type *type, struct attribute_group *ag)
3930 {
3931 pmu_set_mapping(type, ag, skx_iio_mapping_show, IIO_TOPOLOGY_TYPE);
3932 }
3933
skx_iio_set_mapping(struct intel_uncore_type * type)3934 static void skx_iio_set_mapping(struct intel_uncore_type *type)
3935 {
3936 pmu_iio_set_mapping(type, &skx_iio_mapping_group);
3937 }
3938
skx_iio_cleanup_mapping(struct intel_uncore_type * type)3939 static void skx_iio_cleanup_mapping(struct intel_uncore_type *type)
3940 {
3941 pmu_cleanup_mapping(type, &skx_iio_mapping_group);
3942 }
3943
3944 static struct intel_uncore_type skx_uncore_iio = {
3945 .name = "iio",
3946 .num_counters = 4,
3947 .num_boxes = 6,
3948 .perf_ctr_bits = 48,
3949 .event_ctl = SKX_IIO0_MSR_PMON_CTL0,
3950 .perf_ctr = SKX_IIO0_MSR_PMON_CTR0,
3951 .event_mask = SKX_IIO_PMON_RAW_EVENT_MASK,
3952 .event_mask_ext = SKX_IIO_PMON_RAW_EVENT_MASK_EXT,
3953 .box_ctl = SKX_IIO0_MSR_PMON_BOX_CTL,
3954 .msr_offset = SKX_IIO_MSR_OFFSET,
3955 .constraints = skx_uncore_iio_constraints,
3956 .ops = &skx_uncore_iio_ops,
3957 .format_group = &skx_uncore_iio_format_group,
3958 .attr_update = skx_iio_attr_update,
3959 .get_topology = skx_iio_get_topology,
3960 .set_mapping = skx_iio_set_mapping,
3961 .cleanup_mapping = skx_iio_cleanup_mapping,
3962 };
3963
3964 enum perf_uncore_iio_freerunning_type_id {
3965 SKX_IIO_MSR_IOCLK = 0,
3966 SKX_IIO_MSR_BW = 1,
3967 SKX_IIO_MSR_UTIL = 2,
3968
3969 SKX_IIO_FREERUNNING_TYPE_MAX,
3970 };
3971
3972
3973 static struct freerunning_counters skx_iio_freerunning[] = {
3974 [SKX_IIO_MSR_IOCLK] = { 0xa45, 0x1, 0x20, 1, 36 },
3975 [SKX_IIO_MSR_BW] = { 0xb00, 0x1, 0x10, 8, 36 },
3976 [SKX_IIO_MSR_UTIL] = { 0xb08, 0x1, 0x10, 8, 36 },
3977 };
3978
3979 #define INTEL_UNCORE_FR_EVENT_DESC(name, umask, scl) \
3980 INTEL_UNCORE_EVENT_DESC(name, \
3981 "event=0xff,umask=" __stringify(umask)),\
3982 INTEL_UNCORE_EVENT_DESC(name.scale, __stringify(scl)), \
3983 INTEL_UNCORE_EVENT_DESC(name.unit, "MiB")
3984
3985 static struct uncore_event_desc skx_uncore_iio_freerunning_events[] = {
3986 /* Free-Running IO CLOCKS Counter */
3987 INTEL_UNCORE_EVENT_DESC(ioclk, "event=0xff,umask=0x10"),
3988 /* Free-Running IIO BANDWIDTH Counters */
3989 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port0, 0x20, 3.814697266e-6),
3990 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port1, 0x21, 3.814697266e-6),
3991 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port2, 0x22, 3.814697266e-6),
3992 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port3, 0x23, 3.814697266e-6),
3993 INTEL_UNCORE_FR_EVENT_DESC(bw_out_port0, 0x24, 3.814697266e-6),
3994 INTEL_UNCORE_FR_EVENT_DESC(bw_out_port1, 0x25, 3.814697266e-6),
3995 INTEL_UNCORE_FR_EVENT_DESC(bw_out_port2, 0x26, 3.814697266e-6),
3996 INTEL_UNCORE_FR_EVENT_DESC(bw_out_port3, 0x27, 3.814697266e-6),
3997 /* Free-running IIO UTILIZATION Counters */
3998 INTEL_UNCORE_EVENT_DESC(util_in_port0, "event=0xff,umask=0x30"),
3999 INTEL_UNCORE_EVENT_DESC(util_out_port0, "event=0xff,umask=0x31"),
4000 INTEL_UNCORE_EVENT_DESC(util_in_port1, "event=0xff,umask=0x32"),
4001 INTEL_UNCORE_EVENT_DESC(util_out_port1, "event=0xff,umask=0x33"),
4002 INTEL_UNCORE_EVENT_DESC(util_in_port2, "event=0xff,umask=0x34"),
4003 INTEL_UNCORE_EVENT_DESC(util_out_port2, "event=0xff,umask=0x35"),
4004 INTEL_UNCORE_EVENT_DESC(util_in_port3, "event=0xff,umask=0x36"),
4005 INTEL_UNCORE_EVENT_DESC(util_out_port3, "event=0xff,umask=0x37"),
4006 { /* end: all zeroes */ },
4007 };
4008
4009 static struct intel_uncore_ops skx_uncore_iio_freerunning_ops = {
4010 .read_counter = uncore_msr_read_counter,
4011 .hw_config = uncore_freerunning_hw_config,
4012 };
4013
4014 static struct attribute *skx_uncore_iio_freerunning_formats_attr[] = {
4015 &format_attr_event.attr,
4016 &format_attr_umask.attr,
4017 NULL,
4018 };
4019
4020 static const struct attribute_group skx_uncore_iio_freerunning_format_group = {
4021 .name = "format",
4022 .attrs = skx_uncore_iio_freerunning_formats_attr,
4023 };
4024
4025 static struct intel_uncore_type skx_uncore_iio_free_running = {
4026 .name = "iio_free_running",
4027 .num_counters = 17,
4028 .num_boxes = 6,
4029 .num_freerunning_types = SKX_IIO_FREERUNNING_TYPE_MAX,
4030 .freerunning = skx_iio_freerunning,
4031 .ops = &skx_uncore_iio_freerunning_ops,
4032 .event_descs = skx_uncore_iio_freerunning_events,
4033 .format_group = &skx_uncore_iio_freerunning_format_group,
4034 };
4035
4036 static struct attribute *skx_uncore_formats_attr[] = {
4037 &format_attr_event.attr,
4038 &format_attr_umask.attr,
4039 &format_attr_edge.attr,
4040 &format_attr_inv.attr,
4041 &format_attr_thresh8.attr,
4042 NULL,
4043 };
4044
4045 static const struct attribute_group skx_uncore_format_group = {
4046 .name = "format",
4047 .attrs = skx_uncore_formats_attr,
4048 };
4049
4050 static struct intel_uncore_type skx_uncore_irp = {
4051 .name = "irp",
4052 .num_counters = 2,
4053 .num_boxes = 6,
4054 .perf_ctr_bits = 48,
4055 .event_ctl = SKX_IRP0_MSR_PMON_CTL0,
4056 .perf_ctr = SKX_IRP0_MSR_PMON_CTR0,
4057 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
4058 .box_ctl = SKX_IRP0_MSR_PMON_BOX_CTL,
4059 .msr_offset = SKX_IRP_MSR_OFFSET,
4060 .ops = &skx_uncore_iio_ops,
4061 .format_group = &skx_uncore_format_group,
4062 };
4063
4064 static struct attribute *skx_uncore_pcu_formats_attr[] = {
4065 &format_attr_event.attr,
4066 &format_attr_umask.attr,
4067 &format_attr_edge.attr,
4068 &format_attr_inv.attr,
4069 &format_attr_thresh8.attr,
4070 &format_attr_occ_invert.attr,
4071 &format_attr_occ_edge_det.attr,
4072 &format_attr_filter_band0.attr,
4073 &format_attr_filter_band1.attr,
4074 &format_attr_filter_band2.attr,
4075 &format_attr_filter_band3.attr,
4076 NULL,
4077 };
4078
4079 static struct attribute_group skx_uncore_pcu_format_group = {
4080 .name = "format",
4081 .attrs = skx_uncore_pcu_formats_attr,
4082 };
4083
4084 static struct intel_uncore_ops skx_uncore_pcu_ops = {
4085 IVBEP_UNCORE_MSR_OPS_COMMON_INIT(),
4086 .hw_config = hswep_pcu_hw_config,
4087 .get_constraint = snbep_pcu_get_constraint,
4088 .put_constraint = snbep_pcu_put_constraint,
4089 };
4090
4091 static struct intel_uncore_type skx_uncore_pcu = {
4092 .name = "pcu",
4093 .num_counters = 4,
4094 .num_boxes = 1,
4095 .perf_ctr_bits = 48,
4096 .perf_ctr = HSWEP_PCU_MSR_PMON_CTR0,
4097 .event_ctl = HSWEP_PCU_MSR_PMON_CTL0,
4098 .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
4099 .box_ctl = HSWEP_PCU_MSR_PMON_BOX_CTL,
4100 .num_shared_regs = 1,
4101 .ops = &skx_uncore_pcu_ops,
4102 .format_group = &skx_uncore_pcu_format_group,
4103 };
4104
4105 static struct intel_uncore_type *skx_msr_uncores[] = {
4106 &skx_uncore_ubox,
4107 &skx_uncore_chabox,
4108 &skx_uncore_iio,
4109 &skx_uncore_iio_free_running,
4110 &skx_uncore_irp,
4111 &skx_uncore_pcu,
4112 NULL,
4113 };
4114
4115 /*
4116 * To determine the number of CHAs, it should read bits 27:0 in the CAPID6
4117 * register which located at Device 30, Function 3, Offset 0x9C. PCI ID 0x2083.
4118 */
4119 #define SKX_CAPID6 0x9c
4120 #define SKX_CHA_BIT_MASK GENMASK(27, 0)
4121
skx_count_chabox(void)4122 static int skx_count_chabox(void)
4123 {
4124 struct pci_dev *dev = NULL;
4125 u32 val = 0;
4126
4127 dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2083, dev);
4128 if (!dev)
4129 goto out;
4130
4131 pci_read_config_dword(dev, SKX_CAPID6, &val);
4132 val &= SKX_CHA_BIT_MASK;
4133 out:
4134 pci_dev_put(dev);
4135 return hweight32(val);
4136 }
4137
skx_uncore_cpu_init(void)4138 void skx_uncore_cpu_init(void)
4139 {
4140 skx_uncore_chabox.num_boxes = skx_count_chabox();
4141 uncore_msr_uncores = skx_msr_uncores;
4142 }
4143
4144 static struct intel_uncore_type skx_uncore_imc = {
4145 .name = "imc",
4146 .num_counters = 4,
4147 .num_boxes = 6,
4148 .perf_ctr_bits = 48,
4149 .fixed_ctr_bits = 48,
4150 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
4151 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
4152 .event_descs = hswep_uncore_imc_events,
4153 .perf_ctr = SNBEP_PCI_PMON_CTR0,
4154 .event_ctl = SNBEP_PCI_PMON_CTL0,
4155 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
4156 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
4157 .ops = &ivbep_uncore_pci_ops,
4158 .format_group = &skx_uncore_format_group,
4159 };
4160
4161 static struct attribute *skx_upi_uncore_formats_attr[] = {
4162 &format_attr_event.attr,
4163 &format_attr_umask_ext.attr,
4164 &format_attr_edge.attr,
4165 &format_attr_inv.attr,
4166 &format_attr_thresh8.attr,
4167 NULL,
4168 };
4169
4170 static const struct attribute_group skx_upi_uncore_format_group = {
4171 .name = "format",
4172 .attrs = skx_upi_uncore_formats_attr,
4173 };
4174
skx_upi_uncore_pci_init_box(struct intel_uncore_box * box)4175 static int skx_upi_uncore_pci_init_box(struct intel_uncore_box *box)
4176 {
4177 struct pci_dev *pdev = box->pci_dev;
4178
4179 __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags);
4180 return pci_write_config_dword(pdev, SKX_UPI_PCI_PMON_BOX_CTL,
4181 IVBEP_PMON_BOX_CTL_INT);
4182 }
4183
4184 static struct intel_uncore_ops skx_upi_uncore_pci_ops = {
4185 .init_box = skx_upi_uncore_pci_init_box,
4186 .disable_box = snbep_uncore_pci_disable_box,
4187 .enable_box = snbep_uncore_pci_enable_box,
4188 .disable_event = snbep_uncore_pci_disable_event,
4189 .enable_event = snbep_uncore_pci_enable_event,
4190 .read_counter = snbep_uncore_pci_read_counter,
4191 };
4192
4193 static umode_t
skx_upi_mapping_visible(struct kobject * kobj,struct attribute * attr,int die)4194 skx_upi_mapping_visible(struct kobject *kobj, struct attribute *attr, int die)
4195 {
4196 struct intel_uncore_pmu *pmu = dev_to_uncore_pmu(kobj_to_dev(kobj));
4197
4198 return pmu->type->topology[die][pmu->pmu_idx].upi->enabled ? attr->mode : 0;
4199 }
4200
skx_upi_mapping_show(struct device * dev,struct device_attribute * attr,char * buf)4201 static ssize_t skx_upi_mapping_show(struct device *dev,
4202 struct device_attribute *attr, char *buf)
4203 {
4204 struct intel_uncore_pmu *pmu = dev_to_uncore_pmu(dev);
4205 struct dev_ext_attribute *ea = to_dev_ext_attribute(attr);
4206 long die = (long)ea->var;
4207 struct uncore_upi_topology *upi = pmu->type->topology[die][pmu->pmu_idx].upi;
4208
4209 return sysfs_emit(buf, "upi_%d,die_%d\n", upi->pmu_idx_to, upi->die_to);
4210 }
4211
4212 #define SKX_UPI_REG_DID 0x2058
4213 #define SKX_UPI_REGS_ADDR_DEVICE_LINK0 0x0e
4214 #define SKX_UPI_REGS_ADDR_FUNCTION 0x00
4215
4216 /*
4217 * UPI Link Parameter 0
4218 * | Bit | Default | Description
4219 * | 19:16 | 0h | base_nodeid - The NodeID of the sending socket.
4220 * | 12:8 | 00h | sending_port - The processor die port number of the sending port.
4221 */
4222 #define SKX_KTILP0_OFFSET 0x94
4223
4224 /*
4225 * UPI Pcode Status. This register is used by PCode to store the link training status.
4226 * | Bit | Default | Description
4227 * | 4 | 0h | ll_status_valid — Bit indicates the valid training status
4228 * logged from PCode to the BIOS.
4229 */
4230 #define SKX_KTIPCSTS_OFFSET 0x120
4231
upi_fill_topology(struct pci_dev * dev,struct intel_uncore_topology * tp,int pmu_idx)4232 static int upi_fill_topology(struct pci_dev *dev, struct intel_uncore_topology *tp,
4233 int pmu_idx)
4234 {
4235 int ret;
4236 u32 upi_conf;
4237 struct uncore_upi_topology *upi = tp->upi;
4238
4239 tp->pmu_idx = pmu_idx;
4240 ret = pci_read_config_dword(dev, SKX_KTIPCSTS_OFFSET, &upi_conf);
4241 if (ret) {
4242 ret = pcibios_err_to_errno(ret);
4243 goto err;
4244 }
4245 upi->enabled = (upi_conf >> 4) & 1;
4246 if (upi->enabled) {
4247 ret = pci_read_config_dword(dev, SKX_KTILP0_OFFSET,
4248 &upi_conf);
4249 if (ret) {
4250 ret = pcibios_err_to_errno(ret);
4251 goto err;
4252 }
4253 upi->die_to = (upi_conf >> 16) & 0xf;
4254 upi->pmu_idx_to = (upi_conf >> 8) & 0x1f;
4255 }
4256 err:
4257 return ret;
4258 }
4259
skx_upi_topology_cb(struct intel_uncore_type * type,int segment,int die,u64 cpu_bus_msr)4260 static int skx_upi_topology_cb(struct intel_uncore_type *type, int segment,
4261 int die, u64 cpu_bus_msr)
4262 {
4263 int idx, ret = 0;
4264 struct intel_uncore_topology *upi;
4265 unsigned int devfn;
4266 struct pci_dev *dev = NULL;
4267 u8 bus = cpu_bus_msr >> (3 * BUS_NUM_STRIDE);
4268
4269 for (idx = 0; idx < type->num_boxes; idx++) {
4270 upi = &type->topology[die][idx];
4271 devfn = PCI_DEVFN(SKX_UPI_REGS_ADDR_DEVICE_LINK0 + idx,
4272 SKX_UPI_REGS_ADDR_FUNCTION);
4273 dev = pci_get_domain_bus_and_slot(segment, bus, devfn);
4274 if (dev) {
4275 ret = upi_fill_topology(dev, upi, idx);
4276 pci_dev_put(dev);
4277 if (ret)
4278 break;
4279 }
4280 }
4281
4282 return ret;
4283 }
4284
skx_upi_get_topology(struct intel_uncore_type * type)4285 static int skx_upi_get_topology(struct intel_uncore_type *type)
4286 {
4287 /* CPX case is not supported */
4288 if (boot_cpu_data.x86_stepping == 11)
4289 return -EPERM;
4290
4291 return skx_pmu_get_topology(type, skx_upi_topology_cb);
4292 }
4293
4294 static struct attribute_group skx_upi_mapping_group = {
4295 .is_visible = skx_upi_mapping_visible,
4296 };
4297
4298 static const struct attribute_group *skx_upi_attr_update[] = {
4299 &skx_upi_mapping_group,
4300 NULL
4301 };
4302
4303 static void
pmu_upi_set_mapping(struct intel_uncore_type * type,struct attribute_group * ag)4304 pmu_upi_set_mapping(struct intel_uncore_type *type, struct attribute_group *ag)
4305 {
4306 pmu_set_mapping(type, ag, skx_upi_mapping_show, UPI_TOPOLOGY_TYPE);
4307 }
4308
skx_upi_set_mapping(struct intel_uncore_type * type)4309 static void skx_upi_set_mapping(struct intel_uncore_type *type)
4310 {
4311 pmu_upi_set_mapping(type, &skx_upi_mapping_group);
4312 }
4313
skx_upi_cleanup_mapping(struct intel_uncore_type * type)4314 static void skx_upi_cleanup_mapping(struct intel_uncore_type *type)
4315 {
4316 pmu_cleanup_mapping(type, &skx_upi_mapping_group);
4317 }
4318
4319 static struct intel_uncore_type skx_uncore_upi = {
4320 .name = "upi",
4321 .num_counters = 4,
4322 .num_boxes = 3,
4323 .perf_ctr_bits = 48,
4324 .perf_ctr = SKX_UPI_PCI_PMON_CTR0,
4325 .event_ctl = SKX_UPI_PCI_PMON_CTL0,
4326 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
4327 .event_mask_ext = SKX_UPI_CTL_UMASK_EXT,
4328 .box_ctl = SKX_UPI_PCI_PMON_BOX_CTL,
4329 .ops = &skx_upi_uncore_pci_ops,
4330 .format_group = &skx_upi_uncore_format_group,
4331 .attr_update = skx_upi_attr_update,
4332 .get_topology = skx_upi_get_topology,
4333 .set_mapping = skx_upi_set_mapping,
4334 .cleanup_mapping = skx_upi_cleanup_mapping,
4335 };
4336
skx_m2m_uncore_pci_init_box(struct intel_uncore_box * box)4337 static int skx_m2m_uncore_pci_init_box(struct intel_uncore_box *box)
4338 {
4339 struct pci_dev *pdev = box->pci_dev;
4340
4341 __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags);
4342 return pci_write_config_dword(pdev, SKX_M2M_PCI_PMON_BOX_CTL,
4343 IVBEP_PMON_BOX_CTL_INT);
4344 }
4345
4346 static struct intel_uncore_ops skx_m2m_uncore_pci_ops = {
4347 .init_box = skx_m2m_uncore_pci_init_box,
4348 .disable_box = snbep_uncore_pci_disable_box,
4349 .enable_box = snbep_uncore_pci_enable_box,
4350 .disable_event = snbep_uncore_pci_disable_event,
4351 .enable_event = snbep_uncore_pci_enable_event,
4352 .read_counter = snbep_uncore_pci_read_counter,
4353 };
4354
4355 static struct intel_uncore_type skx_uncore_m2m = {
4356 .name = "m2m",
4357 .num_counters = 4,
4358 .num_boxes = 2,
4359 .perf_ctr_bits = 48,
4360 .perf_ctr = SKX_M2M_PCI_PMON_CTR0,
4361 .event_ctl = SKX_M2M_PCI_PMON_CTL0,
4362 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
4363 .box_ctl = SKX_M2M_PCI_PMON_BOX_CTL,
4364 .ops = &skx_m2m_uncore_pci_ops,
4365 .format_group = &skx_uncore_format_group,
4366 };
4367
4368 static struct event_constraint skx_uncore_m2pcie_constraints[] = {
4369 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
4370 EVENT_CONSTRAINT_END
4371 };
4372
4373 static struct intel_uncore_type skx_uncore_m2pcie = {
4374 .name = "m2pcie",
4375 .num_counters = 4,
4376 .num_boxes = 4,
4377 .perf_ctr_bits = 48,
4378 .constraints = skx_uncore_m2pcie_constraints,
4379 .perf_ctr = SNBEP_PCI_PMON_CTR0,
4380 .event_ctl = SNBEP_PCI_PMON_CTL0,
4381 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
4382 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
4383 .ops = &ivbep_uncore_pci_ops,
4384 .format_group = &skx_uncore_format_group,
4385 };
4386
4387 static struct event_constraint skx_uncore_m3upi_constraints[] = {
4388 UNCORE_EVENT_CONSTRAINT_RANGE(0x1d, 0x1e, 0x1),
4389 UNCORE_EVENT_CONSTRAINT(0x40, 0x7),
4390 UNCORE_EVENT_CONSTRAINT_RANGE(0x4e, 0x52, 0x7),
4391 EVENT_CONSTRAINT_END
4392 };
4393
4394 static struct intel_uncore_type skx_uncore_m3upi = {
4395 .name = "m3upi",
4396 .num_counters = 3,
4397 .num_boxes = 3,
4398 .perf_ctr_bits = 48,
4399 .constraints = skx_uncore_m3upi_constraints,
4400 .perf_ctr = SNBEP_PCI_PMON_CTR0,
4401 .event_ctl = SNBEP_PCI_PMON_CTL0,
4402 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
4403 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
4404 .ops = &ivbep_uncore_pci_ops,
4405 .format_group = &skx_uncore_format_group,
4406 };
4407
4408 enum {
4409 SKX_PCI_UNCORE_IMC,
4410 SKX_PCI_UNCORE_M2M,
4411 SKX_PCI_UNCORE_UPI,
4412 SKX_PCI_UNCORE_M2PCIE,
4413 SKX_PCI_UNCORE_M3UPI,
4414 };
4415
4416 static struct intel_uncore_type *skx_pci_uncores[] = {
4417 [SKX_PCI_UNCORE_IMC] = &skx_uncore_imc,
4418 [SKX_PCI_UNCORE_M2M] = &skx_uncore_m2m,
4419 [SKX_PCI_UNCORE_UPI] = &skx_uncore_upi,
4420 [SKX_PCI_UNCORE_M2PCIE] = &skx_uncore_m2pcie,
4421 [SKX_PCI_UNCORE_M3UPI] = &skx_uncore_m3upi,
4422 NULL,
4423 };
4424
4425 static const struct pci_device_id skx_uncore_pci_ids[] = {
4426 { /* MC0 Channel 0 */
4427 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2042),
4428 .driver_data = UNCORE_PCI_DEV_FULL_DATA(10, 2, SKX_PCI_UNCORE_IMC, 0),
4429 },
4430 { /* MC0 Channel 1 */
4431 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2046),
4432 .driver_data = UNCORE_PCI_DEV_FULL_DATA(10, 6, SKX_PCI_UNCORE_IMC, 1),
4433 },
4434 { /* MC0 Channel 2 */
4435 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204a),
4436 .driver_data = UNCORE_PCI_DEV_FULL_DATA(11, 2, SKX_PCI_UNCORE_IMC, 2),
4437 },
4438 { /* MC1 Channel 0 */
4439 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2042),
4440 .driver_data = UNCORE_PCI_DEV_FULL_DATA(12, 2, SKX_PCI_UNCORE_IMC, 3),
4441 },
4442 { /* MC1 Channel 1 */
4443 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2046),
4444 .driver_data = UNCORE_PCI_DEV_FULL_DATA(12, 6, SKX_PCI_UNCORE_IMC, 4),
4445 },
4446 { /* MC1 Channel 2 */
4447 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204a),
4448 .driver_data = UNCORE_PCI_DEV_FULL_DATA(13, 2, SKX_PCI_UNCORE_IMC, 5),
4449 },
4450 { /* M2M0 */
4451 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2066),
4452 .driver_data = UNCORE_PCI_DEV_FULL_DATA(8, 0, SKX_PCI_UNCORE_M2M, 0),
4453 },
4454 { /* M2M1 */
4455 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2066),
4456 .driver_data = UNCORE_PCI_DEV_FULL_DATA(9, 0, SKX_PCI_UNCORE_M2M, 1),
4457 },
4458 { /* UPI0 Link 0 */
4459 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2058),
4460 .driver_data = UNCORE_PCI_DEV_FULL_DATA(14, 0, SKX_PCI_UNCORE_UPI, 0),
4461 },
4462 { /* UPI0 Link 1 */
4463 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2058),
4464 .driver_data = UNCORE_PCI_DEV_FULL_DATA(15, 0, SKX_PCI_UNCORE_UPI, 1),
4465 },
4466 { /* UPI1 Link 2 */
4467 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2058),
4468 .driver_data = UNCORE_PCI_DEV_FULL_DATA(16, 0, SKX_PCI_UNCORE_UPI, 2),
4469 },
4470 { /* M2PCIe 0 */
4471 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088),
4472 .driver_data = UNCORE_PCI_DEV_FULL_DATA(21, 1, SKX_PCI_UNCORE_M2PCIE, 0),
4473 },
4474 { /* M2PCIe 1 */
4475 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088),
4476 .driver_data = UNCORE_PCI_DEV_FULL_DATA(22, 1, SKX_PCI_UNCORE_M2PCIE, 1),
4477 },
4478 { /* M2PCIe 2 */
4479 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088),
4480 .driver_data = UNCORE_PCI_DEV_FULL_DATA(23, 1, SKX_PCI_UNCORE_M2PCIE, 2),
4481 },
4482 { /* M2PCIe 3 */
4483 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088),
4484 .driver_data = UNCORE_PCI_DEV_FULL_DATA(21, 5, SKX_PCI_UNCORE_M2PCIE, 3),
4485 },
4486 { /* M3UPI0 Link 0 */
4487 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204D),
4488 .driver_data = UNCORE_PCI_DEV_FULL_DATA(18, 1, SKX_PCI_UNCORE_M3UPI, 0),
4489 },
4490 { /* M3UPI0 Link 1 */
4491 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204E),
4492 .driver_data = UNCORE_PCI_DEV_FULL_DATA(18, 2, SKX_PCI_UNCORE_M3UPI, 1),
4493 },
4494 { /* M3UPI1 Link 2 */
4495 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204D),
4496 .driver_data = UNCORE_PCI_DEV_FULL_DATA(18, 5, SKX_PCI_UNCORE_M3UPI, 2),
4497 },
4498 { /* end: all zeroes */ }
4499 };
4500
4501
4502 static struct pci_driver skx_uncore_pci_driver = {
4503 .name = "skx_uncore",
4504 .id_table = skx_uncore_pci_ids,
4505 };
4506
skx_uncore_pci_init(void)4507 int skx_uncore_pci_init(void)
4508 {
4509 /* need to double check pci address */
4510 int ret = snbep_pci2phy_map_init(0x2014, SKX_CPUNODEID, SKX_GIDNIDMAP, false);
4511
4512 if (ret)
4513 return ret;
4514
4515 uncore_pci_uncores = skx_pci_uncores;
4516 uncore_pci_driver = &skx_uncore_pci_driver;
4517 return 0;
4518 }
4519
4520 /* end of SKX uncore support */
4521
4522 /* SNR uncore support */
4523
4524 static struct intel_uncore_type snr_uncore_ubox = {
4525 .name = "ubox",
4526 .num_counters = 2,
4527 .num_boxes = 1,
4528 .perf_ctr_bits = 48,
4529 .fixed_ctr_bits = 48,
4530 .perf_ctr = SNR_U_MSR_PMON_CTR0,
4531 .event_ctl = SNR_U_MSR_PMON_CTL0,
4532 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
4533 .fixed_ctr = SNR_U_MSR_PMON_UCLK_FIXED_CTR,
4534 .fixed_ctl = SNR_U_MSR_PMON_UCLK_FIXED_CTL,
4535 .ops = &ivbep_uncore_msr_ops,
4536 .format_group = &ivbep_uncore_format_group,
4537 };
4538
4539 static struct attribute *snr_uncore_cha_formats_attr[] = {
4540 &format_attr_event.attr,
4541 &format_attr_umask_ext2.attr,
4542 &format_attr_edge.attr,
4543 &format_attr_tid_en.attr,
4544 &format_attr_inv.attr,
4545 &format_attr_thresh8.attr,
4546 &format_attr_filter_tid5.attr,
4547 NULL,
4548 };
4549 static const struct attribute_group snr_uncore_chabox_format_group = {
4550 .name = "format",
4551 .attrs = snr_uncore_cha_formats_attr,
4552 };
4553
snr_cha_hw_config(struct intel_uncore_box * box,struct perf_event * event)4554 static int snr_cha_hw_config(struct intel_uncore_box *box, struct perf_event *event)
4555 {
4556 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
4557
4558 reg1->reg = SNR_C0_MSR_PMON_BOX_FILTER0 +
4559 box->pmu->type->msr_offset * box->pmu->pmu_idx;
4560 reg1->config = event->attr.config1 & SKX_CHA_MSR_PMON_BOX_FILTER_TID;
4561 reg1->idx = 0;
4562
4563 return 0;
4564 }
4565
snr_cha_enable_event(struct intel_uncore_box * box,struct perf_event * event)4566 static void snr_cha_enable_event(struct intel_uncore_box *box,
4567 struct perf_event *event)
4568 {
4569 struct hw_perf_event *hwc = &event->hw;
4570 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
4571
4572 if (reg1->idx != EXTRA_REG_NONE)
4573 wrmsrq(reg1->reg, reg1->config);
4574
4575 wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
4576 }
4577
4578 static struct intel_uncore_ops snr_uncore_chabox_ops = {
4579 .init_box = ivbep_uncore_msr_init_box,
4580 .disable_box = snbep_uncore_msr_disable_box,
4581 .enable_box = snbep_uncore_msr_enable_box,
4582 .disable_event = snbep_uncore_msr_disable_event,
4583 .enable_event = snr_cha_enable_event,
4584 .read_counter = uncore_msr_read_counter,
4585 .hw_config = snr_cha_hw_config,
4586 };
4587
4588 static struct intel_uncore_type snr_uncore_chabox = {
4589 .name = "cha",
4590 .num_counters = 4,
4591 .num_boxes = 6,
4592 .perf_ctr_bits = 48,
4593 .event_ctl = SNR_CHA_MSR_PMON_CTL0,
4594 .perf_ctr = SNR_CHA_MSR_PMON_CTR0,
4595 .box_ctl = SNR_CHA_MSR_PMON_BOX_CTL,
4596 .msr_offset = HSWEP_CBO_MSR_OFFSET,
4597 .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK,
4598 .event_mask_ext = SNR_CHA_RAW_EVENT_MASK_EXT,
4599 .ops = &snr_uncore_chabox_ops,
4600 .format_group = &snr_uncore_chabox_format_group,
4601 };
4602
4603 static struct attribute *snr_uncore_iio_formats_attr[] = {
4604 &format_attr_event.attr,
4605 &format_attr_umask.attr,
4606 &format_attr_edge.attr,
4607 &format_attr_inv.attr,
4608 &format_attr_thresh9.attr,
4609 &format_attr_ch_mask2.attr,
4610 &format_attr_fc_mask2.attr,
4611 NULL,
4612 };
4613
4614 static const struct attribute_group snr_uncore_iio_format_group = {
4615 .name = "format",
4616 .attrs = snr_uncore_iio_formats_attr,
4617 };
4618
4619 static umode_t
snr_iio_mapping_visible(struct kobject * kobj,struct attribute * attr,int die)4620 snr_iio_mapping_visible(struct kobject *kobj, struct attribute *attr, int die)
4621 {
4622 /* Root bus 0x00 is valid only for pmu_idx = 1. */
4623 return pmu_iio_mapping_visible(kobj, attr, die, 1);
4624 }
4625
4626 static struct attribute_group snr_iio_mapping_group = {
4627 .is_visible = snr_iio_mapping_visible,
4628 };
4629
4630 static const struct attribute_group *snr_iio_attr_update[] = {
4631 &snr_iio_mapping_group,
4632 NULL,
4633 };
4634
sad_cfg_iio_topology(struct intel_uncore_type * type,u8 * sad_pmon_mapping)4635 static int sad_cfg_iio_topology(struct intel_uncore_type *type, u8 *sad_pmon_mapping)
4636 {
4637 u32 sad_cfg;
4638 int die, stack_id, ret = -EPERM;
4639 struct pci_dev *dev = NULL;
4640
4641 while ((dev = pci_get_device(PCI_VENDOR_ID_INTEL, SNR_ICX_MESH2IIO_MMAP_DID, dev))) {
4642 ret = pci_read_config_dword(dev, SNR_ICX_SAD_CONTROL_CFG, &sad_cfg);
4643 if (ret) {
4644 ret = pcibios_err_to_errno(ret);
4645 break;
4646 }
4647
4648 die = uncore_pcibus_to_dieid(dev->bus);
4649 stack_id = SAD_CONTROL_STACK_ID(sad_cfg);
4650 if (die < 0 || stack_id >= type->num_boxes) {
4651 ret = -EPERM;
4652 break;
4653 }
4654
4655 /* Convert stack id from SAD_CONTROL to PMON notation. */
4656 stack_id = sad_pmon_mapping[stack_id];
4657
4658 type->topology[die][stack_id].iio->segment = pci_domain_nr(dev->bus);
4659 type->topology[die][stack_id].pmu_idx = stack_id;
4660 type->topology[die][stack_id].iio->pci_bus_no = dev->bus->number;
4661 }
4662
4663 pci_dev_put(dev);
4664
4665 return ret;
4666 }
4667
4668 /*
4669 * SNR has a static mapping of stack IDs from SAD_CONTROL_CFG notation to PMON
4670 */
4671 enum {
4672 SNR_QAT_PMON_ID,
4673 SNR_CBDMA_DMI_PMON_ID,
4674 SNR_NIS_PMON_ID,
4675 SNR_DLB_PMON_ID,
4676 SNR_PCIE_GEN3_PMON_ID
4677 };
4678
4679 static u8 snr_sad_pmon_mapping[] = {
4680 SNR_CBDMA_DMI_PMON_ID,
4681 SNR_PCIE_GEN3_PMON_ID,
4682 SNR_DLB_PMON_ID,
4683 SNR_NIS_PMON_ID,
4684 SNR_QAT_PMON_ID
4685 };
4686
snr_iio_get_topology(struct intel_uncore_type * type)4687 static int snr_iio_get_topology(struct intel_uncore_type *type)
4688 {
4689 return sad_cfg_iio_topology(type, snr_sad_pmon_mapping);
4690 }
4691
snr_iio_set_mapping(struct intel_uncore_type * type)4692 static void snr_iio_set_mapping(struct intel_uncore_type *type)
4693 {
4694 pmu_iio_set_mapping(type, &snr_iio_mapping_group);
4695 }
4696
snr_iio_cleanup_mapping(struct intel_uncore_type * type)4697 static void snr_iio_cleanup_mapping(struct intel_uncore_type *type)
4698 {
4699 pmu_cleanup_mapping(type, &snr_iio_mapping_group);
4700 }
4701
4702 static struct event_constraint snr_uncore_iio_constraints[] = {
4703 UNCORE_EVENT_CONSTRAINT(0x83, 0x3),
4704 UNCORE_EVENT_CONSTRAINT(0xc0, 0xc),
4705 UNCORE_EVENT_CONSTRAINT(0xd5, 0xc),
4706 EVENT_CONSTRAINT_END
4707 };
4708
4709 static struct intel_uncore_type snr_uncore_iio = {
4710 .name = "iio",
4711 .num_counters = 4,
4712 .num_boxes = 5,
4713 .perf_ctr_bits = 48,
4714 .event_ctl = SNR_IIO_MSR_PMON_CTL0,
4715 .perf_ctr = SNR_IIO_MSR_PMON_CTR0,
4716 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
4717 .event_mask_ext = SNR_IIO_PMON_RAW_EVENT_MASK_EXT,
4718 .box_ctl = SNR_IIO_MSR_PMON_BOX_CTL,
4719 .msr_offset = SNR_IIO_MSR_OFFSET,
4720 .constraints = snr_uncore_iio_constraints,
4721 .ops = &ivbep_uncore_msr_ops,
4722 .format_group = &snr_uncore_iio_format_group,
4723 .attr_update = snr_iio_attr_update,
4724 .get_topology = snr_iio_get_topology,
4725 .set_mapping = snr_iio_set_mapping,
4726 .cleanup_mapping = snr_iio_cleanup_mapping,
4727 };
4728
4729 static struct intel_uncore_type snr_uncore_irp = {
4730 .name = "irp",
4731 .num_counters = 2,
4732 .num_boxes = 5,
4733 .perf_ctr_bits = 48,
4734 .event_ctl = SNR_IRP0_MSR_PMON_CTL0,
4735 .perf_ctr = SNR_IRP0_MSR_PMON_CTR0,
4736 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
4737 .box_ctl = SNR_IRP0_MSR_PMON_BOX_CTL,
4738 .msr_offset = SNR_IRP_MSR_OFFSET,
4739 .ops = &ivbep_uncore_msr_ops,
4740 .format_group = &ivbep_uncore_format_group,
4741 };
4742
4743 static struct intel_uncore_type snr_uncore_m2pcie = {
4744 .name = "m2pcie",
4745 .num_counters = 4,
4746 .num_boxes = 5,
4747 .perf_ctr_bits = 48,
4748 .event_ctl = SNR_M2PCIE_MSR_PMON_CTL0,
4749 .perf_ctr = SNR_M2PCIE_MSR_PMON_CTR0,
4750 .box_ctl = SNR_M2PCIE_MSR_PMON_BOX_CTL,
4751 .msr_offset = SNR_M2PCIE_MSR_OFFSET,
4752 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
4753 .ops = &ivbep_uncore_msr_ops,
4754 .format_group = &ivbep_uncore_format_group,
4755 };
4756
snr_pcu_hw_config(struct intel_uncore_box * box,struct perf_event * event)4757 static int snr_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event)
4758 {
4759 struct hw_perf_event *hwc = &event->hw;
4760 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
4761 int ev_sel = hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK;
4762
4763 if (ev_sel >= 0xb && ev_sel <= 0xe) {
4764 reg1->reg = SNR_PCU_MSR_PMON_BOX_FILTER;
4765 reg1->idx = ev_sel - 0xb;
4766 reg1->config = event->attr.config1 & (0xff << reg1->idx);
4767 }
4768 return 0;
4769 }
4770
4771 static struct intel_uncore_ops snr_uncore_pcu_ops = {
4772 IVBEP_UNCORE_MSR_OPS_COMMON_INIT(),
4773 .hw_config = snr_pcu_hw_config,
4774 .get_constraint = snbep_pcu_get_constraint,
4775 .put_constraint = snbep_pcu_put_constraint,
4776 };
4777
4778 static struct intel_uncore_type snr_uncore_pcu = {
4779 .name = "pcu",
4780 .num_counters = 4,
4781 .num_boxes = 1,
4782 .perf_ctr_bits = 48,
4783 .perf_ctr = SNR_PCU_MSR_PMON_CTR0,
4784 .event_ctl = SNR_PCU_MSR_PMON_CTL0,
4785 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
4786 .box_ctl = SNR_PCU_MSR_PMON_BOX_CTL,
4787 .num_shared_regs = 1,
4788 .ops = &snr_uncore_pcu_ops,
4789 .format_group = &skx_uncore_pcu_format_group,
4790 };
4791
4792 enum perf_uncore_snr_iio_freerunning_type_id {
4793 SNR_IIO_MSR_IOCLK,
4794 SNR_IIO_MSR_BW_IN,
4795
4796 SNR_IIO_FREERUNNING_TYPE_MAX,
4797 };
4798
4799 static struct freerunning_counters snr_iio_freerunning[] = {
4800 [SNR_IIO_MSR_IOCLK] = { 0x1eac, 0x1, 0x10, 1, 48 },
4801 [SNR_IIO_MSR_BW_IN] = { 0x1f00, 0x1, 0x10, 8, 48 },
4802 };
4803
4804 static struct uncore_event_desc snr_uncore_iio_freerunning_events[] = {
4805 /* Free-Running IIO CLOCKS Counter */
4806 INTEL_UNCORE_EVENT_DESC(ioclk, "event=0xff,umask=0x10"),
4807 /* Free-Running IIO BANDWIDTH IN Counters */
4808 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port0, 0x20, 3.0517578125e-5),
4809 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port1, 0x21, 3.0517578125e-5),
4810 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port2, 0x22, 3.0517578125e-5),
4811 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port3, 0x23, 3.0517578125e-5),
4812 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port4, 0x24, 3.0517578125e-5),
4813 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port5, 0x25, 3.0517578125e-5),
4814 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port6, 0x26, 3.0517578125e-5),
4815 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port7, 0x27, 3.0517578125e-5),
4816 { /* end: all zeroes */ },
4817 };
4818
4819 static struct intel_uncore_type snr_uncore_iio_free_running = {
4820 .name = "iio_free_running",
4821 .num_counters = 9,
4822 .num_boxes = 5,
4823 .num_freerunning_types = SNR_IIO_FREERUNNING_TYPE_MAX,
4824 .freerunning = snr_iio_freerunning,
4825 .ops = &skx_uncore_iio_freerunning_ops,
4826 .event_descs = snr_uncore_iio_freerunning_events,
4827 .format_group = &skx_uncore_iio_freerunning_format_group,
4828 };
4829
4830 static struct intel_uncore_type *snr_msr_uncores[] = {
4831 &snr_uncore_ubox,
4832 &snr_uncore_chabox,
4833 &snr_uncore_iio,
4834 &snr_uncore_irp,
4835 &snr_uncore_m2pcie,
4836 &snr_uncore_pcu,
4837 &snr_uncore_iio_free_running,
4838 NULL,
4839 };
4840
snr_uncore_cpu_init(void)4841 void snr_uncore_cpu_init(void)
4842 {
4843 uncore_msr_uncores = snr_msr_uncores;
4844 }
4845
snr_m2m_uncore_pci_init_box(struct intel_uncore_box * box)4846 static int snr_m2m_uncore_pci_init_box(struct intel_uncore_box *box)
4847 {
4848 struct pci_dev *pdev = box->pci_dev;
4849 int box_ctl = uncore_pci_box_ctl(box);
4850
4851 __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags);
4852 return pci_write_config_dword(pdev, box_ctl, IVBEP_PMON_BOX_CTL_INT);
4853 }
4854
4855 static struct intel_uncore_ops snr_m2m_uncore_pci_ops = {
4856 .init_box = snr_m2m_uncore_pci_init_box,
4857 .disable_box = snbep_uncore_pci_disable_box,
4858 .enable_box = snbep_uncore_pci_enable_box,
4859 .disable_event = snbep_uncore_pci_disable_event,
4860 .enable_event = snbep_uncore_pci_enable_event,
4861 .read_counter = snbep_uncore_pci_read_counter,
4862 };
4863
4864 static struct attribute *snr_m2m_uncore_formats_attr[] = {
4865 &format_attr_event.attr,
4866 &format_attr_umask_ext3.attr,
4867 &format_attr_edge.attr,
4868 &format_attr_inv.attr,
4869 &format_attr_thresh8.attr,
4870 NULL,
4871 };
4872
4873 static const struct attribute_group snr_m2m_uncore_format_group = {
4874 .name = "format",
4875 .attrs = snr_m2m_uncore_formats_attr,
4876 };
4877
4878 static struct intel_uncore_type snr_uncore_m2m = {
4879 .name = "m2m",
4880 .num_counters = 4,
4881 .num_boxes = 1,
4882 .perf_ctr_bits = 48,
4883 .perf_ctr = SNR_M2M_PCI_PMON_CTR0,
4884 .event_ctl = SNR_M2M_PCI_PMON_CTL0,
4885 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
4886 .event_mask_ext = SNR_M2M_PCI_PMON_UMASK_EXT,
4887 .box_ctl = SNR_M2M_PCI_PMON_BOX_CTL,
4888 .ops = &snr_m2m_uncore_pci_ops,
4889 .format_group = &snr_m2m_uncore_format_group,
4890 };
4891
snr_uncore_pci_enable_event(struct intel_uncore_box * box,struct perf_event * event)4892 static void snr_uncore_pci_enable_event(struct intel_uncore_box *box, struct perf_event *event)
4893 {
4894 struct pci_dev *pdev = box->pci_dev;
4895 struct hw_perf_event *hwc = &event->hw;
4896
4897 pci_write_config_dword(pdev, hwc->config_base, (u32)(hwc->config | SNBEP_PMON_CTL_EN));
4898 pci_write_config_dword(pdev, hwc->config_base + 4, (u32)(hwc->config >> 32));
4899 }
4900
4901 static struct intel_uncore_ops snr_pcie3_uncore_pci_ops = {
4902 .init_box = snr_m2m_uncore_pci_init_box,
4903 .disable_box = snbep_uncore_pci_disable_box,
4904 .enable_box = snbep_uncore_pci_enable_box,
4905 .disable_event = snbep_uncore_pci_disable_event,
4906 .enable_event = snr_uncore_pci_enable_event,
4907 .read_counter = snbep_uncore_pci_read_counter,
4908 };
4909
4910 static struct intel_uncore_type snr_uncore_pcie3 = {
4911 .name = "pcie3",
4912 .num_counters = 4,
4913 .num_boxes = 1,
4914 .perf_ctr_bits = 48,
4915 .perf_ctr = SNR_PCIE3_PCI_PMON_CTR0,
4916 .event_ctl = SNR_PCIE3_PCI_PMON_CTL0,
4917 .event_mask = SKX_IIO_PMON_RAW_EVENT_MASK,
4918 .event_mask_ext = SKX_IIO_PMON_RAW_EVENT_MASK_EXT,
4919 .box_ctl = SNR_PCIE3_PCI_PMON_BOX_CTL,
4920 .ops = &snr_pcie3_uncore_pci_ops,
4921 .format_group = &skx_uncore_iio_format_group,
4922 };
4923
4924 enum {
4925 SNR_PCI_UNCORE_M2M,
4926 SNR_PCI_UNCORE_PCIE3,
4927 };
4928
4929 static struct intel_uncore_type *snr_pci_uncores[] = {
4930 [SNR_PCI_UNCORE_M2M] = &snr_uncore_m2m,
4931 [SNR_PCI_UNCORE_PCIE3] = &snr_uncore_pcie3,
4932 NULL,
4933 };
4934
4935 static const struct pci_device_id snr_uncore_pci_ids[] = {
4936 { /* M2M */
4937 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x344a),
4938 .driver_data = UNCORE_PCI_DEV_FULL_DATA(12, 0, SNR_PCI_UNCORE_M2M, 0),
4939 },
4940 { /* end: all zeroes */ }
4941 };
4942
4943 static struct pci_driver snr_uncore_pci_driver = {
4944 .name = "snr_uncore",
4945 .id_table = snr_uncore_pci_ids,
4946 };
4947
4948 static const struct pci_device_id snr_uncore_pci_sub_ids[] = {
4949 { /* PCIe3 RP */
4950 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x334a),
4951 .driver_data = UNCORE_PCI_DEV_FULL_DATA(4, 0, SNR_PCI_UNCORE_PCIE3, 0),
4952 },
4953 { /* end: all zeroes */ }
4954 };
4955
4956 static struct pci_driver snr_uncore_pci_sub_driver = {
4957 .name = "snr_uncore_sub",
4958 .id_table = snr_uncore_pci_sub_ids,
4959 };
4960
snr_uncore_pci_init(void)4961 int snr_uncore_pci_init(void)
4962 {
4963 /* SNR UBOX DID */
4964 int ret = snbep_pci2phy_map_init(0x3460, SKX_CPUNODEID,
4965 SKX_GIDNIDMAP, true);
4966
4967 if (ret)
4968 return ret;
4969
4970 uncore_pci_uncores = snr_pci_uncores;
4971 uncore_pci_driver = &snr_uncore_pci_driver;
4972 uncore_pci_sub_driver = &snr_uncore_pci_sub_driver;
4973 return 0;
4974 }
4975
4976 #define SNR_MC_DEVICE_ID 0x3451
4977
snr_uncore_get_mc_dev(unsigned int device,int id)4978 static struct pci_dev *snr_uncore_get_mc_dev(unsigned int device, int id)
4979 {
4980 struct pci_dev *mc_dev = NULL;
4981 int pkg;
4982
4983 while (1) {
4984 mc_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, mc_dev);
4985 if (!mc_dev)
4986 break;
4987 pkg = uncore_pcibus_to_dieid(mc_dev->bus);
4988 if (pkg == id)
4989 break;
4990 }
4991 return mc_dev;
4992 }
4993
snr_uncore_mmio_map(struct intel_uncore_box * box,unsigned int box_ctl,int mem_offset,unsigned int device)4994 static int snr_uncore_mmio_map(struct intel_uncore_box *box,
4995 unsigned int box_ctl, int mem_offset,
4996 unsigned int device)
4997 {
4998 struct pci_dev *pdev = snr_uncore_get_mc_dev(device, box->dieid);
4999 struct intel_uncore_type *type = box->pmu->type;
5000 resource_size_t addr;
5001 u32 pci_dword;
5002
5003 if (!pdev)
5004 return -ENODEV;
5005
5006 pci_read_config_dword(pdev, SNR_IMC_MMIO_BASE_OFFSET, &pci_dword);
5007 addr = ((resource_size_t)pci_dword & SNR_IMC_MMIO_BASE_MASK) << 23;
5008
5009 pci_read_config_dword(pdev, mem_offset, &pci_dword);
5010 addr |= (pci_dword & SNR_IMC_MMIO_MEM0_MASK) << 12;
5011
5012 addr += box_ctl;
5013
5014 pci_dev_put(pdev);
5015
5016 box->io_addr = ioremap(addr, type->mmio_map_size);
5017 if (!box->io_addr) {
5018 pr_warn("perf uncore: Failed to ioremap for %s.\n", type->name);
5019 return -EINVAL;
5020 }
5021
5022 return 0;
5023 }
5024
__snr_uncore_mmio_init_box(struct intel_uncore_box * box,unsigned int box_ctl,int mem_offset,unsigned int device)5025 static int __snr_uncore_mmio_init_box(struct intel_uncore_box *box,
5026 unsigned int box_ctl, int mem_offset,
5027 unsigned int device)
5028 {
5029 int ret;
5030
5031 ret = snr_uncore_mmio_map(box, box_ctl, mem_offset, device);
5032 if (!ret)
5033 writel(IVBEP_PMON_BOX_CTL_INT, box->io_addr);
5034
5035 return ret;
5036 }
5037
snr_uncore_mmio_init_box(struct intel_uncore_box * box)5038 static int snr_uncore_mmio_init_box(struct intel_uncore_box *box)
5039 {
5040 return __snr_uncore_mmio_init_box(box, uncore_mmio_box_ctl(box),
5041 SNR_IMC_MMIO_MEM0_OFFSET,
5042 SNR_MC_DEVICE_ID);
5043 }
5044
snr_uncore_mmio_disable_box(struct intel_uncore_box * box)5045 static void snr_uncore_mmio_disable_box(struct intel_uncore_box *box)
5046 {
5047 u32 config;
5048
5049 if (!box->io_addr)
5050 return;
5051
5052 config = readl(box->io_addr);
5053 config |= SNBEP_PMON_BOX_CTL_FRZ;
5054 writel(config, box->io_addr);
5055 }
5056
snr_uncore_mmio_enable_box(struct intel_uncore_box * box)5057 static void snr_uncore_mmio_enable_box(struct intel_uncore_box *box)
5058 {
5059 u32 config;
5060
5061 if (!box->io_addr)
5062 return;
5063
5064 config = readl(box->io_addr);
5065 config &= ~SNBEP_PMON_BOX_CTL_FRZ;
5066 writel(config, box->io_addr);
5067 }
5068
snr_uncore_mmio_enable_event(struct intel_uncore_box * box,struct perf_event * event)5069 static void snr_uncore_mmio_enable_event(struct intel_uncore_box *box,
5070 struct perf_event *event)
5071 {
5072 struct hw_perf_event *hwc = &event->hw;
5073
5074 if (!box->io_addr)
5075 return;
5076
5077 if (!uncore_mmio_is_valid_offset(box, hwc->config_base))
5078 return;
5079
5080 writel(hwc->config | SNBEP_PMON_CTL_EN,
5081 box->io_addr + hwc->config_base);
5082 }
5083
snr_uncore_mmio_disable_event(struct intel_uncore_box * box,struct perf_event * event)5084 static void snr_uncore_mmio_disable_event(struct intel_uncore_box *box,
5085 struct perf_event *event)
5086 {
5087 struct hw_perf_event *hwc = &event->hw;
5088
5089 if (!box->io_addr)
5090 return;
5091
5092 if (!uncore_mmio_is_valid_offset(box, hwc->config_base))
5093 return;
5094
5095 writel(hwc->config, box->io_addr + hwc->config_base);
5096 }
5097
5098 static struct intel_uncore_ops snr_uncore_mmio_ops = {
5099 .init_box = snr_uncore_mmio_init_box,
5100 .exit_box = uncore_mmio_exit_box,
5101 .disable_box = snr_uncore_mmio_disable_box,
5102 .enable_box = snr_uncore_mmio_enable_box,
5103 .disable_event = snr_uncore_mmio_disable_event,
5104 .enable_event = snr_uncore_mmio_enable_event,
5105 .read_counter = uncore_mmio_read_counter,
5106 };
5107
5108 static struct uncore_event_desc snr_uncore_imc_events[] = {
5109 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x00,umask=0x00"),
5110 INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x0f"),
5111 INTEL_UNCORE_EVENT_DESC(cas_count_read.scale, "6.103515625e-5"),
5112 INTEL_UNCORE_EVENT_DESC(cas_count_read.unit, "MiB"),
5113 INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x30"),
5114 INTEL_UNCORE_EVENT_DESC(cas_count_write.scale, "6.103515625e-5"),
5115 INTEL_UNCORE_EVENT_DESC(cas_count_write.unit, "MiB"),
5116 { /* end: all zeroes */ },
5117 };
5118
5119 static struct intel_uncore_type snr_uncore_imc = {
5120 .name = "imc",
5121 .num_counters = 4,
5122 .num_boxes = 2,
5123 .perf_ctr_bits = 48,
5124 .fixed_ctr_bits = 48,
5125 .fixed_ctr = SNR_IMC_MMIO_PMON_FIXED_CTR,
5126 .fixed_ctl = SNR_IMC_MMIO_PMON_FIXED_CTL,
5127 .event_descs = snr_uncore_imc_events,
5128 .perf_ctr = SNR_IMC_MMIO_PMON_CTR0,
5129 .event_ctl = SNR_IMC_MMIO_PMON_CTL0,
5130 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
5131 .box_ctl = SNR_IMC_MMIO_PMON_BOX_CTL,
5132 .mmio_offset = SNR_IMC_MMIO_OFFSET,
5133 .mmio_map_size = SNR_IMC_MMIO_SIZE,
5134 .ops = &snr_uncore_mmio_ops,
5135 .format_group = &skx_uncore_format_group,
5136 };
5137
5138 enum perf_uncore_snr_imc_freerunning_type_id {
5139 SNR_IMC_DCLK,
5140 SNR_IMC_DDR,
5141
5142 SNR_IMC_FREERUNNING_TYPE_MAX,
5143 };
5144
5145 static struct freerunning_counters snr_imc_freerunning[] = {
5146 [SNR_IMC_DCLK] = { 0x22b0, 0x0, 0, 1, 48 },
5147 [SNR_IMC_DDR] = { 0x2290, 0x8, 0, 2, 48 },
5148 };
5149
5150 static struct uncore_event_desc snr_uncore_imc_freerunning_events[] = {
5151 INTEL_UNCORE_EVENT_DESC(dclk, "event=0xff,umask=0x10"),
5152
5153 INTEL_UNCORE_FR_EVENT_DESC(read, 0x20, 6.103515625e-5),
5154 INTEL_UNCORE_FR_EVENT_DESC(write, 0x21, 6.103515625e-5),
5155 { /* end: all zeroes */ },
5156 };
5157
5158 static struct intel_uncore_ops snr_uncore_imc_freerunning_ops = {
5159 .init_box = snr_uncore_mmio_init_box,
5160 .exit_box = uncore_mmio_exit_box,
5161 .read_counter = uncore_mmio_read_counter,
5162 .hw_config = uncore_freerunning_hw_config,
5163 };
5164
5165 static struct intel_uncore_type snr_uncore_imc_free_running = {
5166 .name = "imc_free_running",
5167 .num_counters = 3,
5168 .num_boxes = 1,
5169 .num_freerunning_types = SNR_IMC_FREERUNNING_TYPE_MAX,
5170 .mmio_map_size = SNR_IMC_MMIO_SIZE,
5171 .freerunning = snr_imc_freerunning,
5172 .ops = &snr_uncore_imc_freerunning_ops,
5173 .event_descs = snr_uncore_imc_freerunning_events,
5174 .format_group = &skx_uncore_iio_freerunning_format_group,
5175 };
5176
5177 static struct intel_uncore_type *snr_mmio_uncores[] = {
5178 &snr_uncore_imc,
5179 &snr_uncore_imc_free_running,
5180 NULL,
5181 };
5182
snr_uncore_mmio_init(void)5183 void snr_uncore_mmio_init(void)
5184 {
5185 uncore_mmio_uncores = snr_mmio_uncores;
5186 }
5187
5188 /* end of SNR uncore support */
5189
5190 /* ICX uncore support */
5191
5192 static u64 icx_cha_msr_offsets[] = {
5193 0x2a0, 0x2ae, 0x2bc, 0x2ca, 0x2d8, 0x2e6, 0x2f4, 0x302, 0x310,
5194 0x31e, 0x32c, 0x33a, 0x348, 0x356, 0x364, 0x372, 0x380, 0x38e,
5195 0x3aa, 0x3b8, 0x3c6, 0x3d4, 0x3e2, 0x3f0, 0x3fe, 0x40c, 0x41a,
5196 0x428, 0x436, 0x444, 0x452, 0x460, 0x46e, 0x47c, 0x0, 0xe,
5197 0x1c, 0x2a, 0x38, 0x46,
5198 };
5199
icx_cha_hw_config(struct intel_uncore_box * box,struct perf_event * event)5200 static int icx_cha_hw_config(struct intel_uncore_box *box, struct perf_event *event)
5201 {
5202 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
5203 bool tie_en = !!(event->hw.config & SNBEP_CBO_PMON_CTL_TID_EN);
5204
5205 if (tie_en) {
5206 reg1->reg = ICX_C34_MSR_PMON_BOX_FILTER0 +
5207 icx_cha_msr_offsets[box->pmu->pmu_idx];
5208 reg1->config = event->attr.config1 & SKX_CHA_MSR_PMON_BOX_FILTER_TID;
5209 reg1->idx = 0;
5210 }
5211
5212 return 0;
5213 }
5214
5215 static struct intel_uncore_ops icx_uncore_chabox_ops = {
5216 .init_box = ivbep_uncore_msr_init_box,
5217 .disable_box = snbep_uncore_msr_disable_box,
5218 .enable_box = snbep_uncore_msr_enable_box,
5219 .disable_event = snbep_uncore_msr_disable_event,
5220 .enable_event = snr_cha_enable_event,
5221 .read_counter = uncore_msr_read_counter,
5222 .hw_config = icx_cha_hw_config,
5223 };
5224
5225 static struct intel_uncore_type icx_uncore_chabox = {
5226 .name = "cha",
5227 .num_counters = 4,
5228 .perf_ctr_bits = 48,
5229 .event_ctl = ICX_C34_MSR_PMON_CTL0,
5230 .perf_ctr = ICX_C34_MSR_PMON_CTR0,
5231 .box_ctl = ICX_C34_MSR_PMON_BOX_CTL,
5232 .msr_offsets = icx_cha_msr_offsets,
5233 .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK,
5234 .event_mask_ext = SNR_CHA_RAW_EVENT_MASK_EXT,
5235 .constraints = skx_uncore_chabox_constraints,
5236 .ops = &icx_uncore_chabox_ops,
5237 .format_group = &snr_uncore_chabox_format_group,
5238 };
5239
5240 static u64 icx_msr_offsets[] = {
5241 0x0, 0x20, 0x40, 0x90, 0xb0, 0xd0,
5242 };
5243
5244 static struct event_constraint icx_uncore_iio_constraints[] = {
5245 UNCORE_EVENT_CONSTRAINT(0x02, 0x3),
5246 UNCORE_EVENT_CONSTRAINT(0x03, 0x3),
5247 UNCORE_EVENT_CONSTRAINT(0x83, 0x3),
5248 UNCORE_EVENT_CONSTRAINT(0x88, 0xc),
5249 UNCORE_EVENT_CONSTRAINT(0xc0, 0xc),
5250 UNCORE_EVENT_CONSTRAINT(0xc5, 0xc),
5251 UNCORE_EVENT_CONSTRAINT(0xd5, 0xc),
5252 EVENT_CONSTRAINT_END
5253 };
5254
5255 static umode_t
icx_iio_mapping_visible(struct kobject * kobj,struct attribute * attr,int die)5256 icx_iio_mapping_visible(struct kobject *kobj, struct attribute *attr, int die)
5257 {
5258 /* Root bus 0x00 is valid only for pmu_idx = 5. */
5259 return pmu_iio_mapping_visible(kobj, attr, die, 5);
5260 }
5261
5262 static struct attribute_group icx_iio_mapping_group = {
5263 .is_visible = icx_iio_mapping_visible,
5264 };
5265
5266 static const struct attribute_group *icx_iio_attr_update[] = {
5267 &icx_iio_mapping_group,
5268 NULL,
5269 };
5270
5271 /*
5272 * ICX has a static mapping of stack IDs from SAD_CONTROL_CFG notation to PMON
5273 */
5274 enum {
5275 ICX_PCIE1_PMON_ID,
5276 ICX_PCIE2_PMON_ID,
5277 ICX_PCIE3_PMON_ID,
5278 ICX_PCIE4_PMON_ID,
5279 ICX_PCIE5_PMON_ID,
5280 ICX_CBDMA_DMI_PMON_ID
5281 };
5282
5283 static u8 icx_sad_pmon_mapping[] = {
5284 ICX_CBDMA_DMI_PMON_ID,
5285 ICX_PCIE1_PMON_ID,
5286 ICX_PCIE2_PMON_ID,
5287 ICX_PCIE3_PMON_ID,
5288 ICX_PCIE4_PMON_ID,
5289 ICX_PCIE5_PMON_ID,
5290 };
5291
icx_iio_get_topology(struct intel_uncore_type * type)5292 static int icx_iio_get_topology(struct intel_uncore_type *type)
5293 {
5294 return sad_cfg_iio_topology(type, icx_sad_pmon_mapping);
5295 }
5296
icx_iio_set_mapping(struct intel_uncore_type * type)5297 static void icx_iio_set_mapping(struct intel_uncore_type *type)
5298 {
5299 /* Detect ICX-D system. This case is not supported */
5300 if (boot_cpu_data.x86_vfm == INTEL_ICELAKE_D) {
5301 pmu_clear_mapping_attr(type->attr_update, &icx_iio_mapping_group);
5302 return;
5303 }
5304 pmu_iio_set_mapping(type, &icx_iio_mapping_group);
5305 }
5306
icx_iio_cleanup_mapping(struct intel_uncore_type * type)5307 static void icx_iio_cleanup_mapping(struct intel_uncore_type *type)
5308 {
5309 pmu_cleanup_mapping(type, &icx_iio_mapping_group);
5310 }
5311
5312 static struct intel_uncore_type icx_uncore_iio = {
5313 .name = "iio",
5314 .num_counters = 4,
5315 .num_boxes = 6,
5316 .perf_ctr_bits = 48,
5317 .event_ctl = ICX_IIO_MSR_PMON_CTL0,
5318 .perf_ctr = ICX_IIO_MSR_PMON_CTR0,
5319 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
5320 .event_mask_ext = SNR_IIO_PMON_RAW_EVENT_MASK_EXT,
5321 .box_ctl = ICX_IIO_MSR_PMON_BOX_CTL,
5322 .msr_offsets = icx_msr_offsets,
5323 .constraints = icx_uncore_iio_constraints,
5324 .ops = &skx_uncore_iio_ops,
5325 .format_group = &snr_uncore_iio_format_group,
5326 .attr_update = icx_iio_attr_update,
5327 .get_topology = icx_iio_get_topology,
5328 .set_mapping = icx_iio_set_mapping,
5329 .cleanup_mapping = icx_iio_cleanup_mapping,
5330 };
5331
5332 static struct intel_uncore_type icx_uncore_irp = {
5333 .name = "irp",
5334 .num_counters = 2,
5335 .num_boxes = 6,
5336 .perf_ctr_bits = 48,
5337 .event_ctl = ICX_IRP0_MSR_PMON_CTL0,
5338 .perf_ctr = ICX_IRP0_MSR_PMON_CTR0,
5339 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
5340 .box_ctl = ICX_IRP0_MSR_PMON_BOX_CTL,
5341 .msr_offsets = icx_msr_offsets,
5342 .ops = &ivbep_uncore_msr_ops,
5343 .format_group = &ivbep_uncore_format_group,
5344 };
5345
5346 static struct event_constraint icx_uncore_m2pcie_constraints[] = {
5347 UNCORE_EVENT_CONSTRAINT(0x14, 0x3),
5348 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
5349 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
5350 EVENT_CONSTRAINT_END
5351 };
5352
5353 static struct intel_uncore_type icx_uncore_m2pcie = {
5354 .name = "m2pcie",
5355 .num_counters = 4,
5356 .num_boxes = 6,
5357 .perf_ctr_bits = 48,
5358 .event_ctl = ICX_M2PCIE_MSR_PMON_CTL0,
5359 .perf_ctr = ICX_M2PCIE_MSR_PMON_CTR0,
5360 .box_ctl = ICX_M2PCIE_MSR_PMON_BOX_CTL,
5361 .msr_offsets = icx_msr_offsets,
5362 .constraints = icx_uncore_m2pcie_constraints,
5363 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
5364 .ops = &ivbep_uncore_msr_ops,
5365 .format_group = &ivbep_uncore_format_group,
5366 };
5367
5368 enum perf_uncore_icx_iio_freerunning_type_id {
5369 ICX_IIO_MSR_IOCLK,
5370 ICX_IIO_MSR_BW_IN,
5371
5372 ICX_IIO_FREERUNNING_TYPE_MAX,
5373 };
5374
5375 static unsigned icx_iio_clk_freerunning_box_offsets[] = {
5376 0x0, 0x20, 0x40, 0x90, 0xb0, 0xd0,
5377 };
5378
5379 static unsigned icx_iio_bw_freerunning_box_offsets[] = {
5380 0x0, 0x10, 0x20, 0x90, 0xa0, 0xb0,
5381 };
5382
5383 static struct freerunning_counters icx_iio_freerunning[] = {
5384 [ICX_IIO_MSR_IOCLK] = { 0xa55, 0x1, 0x20, 1, 48, icx_iio_clk_freerunning_box_offsets },
5385 [ICX_IIO_MSR_BW_IN] = { 0xaa0, 0x1, 0x10, 8, 48, icx_iio_bw_freerunning_box_offsets },
5386 };
5387
5388 static struct intel_uncore_type icx_uncore_iio_free_running = {
5389 .name = "iio_free_running",
5390 .num_counters = 9,
5391 .num_boxes = 6,
5392 .num_freerunning_types = ICX_IIO_FREERUNNING_TYPE_MAX,
5393 .freerunning = icx_iio_freerunning,
5394 .ops = &skx_uncore_iio_freerunning_ops,
5395 .event_descs = snr_uncore_iio_freerunning_events,
5396 .format_group = &skx_uncore_iio_freerunning_format_group,
5397 };
5398
5399 static struct intel_uncore_type *icx_msr_uncores[] = {
5400 &skx_uncore_ubox,
5401 &icx_uncore_chabox,
5402 &icx_uncore_iio,
5403 &icx_uncore_irp,
5404 &icx_uncore_m2pcie,
5405 &skx_uncore_pcu,
5406 &icx_uncore_iio_free_running,
5407 NULL,
5408 };
5409
5410 /*
5411 * To determine the number of CHAs, it should read CAPID6(Low) and CAPID7 (High)
5412 * registers which located at Device 30, Function 3
5413 */
5414 #define ICX_CAPID6 0x9c
5415 #define ICX_CAPID7 0xa0
5416
icx_count_chabox(void)5417 static u64 icx_count_chabox(void)
5418 {
5419 struct pci_dev *dev = NULL;
5420 u64 caps = 0;
5421
5422 dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x345b, dev);
5423 if (!dev)
5424 goto out;
5425
5426 pci_read_config_dword(dev, ICX_CAPID6, (u32 *)&caps);
5427 pci_read_config_dword(dev, ICX_CAPID7, (u32 *)&caps + 1);
5428 out:
5429 pci_dev_put(dev);
5430 return hweight64(caps);
5431 }
5432
icx_uncore_cpu_init(void)5433 void icx_uncore_cpu_init(void)
5434 {
5435 u64 num_boxes = icx_count_chabox();
5436
5437 if (WARN_ON(num_boxes > ARRAY_SIZE(icx_cha_msr_offsets)))
5438 return;
5439 icx_uncore_chabox.num_boxes = num_boxes;
5440 uncore_msr_uncores = icx_msr_uncores;
5441 }
5442
5443 static struct intel_uncore_type icx_uncore_m2m = {
5444 .name = "m2m",
5445 .num_counters = 4,
5446 .num_boxes = 4,
5447 .perf_ctr_bits = 48,
5448 .perf_ctr = SNR_M2M_PCI_PMON_CTR0,
5449 .event_ctl = SNR_M2M_PCI_PMON_CTL0,
5450 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
5451 .event_mask_ext = SNR_M2M_PCI_PMON_UMASK_EXT,
5452 .box_ctl = SNR_M2M_PCI_PMON_BOX_CTL,
5453 .ops = &snr_m2m_uncore_pci_ops,
5454 .format_group = &snr_m2m_uncore_format_group,
5455 };
5456
5457 static struct attribute *icx_upi_uncore_formats_attr[] = {
5458 &format_attr_event.attr,
5459 &format_attr_umask_ext4.attr,
5460 &format_attr_edge.attr,
5461 &format_attr_inv.attr,
5462 &format_attr_thresh8.attr,
5463 NULL,
5464 };
5465
5466 static const struct attribute_group icx_upi_uncore_format_group = {
5467 .name = "format",
5468 .attrs = icx_upi_uncore_formats_attr,
5469 };
5470
5471 #define ICX_UPI_REGS_ADDR_DEVICE_LINK0 0x02
5472 #define ICX_UPI_REGS_ADDR_FUNCTION 0x01
5473
discover_upi_topology(struct intel_uncore_type * type,int ubox_did,int dev_link0)5474 static int discover_upi_topology(struct intel_uncore_type *type, int ubox_did, int dev_link0)
5475 {
5476 struct pci_dev *ubox = NULL;
5477 struct pci_dev *dev = NULL;
5478 u32 nid, gid;
5479 int idx, lgc_pkg, ret = -EPERM;
5480 struct intel_uncore_topology *upi;
5481 unsigned int devfn;
5482
5483 /* GIDNIDMAP method supports machines which have less than 8 sockets. */
5484 if (uncore_max_dies() > 8)
5485 goto err;
5486
5487 while ((ubox = pci_get_device(PCI_VENDOR_ID_INTEL, ubox_did, ubox))) {
5488 ret = upi_nodeid_groupid(ubox, SKX_CPUNODEID, SKX_GIDNIDMAP, &nid, &gid);
5489 if (ret) {
5490 ret = pcibios_err_to_errno(ret);
5491 break;
5492 }
5493
5494 lgc_pkg = topology_gidnid_map(nid, gid);
5495 if (lgc_pkg < 0) {
5496 ret = -EPERM;
5497 goto err;
5498 }
5499 for (idx = 0; idx < type->num_boxes; idx++) {
5500 upi = &type->topology[lgc_pkg][idx];
5501 devfn = PCI_DEVFN(dev_link0 + idx, ICX_UPI_REGS_ADDR_FUNCTION);
5502 dev = pci_get_domain_bus_and_slot(pci_domain_nr(ubox->bus),
5503 ubox->bus->number,
5504 devfn);
5505 if (dev) {
5506 ret = upi_fill_topology(dev, upi, idx);
5507 pci_dev_put(dev);
5508 if (ret)
5509 goto err;
5510 }
5511 }
5512 }
5513 err:
5514 pci_dev_put(ubox);
5515 return ret;
5516 }
5517
icx_upi_get_topology(struct intel_uncore_type * type)5518 static int icx_upi_get_topology(struct intel_uncore_type *type)
5519 {
5520 return discover_upi_topology(type, ICX_UBOX_DID, ICX_UPI_REGS_ADDR_DEVICE_LINK0);
5521 }
5522
5523 static struct attribute_group icx_upi_mapping_group = {
5524 .is_visible = skx_upi_mapping_visible,
5525 };
5526
5527 static const struct attribute_group *icx_upi_attr_update[] = {
5528 &icx_upi_mapping_group,
5529 NULL
5530 };
5531
icx_upi_set_mapping(struct intel_uncore_type * type)5532 static void icx_upi_set_mapping(struct intel_uncore_type *type)
5533 {
5534 pmu_upi_set_mapping(type, &icx_upi_mapping_group);
5535 }
5536
icx_upi_cleanup_mapping(struct intel_uncore_type * type)5537 static void icx_upi_cleanup_mapping(struct intel_uncore_type *type)
5538 {
5539 pmu_cleanup_mapping(type, &icx_upi_mapping_group);
5540 }
5541
5542 static struct intel_uncore_type icx_uncore_upi = {
5543 .name = "upi",
5544 .num_counters = 4,
5545 .num_boxes = 3,
5546 .perf_ctr_bits = 48,
5547 .perf_ctr = ICX_UPI_PCI_PMON_CTR0,
5548 .event_ctl = ICX_UPI_PCI_PMON_CTL0,
5549 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
5550 .event_mask_ext = ICX_UPI_CTL_UMASK_EXT,
5551 .box_ctl = ICX_UPI_PCI_PMON_BOX_CTL,
5552 .ops = &skx_upi_uncore_pci_ops,
5553 .format_group = &icx_upi_uncore_format_group,
5554 .attr_update = icx_upi_attr_update,
5555 .get_topology = icx_upi_get_topology,
5556 .set_mapping = icx_upi_set_mapping,
5557 .cleanup_mapping = icx_upi_cleanup_mapping,
5558 };
5559
5560 static struct event_constraint icx_uncore_m3upi_constraints[] = {
5561 UNCORE_EVENT_CONSTRAINT_RANGE(0x1c, 0x1f, 0x1),
5562 UNCORE_EVENT_CONSTRAINT(0x40, 0x7),
5563 UNCORE_EVENT_CONSTRAINT_RANGE(0x4e, 0x50, 0x7),
5564 EVENT_CONSTRAINT_END
5565 };
5566
5567 static struct intel_uncore_type icx_uncore_m3upi = {
5568 .name = "m3upi",
5569 .num_counters = 4,
5570 .num_boxes = 3,
5571 .perf_ctr_bits = 48,
5572 .perf_ctr = ICX_M3UPI_PCI_PMON_CTR0,
5573 .event_ctl = ICX_M3UPI_PCI_PMON_CTL0,
5574 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
5575 .box_ctl = ICX_M3UPI_PCI_PMON_BOX_CTL,
5576 .constraints = icx_uncore_m3upi_constraints,
5577 .ops = &ivbep_uncore_pci_ops,
5578 .format_group = &skx_uncore_format_group,
5579 };
5580
5581 enum {
5582 ICX_PCI_UNCORE_M2M,
5583 ICX_PCI_UNCORE_UPI,
5584 ICX_PCI_UNCORE_M3UPI,
5585 };
5586
5587 static struct intel_uncore_type *icx_pci_uncores[] = {
5588 [ICX_PCI_UNCORE_M2M] = &icx_uncore_m2m,
5589 [ICX_PCI_UNCORE_UPI] = &icx_uncore_upi,
5590 [ICX_PCI_UNCORE_M3UPI] = &icx_uncore_m3upi,
5591 NULL,
5592 };
5593
5594 static const struct pci_device_id icx_uncore_pci_ids[] = {
5595 { /* M2M 0 */
5596 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x344a),
5597 .driver_data = UNCORE_PCI_DEV_FULL_DATA(12, 0, ICX_PCI_UNCORE_M2M, 0),
5598 },
5599 { /* M2M 1 */
5600 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x344a),
5601 .driver_data = UNCORE_PCI_DEV_FULL_DATA(13, 0, ICX_PCI_UNCORE_M2M, 1),
5602 },
5603 { /* M2M 2 */
5604 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x344a),
5605 .driver_data = UNCORE_PCI_DEV_FULL_DATA(14, 0, ICX_PCI_UNCORE_M2M, 2),
5606 },
5607 { /* M2M 3 */
5608 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x344a),
5609 .driver_data = UNCORE_PCI_DEV_FULL_DATA(15, 0, ICX_PCI_UNCORE_M2M, 3),
5610 },
5611 { /* UPI Link 0 */
5612 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3441),
5613 .driver_data = UNCORE_PCI_DEV_FULL_DATA(2, 1, ICX_PCI_UNCORE_UPI, 0),
5614 },
5615 { /* UPI Link 1 */
5616 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3441),
5617 .driver_data = UNCORE_PCI_DEV_FULL_DATA(3, 1, ICX_PCI_UNCORE_UPI, 1),
5618 },
5619 { /* UPI Link 2 */
5620 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3441),
5621 .driver_data = UNCORE_PCI_DEV_FULL_DATA(4, 1, ICX_PCI_UNCORE_UPI, 2),
5622 },
5623 { /* M3UPI Link 0 */
5624 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3446),
5625 .driver_data = UNCORE_PCI_DEV_FULL_DATA(5, 1, ICX_PCI_UNCORE_M3UPI, 0),
5626 },
5627 { /* M3UPI Link 1 */
5628 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3446),
5629 .driver_data = UNCORE_PCI_DEV_FULL_DATA(6, 1, ICX_PCI_UNCORE_M3UPI, 1),
5630 },
5631 { /* M3UPI Link 2 */
5632 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3446),
5633 .driver_data = UNCORE_PCI_DEV_FULL_DATA(7, 1, ICX_PCI_UNCORE_M3UPI, 2),
5634 },
5635 { /* end: all zeroes */ }
5636 };
5637
5638 static struct pci_driver icx_uncore_pci_driver = {
5639 .name = "icx_uncore",
5640 .id_table = icx_uncore_pci_ids,
5641 };
5642
icx_uncore_pci_init(void)5643 int icx_uncore_pci_init(void)
5644 {
5645 /* ICX UBOX DID */
5646 int ret = snbep_pci2phy_map_init(0x3450, SKX_CPUNODEID,
5647 SKX_GIDNIDMAP, true);
5648
5649 if (ret)
5650 return ret;
5651
5652 uncore_pci_uncores = icx_pci_uncores;
5653 uncore_pci_driver = &icx_uncore_pci_driver;
5654 return 0;
5655 }
5656
icx_uncore_imc_init_box(struct intel_uncore_box * box)5657 static int icx_uncore_imc_init_box(struct intel_uncore_box *box)
5658 {
5659 unsigned int box_ctl = box->pmu->type->box_ctl +
5660 box->pmu->type->mmio_offset * (box->pmu->pmu_idx % ICX_NUMBER_IMC_CHN);
5661 int mem_offset = (box->pmu->pmu_idx / ICX_NUMBER_IMC_CHN) * ICX_IMC_MEM_STRIDE +
5662 SNR_IMC_MMIO_MEM0_OFFSET;
5663
5664 return __snr_uncore_mmio_init_box(box, box_ctl, mem_offset,
5665 SNR_MC_DEVICE_ID);
5666 }
5667
5668 static struct intel_uncore_ops icx_uncore_mmio_ops = {
5669 .init_box = icx_uncore_imc_init_box,
5670 .exit_box = uncore_mmio_exit_box,
5671 .disable_box = snr_uncore_mmio_disable_box,
5672 .enable_box = snr_uncore_mmio_enable_box,
5673 .disable_event = snr_uncore_mmio_disable_event,
5674 .enable_event = snr_uncore_mmio_enable_event,
5675 .read_counter = uncore_mmio_read_counter,
5676 };
5677
5678 static struct intel_uncore_type icx_uncore_imc = {
5679 .name = "imc",
5680 .num_counters = 4,
5681 .num_boxes = 12,
5682 .perf_ctr_bits = 48,
5683 .fixed_ctr_bits = 48,
5684 .fixed_ctr = SNR_IMC_MMIO_PMON_FIXED_CTR,
5685 .fixed_ctl = SNR_IMC_MMIO_PMON_FIXED_CTL,
5686 .event_descs = snr_uncore_imc_events,
5687 .perf_ctr = SNR_IMC_MMIO_PMON_CTR0,
5688 .event_ctl = SNR_IMC_MMIO_PMON_CTL0,
5689 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
5690 .box_ctl = SNR_IMC_MMIO_PMON_BOX_CTL,
5691 .mmio_offset = SNR_IMC_MMIO_OFFSET,
5692 .mmio_map_size = SNR_IMC_MMIO_SIZE,
5693 .ops = &icx_uncore_mmio_ops,
5694 .format_group = &skx_uncore_format_group,
5695 };
5696
5697 enum perf_uncore_icx_imc_freerunning_type_id {
5698 ICX_IMC_DCLK,
5699 ICX_IMC_DDR,
5700 ICX_IMC_DDRT,
5701
5702 ICX_IMC_FREERUNNING_TYPE_MAX,
5703 };
5704
5705 static struct freerunning_counters icx_imc_freerunning[] = {
5706 [ICX_IMC_DCLK] = { 0x22b0, 0x0, 0, 1, 48 },
5707 [ICX_IMC_DDR] = { 0x2290, 0x8, 0, 2, 48 },
5708 [ICX_IMC_DDRT] = { 0x22a0, 0x8, 0, 2, 48 },
5709 };
5710
5711 static struct uncore_event_desc icx_uncore_imc_freerunning_events[] = {
5712 INTEL_UNCORE_EVENT_DESC(dclk, "event=0xff,umask=0x10"),
5713
5714 INTEL_UNCORE_FR_EVENT_DESC(read, 0x20, 6.103515625e-5),
5715 INTEL_UNCORE_FR_EVENT_DESC(write, 0x21, 6.103515625e-5),
5716 INTEL_UNCORE_FR_EVENT_DESC(ddrt_read, 0x30, 6.103515625e-5),
5717 INTEL_UNCORE_FR_EVENT_DESC(ddrt_write, 0x31, 6.103515625e-5),
5718 { /* end: all zeroes */ },
5719 };
5720
icx_uncore_imc_freerunning_init_box(struct intel_uncore_box * box)5721 static int icx_uncore_imc_freerunning_init_box(struct intel_uncore_box *box)
5722 {
5723 int mem_offset = box->pmu->pmu_idx * ICX_IMC_MEM_STRIDE +
5724 SNR_IMC_MMIO_MEM0_OFFSET;
5725
5726 return snr_uncore_mmio_map(box, uncore_mmio_box_ctl(box),
5727 mem_offset, SNR_MC_DEVICE_ID);
5728 }
5729
5730 static struct intel_uncore_ops icx_uncore_imc_freerunning_ops = {
5731 .init_box = icx_uncore_imc_freerunning_init_box,
5732 .exit_box = uncore_mmio_exit_box,
5733 .read_counter = uncore_mmio_read_counter,
5734 .hw_config = uncore_freerunning_hw_config,
5735 };
5736
5737 static struct intel_uncore_type icx_uncore_imc_free_running = {
5738 .name = "imc_free_running",
5739 .num_counters = 5,
5740 .num_boxes = 4,
5741 .num_freerunning_types = ICX_IMC_FREERUNNING_TYPE_MAX,
5742 .mmio_map_size = SNR_IMC_MMIO_SIZE,
5743 .freerunning = icx_imc_freerunning,
5744 .ops = &icx_uncore_imc_freerunning_ops,
5745 .event_descs = icx_uncore_imc_freerunning_events,
5746 .format_group = &skx_uncore_iio_freerunning_format_group,
5747 };
5748
5749 static struct intel_uncore_type *icx_mmio_uncores[] = {
5750 &icx_uncore_imc,
5751 &icx_uncore_imc_free_running,
5752 NULL,
5753 };
5754
icx_uncore_mmio_init(void)5755 void icx_uncore_mmio_init(void)
5756 {
5757 uncore_mmio_uncores = icx_mmio_uncores;
5758 }
5759
5760 /* end of ICX uncore support */
5761
5762 /* SPR uncore support */
5763
spr_uncore_msr_enable_event(struct intel_uncore_box * box,struct perf_event * event)5764 static void spr_uncore_msr_enable_event(struct intel_uncore_box *box,
5765 struct perf_event *event)
5766 {
5767 struct hw_perf_event *hwc = &event->hw;
5768 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
5769
5770 if (reg1->idx != EXTRA_REG_NONE)
5771 wrmsrq(reg1->reg, reg1->config);
5772
5773 wrmsrq(hwc->config_base, hwc->config);
5774 }
5775
spr_uncore_msr_disable_event(struct intel_uncore_box * box,struct perf_event * event)5776 static void spr_uncore_msr_disable_event(struct intel_uncore_box *box,
5777 struct perf_event *event)
5778 {
5779 struct hw_perf_event *hwc = &event->hw;
5780 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
5781
5782 if (reg1->idx != EXTRA_REG_NONE)
5783 wrmsrq(reg1->reg, 0);
5784
5785 wrmsrq(hwc->config_base, 0);
5786 }
5787
spr_cha_hw_config(struct intel_uncore_box * box,struct perf_event * event)5788 static int spr_cha_hw_config(struct intel_uncore_box *box, struct perf_event *event)
5789 {
5790 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
5791 bool tie_en = !!(event->hw.config & SPR_CHA_PMON_CTL_TID_EN);
5792 struct intel_uncore_type *type = box->pmu->type;
5793 int id = intel_uncore_find_discovery_unit_id(type->boxes, -1, box->pmu->pmu_idx);
5794
5795 if (tie_en) {
5796 reg1->reg = SPR_C0_MSR_PMON_BOX_FILTER0 +
5797 HSWEP_CBO_MSR_OFFSET * id;
5798 reg1->config = event->attr.config1 & SPR_CHA_PMON_BOX_FILTER_TID;
5799 reg1->idx = 0;
5800 }
5801
5802 return 0;
5803 }
5804
5805 static struct intel_uncore_ops spr_uncore_chabox_ops = {
5806 .init_box = intel_generic_uncore_msr_init_box,
5807 .disable_box = intel_generic_uncore_msr_disable_box,
5808 .enable_box = intel_generic_uncore_msr_enable_box,
5809 .disable_event = spr_uncore_msr_disable_event,
5810 .enable_event = spr_uncore_msr_enable_event,
5811 .read_counter = uncore_msr_read_counter,
5812 .hw_config = spr_cha_hw_config,
5813 .get_constraint = uncore_get_constraint,
5814 .put_constraint = uncore_put_constraint,
5815 };
5816
5817 static struct attribute *spr_uncore_cha_formats_attr[] = {
5818 &format_attr_event.attr,
5819 &format_attr_umask_ext5.attr,
5820 &format_attr_tid_en2.attr,
5821 &format_attr_edge.attr,
5822 &format_attr_inv.attr,
5823 &format_attr_thresh8.attr,
5824 &format_attr_filter_tid5.attr,
5825 NULL,
5826 };
5827 static const struct attribute_group spr_uncore_chabox_format_group = {
5828 .name = "format",
5829 .attrs = spr_uncore_cha_formats_attr,
5830 };
5831
alias_show(struct device * dev,struct device_attribute * attr,char * buf)5832 static ssize_t alias_show(struct device *dev,
5833 struct device_attribute *attr,
5834 char *buf)
5835 {
5836 struct intel_uncore_pmu *pmu = dev_to_uncore_pmu(dev);
5837 char pmu_name[UNCORE_PMU_NAME_LEN];
5838
5839 uncore_get_alias_name(pmu_name, pmu);
5840 return sysfs_emit(buf, "%s\n", pmu_name);
5841 }
5842
5843 static DEVICE_ATTR_RO(alias);
5844
5845 static struct attribute *uncore_alias_attrs[] = {
5846 &dev_attr_alias.attr,
5847 NULL
5848 };
5849
5850 ATTRIBUTE_GROUPS(uncore_alias);
5851
5852 static struct intel_uncore_type spr_uncore_chabox = {
5853 .name = "cha",
5854 .event_mask = SPR_CHA_PMON_EVENT_MASK,
5855 .event_mask_ext = SPR_CHA_EVENT_MASK_EXT,
5856 .num_shared_regs = 1,
5857 .constraints = skx_uncore_chabox_constraints,
5858 .ops = &spr_uncore_chabox_ops,
5859 .format_group = &spr_uncore_chabox_format_group,
5860 .attr_update = uncore_alias_groups,
5861 };
5862
5863 static struct intel_uncore_type spr_uncore_iio = {
5864 .name = "iio",
5865 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
5866 .event_mask_ext = SNR_IIO_PMON_RAW_EVENT_MASK_EXT,
5867 .format_group = &snr_uncore_iio_format_group,
5868 .attr_update = uncore_alias_groups,
5869 .constraints = icx_uncore_iio_constraints,
5870 };
5871
5872 static struct attribute *spr_uncore_raw_formats_attr[] = {
5873 &format_attr_event.attr,
5874 &format_attr_umask_ext4.attr,
5875 &format_attr_edge.attr,
5876 &format_attr_inv.attr,
5877 &format_attr_thresh8.attr,
5878 NULL,
5879 };
5880
5881 static const struct attribute_group spr_uncore_raw_format_group = {
5882 .name = "format",
5883 .attrs = spr_uncore_raw_formats_attr,
5884 };
5885
5886 #define SPR_UNCORE_COMMON_FORMAT() \
5887 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, \
5888 .event_mask_ext = SPR_RAW_EVENT_MASK_EXT, \
5889 .format_group = &spr_uncore_raw_format_group, \
5890 .attr_update = uncore_alias_groups
5891
5892 static struct intel_uncore_type spr_uncore_irp = {
5893 SPR_UNCORE_COMMON_FORMAT(),
5894 .name = "irp",
5895
5896 };
5897
5898 static struct event_constraint spr_uncore_m2pcie_constraints[] = {
5899 UNCORE_EVENT_CONSTRAINT(0x14, 0x3),
5900 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
5901 EVENT_CONSTRAINT_END
5902 };
5903
5904 static struct intel_uncore_type spr_uncore_m2pcie = {
5905 SPR_UNCORE_COMMON_FORMAT(),
5906 .name = "m2pcie",
5907 .constraints = spr_uncore_m2pcie_constraints,
5908 };
5909
5910 static struct intel_uncore_type spr_uncore_pcu = {
5911 .name = "pcu",
5912 .attr_update = uncore_alias_groups,
5913 };
5914
spr_uncore_mmio_enable_event(struct intel_uncore_box * box,struct perf_event * event)5915 static void spr_uncore_mmio_enable_event(struct intel_uncore_box *box,
5916 struct perf_event *event)
5917 {
5918 struct hw_perf_event *hwc = &event->hw;
5919
5920 if (!box->io_addr)
5921 return;
5922
5923 if (uncore_pmc_fixed(hwc->idx))
5924 writel(SNBEP_PMON_CTL_EN, box->io_addr + hwc->config_base);
5925 else
5926 writel(hwc->config, box->io_addr + hwc->config_base);
5927 }
5928
5929 static struct intel_uncore_ops spr_uncore_mmio_ops = {
5930 .init_box = intel_generic_uncore_mmio_init_box,
5931 .exit_box = uncore_mmio_exit_box,
5932 .disable_box = intel_generic_uncore_mmio_disable_box,
5933 .enable_box = intel_generic_uncore_mmio_enable_box,
5934 .disable_event = intel_generic_uncore_mmio_disable_event,
5935 .enable_event = spr_uncore_mmio_enable_event,
5936 .read_counter = uncore_mmio_read_counter,
5937 };
5938
5939 static struct uncore_event_desc spr_uncore_imc_events[] = {
5940 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x01,umask=0x00"),
5941 INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x05,umask=0xcf"),
5942 INTEL_UNCORE_EVENT_DESC(cas_count_read.scale, "6.103515625e-5"),
5943 INTEL_UNCORE_EVENT_DESC(cas_count_read.unit, "MiB"),
5944 INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x05,umask=0xf0"),
5945 INTEL_UNCORE_EVENT_DESC(cas_count_write.scale, "6.103515625e-5"),
5946 INTEL_UNCORE_EVENT_DESC(cas_count_write.unit, "MiB"),
5947 { /* end: all zeroes */ },
5948 };
5949
5950 #define SPR_UNCORE_MMIO_COMMON_FORMAT() \
5951 SPR_UNCORE_COMMON_FORMAT(), \
5952 .ops = &spr_uncore_mmio_ops
5953
5954 static struct intel_uncore_type spr_uncore_imc = {
5955 SPR_UNCORE_MMIO_COMMON_FORMAT(),
5956 .name = "imc",
5957 .fixed_ctr_bits = 48,
5958 .fixed_ctr = SNR_IMC_MMIO_PMON_FIXED_CTR,
5959 .fixed_ctl = SNR_IMC_MMIO_PMON_FIXED_CTL,
5960 .event_descs = spr_uncore_imc_events,
5961 };
5962
spr_uncore_pci_enable_event(struct intel_uncore_box * box,struct perf_event * event)5963 static void spr_uncore_pci_enable_event(struct intel_uncore_box *box,
5964 struct perf_event *event)
5965 {
5966 struct pci_dev *pdev = box->pci_dev;
5967 struct hw_perf_event *hwc = &event->hw;
5968
5969 pci_write_config_dword(pdev, hwc->config_base + 4, (u32)(hwc->config >> 32));
5970 pci_write_config_dword(pdev, hwc->config_base, (u32)hwc->config);
5971 }
5972
5973 static struct intel_uncore_ops spr_uncore_pci_ops = {
5974 .init_box = intel_generic_uncore_pci_init_box,
5975 .disable_box = intel_generic_uncore_pci_disable_box,
5976 .enable_box = intel_generic_uncore_pci_enable_box,
5977 .disable_event = intel_generic_uncore_pci_disable_event,
5978 .enable_event = spr_uncore_pci_enable_event,
5979 .read_counter = intel_generic_uncore_pci_read_counter,
5980 };
5981
5982 #define SPR_UNCORE_PCI_COMMON_FORMAT() \
5983 SPR_UNCORE_COMMON_FORMAT(), \
5984 .ops = &spr_uncore_pci_ops
5985
5986 static struct intel_uncore_type spr_uncore_m2m = {
5987 SPR_UNCORE_PCI_COMMON_FORMAT(),
5988 .name = "m2m",
5989 };
5990
5991 static struct attribute_group spr_upi_mapping_group = {
5992 .is_visible = skx_upi_mapping_visible,
5993 };
5994
5995 static const struct attribute_group *spr_upi_attr_update[] = {
5996 &uncore_alias_group,
5997 &spr_upi_mapping_group,
5998 NULL
5999 };
6000
6001 #define SPR_UPI_REGS_ADDR_DEVICE_LINK0 0x01
6002
spr_upi_set_mapping(struct intel_uncore_type * type)6003 static void spr_upi_set_mapping(struct intel_uncore_type *type)
6004 {
6005 pmu_upi_set_mapping(type, &spr_upi_mapping_group);
6006 }
6007
spr_upi_cleanup_mapping(struct intel_uncore_type * type)6008 static void spr_upi_cleanup_mapping(struct intel_uncore_type *type)
6009 {
6010 pmu_cleanup_mapping(type, &spr_upi_mapping_group);
6011 }
6012
spr_upi_get_topology(struct intel_uncore_type * type)6013 static int spr_upi_get_topology(struct intel_uncore_type *type)
6014 {
6015 return discover_upi_topology(type, SPR_UBOX_DID, SPR_UPI_REGS_ADDR_DEVICE_LINK0);
6016 }
6017
6018 static struct intel_uncore_type spr_uncore_mdf = {
6019 SPR_UNCORE_COMMON_FORMAT(),
6020 .name = "mdf",
6021 };
6022
spr_uncore_mmio_offs8_init_box(struct intel_uncore_box * box)6023 static int spr_uncore_mmio_offs8_init_box(struct intel_uncore_box *box)
6024 {
6025 __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags);
6026 return intel_generic_uncore_mmio_init_box(box);
6027 }
6028
6029 static struct intel_uncore_ops spr_uncore_mmio_offs8_ops = {
6030 .init_box = spr_uncore_mmio_offs8_init_box,
6031 .exit_box = uncore_mmio_exit_box,
6032 .disable_box = intel_generic_uncore_mmio_disable_box,
6033 .enable_box = intel_generic_uncore_mmio_enable_box,
6034 .disable_event = intel_generic_uncore_mmio_disable_event,
6035 .enable_event = spr_uncore_mmio_enable_event,
6036 .read_counter = uncore_mmio_read_counter,
6037 };
6038
6039 #define SPR_UNCORE_MMIO_OFFS8_COMMON_FORMAT() \
6040 SPR_UNCORE_COMMON_FORMAT(), \
6041 .ops = &spr_uncore_mmio_offs8_ops
6042
6043 static struct event_constraint spr_uncore_cxlcm_constraints[] = {
6044 UNCORE_EVENT_CONSTRAINT(0x02, 0x0f),
6045 UNCORE_EVENT_CONSTRAINT(0x05, 0x0f),
6046 UNCORE_EVENT_CONSTRAINT_RANGE(0x40, 0x43, 0xf0),
6047 UNCORE_EVENT_CONSTRAINT(0x4b, 0xf0),
6048 UNCORE_EVENT_CONSTRAINT(0x52, 0xf0),
6049 EVENT_CONSTRAINT_END
6050 };
6051
6052 static struct intel_uncore_type spr_uncore_cxlcm = {
6053 SPR_UNCORE_MMIO_OFFS8_COMMON_FORMAT(),
6054 .name = "cxlcm",
6055 .constraints = spr_uncore_cxlcm_constraints,
6056 };
6057
6058 static struct intel_uncore_type spr_uncore_cxldp = {
6059 SPR_UNCORE_MMIO_OFFS8_COMMON_FORMAT(),
6060 .name = "cxldp",
6061 };
6062
6063 static struct intel_uncore_type spr_uncore_hbm = {
6064 SPR_UNCORE_COMMON_FORMAT(),
6065 .name = "hbm",
6066 };
6067
6068 #define UNCORE_SPR_NUM_UNCORE_TYPES 15
6069 #define UNCORE_SPR_CHA 0
6070 #define UNCORE_SPR_IIO 1
6071 #define UNCORE_SPR_IMC 6
6072 #define UNCORE_SPR_UPI 8
6073 #define UNCORE_SPR_M3UPI 9
6074
6075 /*
6076 * The uncore units, which are supported by the discovery table,
6077 * are defined here.
6078 */
6079 static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
6080 &spr_uncore_chabox,
6081 &spr_uncore_iio,
6082 &spr_uncore_irp,
6083 &spr_uncore_m2pcie,
6084 &spr_uncore_pcu,
6085 NULL,
6086 &spr_uncore_imc,
6087 &spr_uncore_m2m,
6088 NULL,
6089 NULL,
6090 NULL,
6091 &spr_uncore_mdf,
6092 &spr_uncore_cxlcm,
6093 &spr_uncore_cxldp,
6094 &spr_uncore_hbm,
6095 };
6096
6097 /*
6098 * The uncore units, which are not supported by the discovery table,
6099 * are implemented from here.
6100 */
6101 #define SPR_UNCORE_UPI_NUM_BOXES 4
6102
6103 static u64 spr_upi_pci_offsets[SPR_UNCORE_UPI_NUM_BOXES] = {
6104 0, 0x8000, 0x10000, 0x18000
6105 };
6106
spr_extra_boxes_cleanup(struct intel_uncore_type * type)6107 static void spr_extra_boxes_cleanup(struct intel_uncore_type *type)
6108 {
6109 struct intel_uncore_discovery_unit *pos;
6110 struct rb_node *node;
6111
6112 if (!type->boxes)
6113 return;
6114
6115 while (!RB_EMPTY_ROOT(type->boxes)) {
6116 node = rb_first(type->boxes);
6117 pos = rb_entry(node, struct intel_uncore_discovery_unit, node);
6118 rb_erase(node, type->boxes);
6119 kfree(pos);
6120 }
6121 kfree(type->boxes);
6122 type->boxes = NULL;
6123 }
6124
6125 static struct intel_uncore_type spr_uncore_upi = {
6126 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
6127 .event_mask_ext = SPR_RAW_EVENT_MASK_EXT,
6128 .format_group = &spr_uncore_raw_format_group,
6129 .ops = &spr_uncore_pci_ops,
6130 .name = "upi",
6131 .attr_update = spr_upi_attr_update,
6132 .get_topology = spr_upi_get_topology,
6133 .set_mapping = spr_upi_set_mapping,
6134 .cleanup_mapping = spr_upi_cleanup_mapping,
6135 .type_id = UNCORE_SPR_UPI,
6136 .num_counters = 4,
6137 .num_boxes = SPR_UNCORE_UPI_NUM_BOXES,
6138 .perf_ctr_bits = 48,
6139 .perf_ctr = ICX_UPI_PCI_PMON_CTR0 - ICX_UPI_PCI_PMON_BOX_CTL,
6140 .event_ctl = ICX_UPI_PCI_PMON_CTL0 - ICX_UPI_PCI_PMON_BOX_CTL,
6141 .box_ctl = ICX_UPI_PCI_PMON_BOX_CTL,
6142 .pci_offsets = spr_upi_pci_offsets,
6143 .cleanup_extra_boxes = spr_extra_boxes_cleanup,
6144 };
6145
6146 static struct intel_uncore_type spr_uncore_m3upi = {
6147 SPR_UNCORE_PCI_COMMON_FORMAT(),
6148 .name = "m3upi",
6149 .type_id = UNCORE_SPR_M3UPI,
6150 .num_counters = 4,
6151 .num_boxes = SPR_UNCORE_UPI_NUM_BOXES,
6152 .perf_ctr_bits = 48,
6153 .perf_ctr = ICX_M3UPI_PCI_PMON_CTR0 - ICX_M3UPI_PCI_PMON_BOX_CTL,
6154 .event_ctl = ICX_M3UPI_PCI_PMON_CTL0 - ICX_M3UPI_PCI_PMON_BOX_CTL,
6155 .box_ctl = ICX_M3UPI_PCI_PMON_BOX_CTL,
6156 .pci_offsets = spr_upi_pci_offsets,
6157 .constraints = icx_uncore_m3upi_constraints,
6158 .cleanup_extra_boxes = spr_extra_boxes_cleanup,
6159 };
6160
6161 enum perf_uncore_spr_iio_freerunning_type_id {
6162 SPR_IIO_MSR_IOCLK,
6163 SPR_IIO_MSR_BW_IN,
6164 SPR_IIO_MSR_BW_OUT,
6165
6166 SPR_IIO_FREERUNNING_TYPE_MAX,
6167 };
6168
6169 static struct freerunning_counters spr_iio_freerunning[] = {
6170 [SPR_IIO_MSR_IOCLK] = { 0x340e, 0x1, 0x10, 1, 48 },
6171 [SPR_IIO_MSR_BW_IN] = { 0x3800, 0x1, 0x10, 8, 48 },
6172 [SPR_IIO_MSR_BW_OUT] = { 0x3808, 0x1, 0x10, 8, 48 },
6173 };
6174
6175 static struct intel_uncore_type spr_uncore_iio_free_running = {
6176 .name = "iio_free_running",
6177 .num_counters = 17,
6178 .num_freerunning_types = SPR_IIO_FREERUNNING_TYPE_MAX,
6179 .freerunning = spr_iio_freerunning,
6180 .ops = &skx_uncore_iio_freerunning_ops,
6181 .event_descs = snr_uncore_iio_freerunning_events,
6182 .format_group = &skx_uncore_iio_freerunning_format_group,
6183 };
6184
6185 enum perf_uncore_spr_imc_freerunning_type_id {
6186 SPR_IMC_DCLK,
6187 SPR_IMC_PQ_CYCLES,
6188
6189 SPR_IMC_FREERUNNING_TYPE_MAX,
6190 };
6191
6192 static struct freerunning_counters spr_imc_freerunning[] = {
6193 [SPR_IMC_DCLK] = { 0x22b0, 0x0, 0, 1, 48 },
6194 [SPR_IMC_PQ_CYCLES] = { 0x2318, 0x8, 0, 2, 48 },
6195 };
6196
6197 static struct uncore_event_desc spr_uncore_imc_freerunning_events[] = {
6198 INTEL_UNCORE_EVENT_DESC(dclk, "event=0xff,umask=0x10"),
6199
6200 INTEL_UNCORE_EVENT_DESC(rpq_cycles, "event=0xff,umask=0x20"),
6201 INTEL_UNCORE_EVENT_DESC(wpq_cycles, "event=0xff,umask=0x21"),
6202 { /* end: all zeroes */ },
6203 };
6204
6205 #define SPR_MC_DEVICE_ID 0x3251
6206
spr_uncore_imc_freerunning_init_box(struct intel_uncore_box * box)6207 static int spr_uncore_imc_freerunning_init_box(struct intel_uncore_box *box)
6208 {
6209 int mem_offset = box->pmu->pmu_idx * ICX_IMC_MEM_STRIDE + SNR_IMC_MMIO_MEM0_OFFSET;
6210 return snr_uncore_mmio_map(box, uncore_mmio_box_ctl(box),
6211 mem_offset, SPR_MC_DEVICE_ID);
6212 }
6213
6214 static struct intel_uncore_ops spr_uncore_imc_freerunning_ops = {
6215 .init_box = spr_uncore_imc_freerunning_init_box,
6216 .exit_box = uncore_mmio_exit_box,
6217 .read_counter = uncore_mmio_read_counter,
6218 .hw_config = uncore_freerunning_hw_config,
6219 };
6220
6221 static struct intel_uncore_type spr_uncore_imc_free_running = {
6222 .name = "imc_free_running",
6223 .num_counters = 3,
6224 .mmio_map_size = SNR_IMC_MMIO_SIZE,
6225 .num_freerunning_types = SPR_IMC_FREERUNNING_TYPE_MAX,
6226 .freerunning = spr_imc_freerunning,
6227 .ops = &spr_uncore_imc_freerunning_ops,
6228 .event_descs = spr_uncore_imc_freerunning_events,
6229 .format_group = &skx_uncore_iio_freerunning_format_group,
6230 };
6231
6232 #define UNCORE_SPR_MSR_EXTRA_UNCORES 1
6233 #define UNCORE_SPR_MMIO_EXTRA_UNCORES 1
6234 #define UNCORE_SPR_PCI_EXTRA_UNCORES 2
6235
6236 static struct intel_uncore_type *spr_msr_uncores[UNCORE_SPR_MSR_EXTRA_UNCORES] = {
6237 &spr_uncore_iio_free_running,
6238 };
6239
6240 static struct intel_uncore_type *spr_mmio_uncores[UNCORE_SPR_MMIO_EXTRA_UNCORES] = {
6241 &spr_uncore_imc_free_running,
6242 };
6243
6244 static struct intel_uncore_type *spr_pci_uncores[UNCORE_SPR_PCI_EXTRA_UNCORES] = {
6245 &spr_uncore_upi,
6246 &spr_uncore_m3upi
6247 };
6248
6249 int spr_uncore_units_ignore[] = {
6250 UNCORE_SPR_UPI,
6251 UNCORE_SPR_M3UPI,
6252 UNCORE_IGNORE_END
6253 };
6254
uncore_type_customized_copy(struct intel_uncore_type * to_type,struct intel_uncore_type * from_type)6255 static void uncore_type_customized_copy(struct intel_uncore_type *to_type,
6256 struct intel_uncore_type *from_type)
6257 {
6258 if (!to_type || !from_type)
6259 return;
6260
6261 if (from_type->name)
6262 to_type->name = from_type->name;
6263 if (from_type->fixed_ctr_bits)
6264 to_type->fixed_ctr_bits = from_type->fixed_ctr_bits;
6265 if (from_type->event_mask)
6266 to_type->event_mask = from_type->event_mask;
6267 if (from_type->event_mask_ext)
6268 to_type->event_mask_ext = from_type->event_mask_ext;
6269 if (from_type->fixed_ctr)
6270 to_type->fixed_ctr = from_type->fixed_ctr;
6271 if (from_type->fixed_ctl)
6272 to_type->fixed_ctl = from_type->fixed_ctl;
6273 if (from_type->fixed_ctr_bits)
6274 to_type->fixed_ctr_bits = from_type->fixed_ctr_bits;
6275 if (from_type->num_shared_regs)
6276 to_type->num_shared_regs = from_type->num_shared_regs;
6277 if (from_type->constraints)
6278 to_type->constraints = from_type->constraints;
6279 if (from_type->ops)
6280 to_type->ops = from_type->ops;
6281 if (from_type->event_descs)
6282 to_type->event_descs = from_type->event_descs;
6283 if (from_type->format_group)
6284 to_type->format_group = from_type->format_group;
6285 if (from_type->attr_update)
6286 to_type->attr_update = from_type->attr_update;
6287 if (from_type->set_mapping)
6288 to_type->set_mapping = from_type->set_mapping;
6289 if (from_type->get_topology)
6290 to_type->get_topology = from_type->get_topology;
6291 if (from_type->cleanup_mapping)
6292 to_type->cleanup_mapping = from_type->cleanup_mapping;
6293 if (from_type->mmio_map_size)
6294 to_type->mmio_map_size = from_type->mmio_map_size;
6295 }
6296
6297 struct intel_uncore_type **
uncore_get_uncores(enum uncore_access_type type_id,int num_extra,struct intel_uncore_type ** extra,int max_num_types,struct intel_uncore_type ** uncores)6298 uncore_get_uncores(enum uncore_access_type type_id, int num_extra,
6299 struct intel_uncore_type **extra, int max_num_types,
6300 struct intel_uncore_type **uncores)
6301 {
6302 struct intel_uncore_type **types, **start_types;
6303 int i;
6304
6305 start_types = types = intel_uncore_generic_init_uncores(type_id, num_extra);
6306
6307 /* Only copy the customized features */
6308 for (; *types; types++) {
6309 if ((*types)->type_id >= max_num_types)
6310 continue;
6311 uncore_type_customized_copy(*types, uncores[(*types)->type_id]);
6312 }
6313
6314 for (i = 0; i < num_extra; i++, types++)
6315 *types = extra[i];
6316
6317 return start_types;
6318 }
6319
6320 static struct intel_uncore_type *
uncore_find_type_by_id(struct intel_uncore_type ** types,int type_id)6321 uncore_find_type_by_id(struct intel_uncore_type **types, int type_id)
6322 {
6323 for (; *types; types++) {
6324 if (type_id == (*types)->type_id)
6325 return *types;
6326 }
6327
6328 return NULL;
6329 }
6330
uncore_type_max_boxes(struct intel_uncore_type ** types,int type_id)6331 static int uncore_type_max_boxes(struct intel_uncore_type **types,
6332 int type_id)
6333 {
6334 struct intel_uncore_discovery_unit *unit;
6335 struct intel_uncore_type *type;
6336 struct rb_node *node;
6337 int max = 0;
6338
6339 type = uncore_find_type_by_id(types, type_id);
6340 if (!type)
6341 return 0;
6342
6343 for (node = rb_first(type->boxes); node; node = rb_next(node)) {
6344 unit = rb_entry(node, struct intel_uncore_discovery_unit, node);
6345
6346 /*
6347 * on DMR IMH2, the unit id starts from 0x8000,
6348 * and we don't need to count it.
6349 */
6350 if ((unit->id > max) && (unit->id < 0x8000))
6351 max = unit->id;
6352 }
6353 return max + 1;
6354 }
6355
6356 #define SPR_MSR_UNC_CBO_CONFIG 0x2FFE
6357
spr_uncore_cpu_init(void)6358 void spr_uncore_cpu_init(void)
6359 {
6360 struct intel_uncore_type *type;
6361 u64 num_cbo;
6362
6363 uncore_msr_uncores = uncore_get_uncores(UNCORE_ACCESS_MSR,
6364 UNCORE_SPR_MSR_EXTRA_UNCORES,
6365 spr_msr_uncores,
6366 UNCORE_SPR_NUM_UNCORE_TYPES,
6367 spr_uncores);
6368
6369 type = uncore_find_type_by_id(uncore_msr_uncores, UNCORE_SPR_CHA);
6370 if (type) {
6371 /*
6372 * The value from the discovery table (stored in the type->num_boxes
6373 * of UNCORE_SPR_CHA) is incorrect on some SPR variants because of a
6374 * firmware bug. Using the value from SPR_MSR_UNC_CBO_CONFIG to replace it.
6375 */
6376 rdmsrq(SPR_MSR_UNC_CBO_CONFIG, num_cbo);
6377 /*
6378 * The MSR doesn't work on the EMR XCC, but the firmware bug doesn't impact
6379 * the EMR XCC. Don't let the value from the MSR replace the existing value.
6380 */
6381 if (num_cbo)
6382 type->num_boxes = num_cbo;
6383 }
6384 spr_uncore_iio_free_running.num_boxes = uncore_type_max_boxes(uncore_msr_uncores, UNCORE_SPR_IIO);
6385 }
6386
6387 #define SPR_UNCORE_UPI_PCIID 0x3241
6388 #define SPR_UNCORE_UPI0_DEVFN 0x9
6389 #define SPR_UNCORE_M3UPI_PCIID 0x3246
6390 #define SPR_UNCORE_M3UPI0_DEVFN 0x29
6391
spr_update_device_location(int type_id)6392 static void spr_update_device_location(int type_id)
6393 {
6394 struct intel_uncore_discovery_unit *unit;
6395 struct intel_uncore_type *type;
6396 struct pci_dev *dev = NULL;
6397 struct rb_root *root;
6398 u32 device, devfn;
6399 int die;
6400
6401 if (type_id == UNCORE_SPR_UPI) {
6402 type = &spr_uncore_upi;
6403 device = SPR_UNCORE_UPI_PCIID;
6404 devfn = SPR_UNCORE_UPI0_DEVFN;
6405 } else if (type_id == UNCORE_SPR_M3UPI) {
6406 type = &spr_uncore_m3upi;
6407 device = SPR_UNCORE_M3UPI_PCIID;
6408 devfn = SPR_UNCORE_M3UPI0_DEVFN;
6409 } else
6410 return;
6411
6412 root = kzalloc_obj(struct rb_root);
6413 if (!root) {
6414 type->num_boxes = 0;
6415 return;
6416 }
6417 *root = RB_ROOT;
6418
6419 while ((dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, dev)) != NULL) {
6420
6421 die = uncore_pcibus_to_dieid(dev->bus);
6422 if (die < 0)
6423 continue;
6424
6425 unit = kzalloc_obj(*unit);
6426 if (!unit)
6427 continue;
6428 unit->die = die;
6429 unit->id = PCI_SLOT(dev->devfn) - PCI_SLOT(devfn);
6430 unit->addr = pci_domain_nr(dev->bus) << UNCORE_DISCOVERY_PCI_DOMAIN_OFFSET |
6431 dev->bus->number << UNCORE_DISCOVERY_PCI_BUS_OFFSET |
6432 devfn << UNCORE_DISCOVERY_PCI_DEVFN_OFFSET |
6433 type->box_ctl;
6434
6435 unit->pmu_idx = unit->id;
6436
6437 uncore_find_add_unit(unit, root, NULL);
6438 }
6439
6440 type->boxes = root;
6441 }
6442
spr_uncore_pci_init(void)6443 int spr_uncore_pci_init(void)
6444 {
6445 int ret = snbep_pci2phy_map_init(0x3250, SKX_CPUNODEID, SKX_GIDNIDMAP, true);
6446
6447 if (ret)
6448 return ret;
6449
6450 /*
6451 * The discovery table of UPI on some SPR variant is broken,
6452 * which impacts the detection of both UPI and M3UPI uncore PMON.
6453 * Use the pre-defined UPI and M3UPI table to replace.
6454 *
6455 * The accurate location, e.g., domain and BUS number,
6456 * can only be retrieved at load time.
6457 * Update the location of UPI and M3UPI.
6458 */
6459 spr_update_device_location(UNCORE_SPR_UPI);
6460 spr_update_device_location(UNCORE_SPR_M3UPI);
6461 uncore_pci_uncores = uncore_get_uncores(UNCORE_ACCESS_PCI,
6462 UNCORE_SPR_PCI_EXTRA_UNCORES,
6463 spr_pci_uncores,
6464 UNCORE_SPR_NUM_UNCORE_TYPES,
6465 spr_uncores);
6466 return 0;
6467 }
6468
spr_uncore_mmio_init(void)6469 void spr_uncore_mmio_init(void)
6470 {
6471 int ret = snbep_pci2phy_map_init(0x3250, SKX_CPUNODEID, SKX_GIDNIDMAP, true);
6472
6473 if (ret) {
6474 uncore_mmio_uncores = uncore_get_uncores(UNCORE_ACCESS_MMIO, 0, NULL,
6475 UNCORE_SPR_NUM_UNCORE_TYPES,
6476 spr_uncores);
6477 } else {
6478 uncore_mmio_uncores = uncore_get_uncores(UNCORE_ACCESS_MMIO,
6479 UNCORE_SPR_MMIO_EXTRA_UNCORES,
6480 spr_mmio_uncores,
6481 UNCORE_SPR_NUM_UNCORE_TYPES,
6482 spr_uncores);
6483
6484 spr_uncore_imc_free_running.num_boxes = uncore_type_max_boxes(uncore_mmio_uncores, UNCORE_SPR_IMC) / 2;
6485 }
6486 }
6487
6488 /* end of SPR uncore support */
6489
6490 /* GNR uncore support */
6491
6492 #define UNCORE_GNR_NUM_UNCORE_TYPES 23
6493
6494 int gnr_uncore_units_ignore[] = {
6495 UNCORE_IGNORE_END
6496 };
6497
6498 static struct intel_uncore_type gnr_uncore_ubox = {
6499 .name = "ubox",
6500 .attr_update = uncore_alias_groups,
6501 };
6502
6503 static struct uncore_event_desc gnr_uncore_imc_events[] = {
6504 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x01,umask=0x00"),
6505 INTEL_UNCORE_EVENT_DESC(cas_count_read_sch0, "event=0x05,umask=0xcf"),
6506 INTEL_UNCORE_EVENT_DESC(cas_count_read_sch0.scale, "6.103515625e-5"),
6507 INTEL_UNCORE_EVENT_DESC(cas_count_read_sch0.unit, "MiB"),
6508 INTEL_UNCORE_EVENT_DESC(cas_count_read_sch1, "event=0x06,umask=0xcf"),
6509 INTEL_UNCORE_EVENT_DESC(cas_count_read_sch1.scale, "6.103515625e-5"),
6510 INTEL_UNCORE_EVENT_DESC(cas_count_read_sch1.unit, "MiB"),
6511 INTEL_UNCORE_EVENT_DESC(cas_count_write_sch0, "event=0x05,umask=0xf0"),
6512 INTEL_UNCORE_EVENT_DESC(cas_count_write_sch0.scale, "6.103515625e-5"),
6513 INTEL_UNCORE_EVENT_DESC(cas_count_write_sch0.unit, "MiB"),
6514 INTEL_UNCORE_EVENT_DESC(cas_count_write_sch1, "event=0x06,umask=0xf0"),
6515 INTEL_UNCORE_EVENT_DESC(cas_count_write_sch1.scale, "6.103515625e-5"),
6516 INTEL_UNCORE_EVENT_DESC(cas_count_write_sch1.unit, "MiB"),
6517 { /* end: all zeroes */ },
6518 };
6519
6520 static struct intel_uncore_type gnr_uncore_imc = {
6521 SPR_UNCORE_MMIO_COMMON_FORMAT(),
6522 .name = "imc",
6523 .fixed_ctr_bits = 48,
6524 .fixed_ctr = SNR_IMC_MMIO_PMON_FIXED_CTR,
6525 .fixed_ctl = SNR_IMC_MMIO_PMON_FIXED_CTL,
6526 .event_descs = gnr_uncore_imc_events,
6527 };
6528
6529 static struct intel_uncore_type gnr_uncore_pciex8 = {
6530 SPR_UNCORE_PCI_COMMON_FORMAT(),
6531 .name = "pciex8",
6532 };
6533
6534 static struct intel_uncore_type gnr_uncore_pciex16 = {
6535 SPR_UNCORE_PCI_COMMON_FORMAT(),
6536 .name = "pciex16",
6537 };
6538
6539 static struct intel_uncore_type gnr_uncore_upi = {
6540 SPR_UNCORE_PCI_COMMON_FORMAT(),
6541 .name = "upi",
6542 };
6543
6544 static struct intel_uncore_type gnr_uncore_b2upi = {
6545 SPR_UNCORE_PCI_COMMON_FORMAT(),
6546 .name = "b2upi",
6547 };
6548
6549 static struct intel_uncore_type gnr_uncore_b2hot = {
6550 .name = "b2hot",
6551 .attr_update = uncore_alias_groups,
6552 };
6553
6554 static struct intel_uncore_type gnr_uncore_b2cmi = {
6555 SPR_UNCORE_PCI_COMMON_FORMAT(),
6556 .name = "b2cmi",
6557 };
6558
6559 static struct intel_uncore_type gnr_uncore_b2cxl = {
6560 SPR_UNCORE_MMIO_OFFS8_COMMON_FORMAT(),
6561 .name = "b2cxl",
6562 };
6563
6564 static struct intel_uncore_type gnr_uncore_mdf_sbo = {
6565 .name = "mdf_sbo",
6566 .attr_update = uncore_alias_groups,
6567 };
6568
6569 static struct intel_uncore_type *gnr_uncores[UNCORE_GNR_NUM_UNCORE_TYPES] = {
6570 &spr_uncore_chabox,
6571 &spr_uncore_iio,
6572 &spr_uncore_irp,
6573 NULL,
6574 &spr_uncore_pcu,
6575 &gnr_uncore_ubox,
6576 &gnr_uncore_imc,
6577 NULL,
6578 &gnr_uncore_upi,
6579 NULL,
6580 NULL,
6581 NULL,
6582 &spr_uncore_cxlcm,
6583 &spr_uncore_cxldp,
6584 NULL,
6585 &gnr_uncore_b2hot,
6586 &gnr_uncore_b2cmi,
6587 &gnr_uncore_b2cxl,
6588 &gnr_uncore_b2upi,
6589 NULL,
6590 &gnr_uncore_mdf_sbo,
6591 &gnr_uncore_pciex16,
6592 &gnr_uncore_pciex8,
6593 };
6594
6595 static struct freerunning_counters gnr_iio_freerunning[] = {
6596 [SPR_IIO_MSR_IOCLK] = { 0x290e, 0x01, 0x10, 1, 48 },
6597 [SPR_IIO_MSR_BW_IN] = { 0x360e, 0x10, 0x80, 8, 48 },
6598 [SPR_IIO_MSR_BW_OUT] = { 0x2e0e, 0x10, 0x80, 8, 48 },
6599 };
6600
gnr_uncore_cpu_init(void)6601 void gnr_uncore_cpu_init(void)
6602 {
6603 uncore_msr_uncores = uncore_get_uncores(UNCORE_ACCESS_MSR,
6604 UNCORE_SPR_MSR_EXTRA_UNCORES,
6605 spr_msr_uncores,
6606 UNCORE_GNR_NUM_UNCORE_TYPES,
6607 gnr_uncores);
6608 spr_uncore_iio_free_running.num_boxes = uncore_type_max_boxes(uncore_msr_uncores, UNCORE_SPR_IIO);
6609 spr_uncore_iio_free_running.freerunning = gnr_iio_freerunning;
6610 }
6611
gnr_uncore_pci_init(void)6612 int gnr_uncore_pci_init(void)
6613 {
6614 uncore_pci_uncores = uncore_get_uncores(UNCORE_ACCESS_PCI, 0, NULL,
6615 UNCORE_GNR_NUM_UNCORE_TYPES,
6616 gnr_uncores);
6617 return 0;
6618 }
6619
gnr_uncore_mmio_init(void)6620 void gnr_uncore_mmio_init(void)
6621 {
6622 uncore_mmio_uncores = uncore_get_uncores(UNCORE_ACCESS_MMIO, 0, NULL,
6623 UNCORE_GNR_NUM_UNCORE_TYPES,
6624 gnr_uncores);
6625 }
6626
6627 /* end of GNR uncore support */
6628
6629 /* DMR uncore support */
6630 #define UNCORE_DMR_NUM_UNCORE_TYPES 52
6631
6632 static struct attribute *dmr_imc_uncore_formats_attr[] = {
6633 &format_attr_event.attr,
6634 &format_attr_umask.attr,
6635 &format_attr_edge.attr,
6636 &format_attr_inv.attr,
6637 &format_attr_thresh10.attr,
6638 NULL,
6639 };
6640
6641 static const struct attribute_group dmr_imc_uncore_format_group = {
6642 .name = "format",
6643 .attrs = dmr_imc_uncore_formats_attr,
6644 };
6645
6646 static struct intel_uncore_type dmr_uncore_imc = {
6647 .name = "imc",
6648 .fixed_ctr_bits = 48,
6649 .fixed_ctr = DMR_IMC_PMON_FIXED_CTR,
6650 .fixed_ctl = DMR_IMC_PMON_FIXED_CTL,
6651 .ops = &spr_uncore_mmio_ops,
6652 .format_group = &dmr_imc_uncore_format_group,
6653 .attr_update = uncore_alias_groups,
6654 };
6655
6656 static struct attribute *dmr_sca_uncore_formats_attr[] = {
6657 &format_attr_event.attr,
6658 &format_attr_umask_ext5.attr,
6659 &format_attr_edge.attr,
6660 &format_attr_inv.attr,
6661 &format_attr_thresh8.attr,
6662 NULL,
6663 };
6664
6665 static const struct attribute_group dmr_sca_uncore_format_group = {
6666 .name = "format",
6667 .attrs = dmr_sca_uncore_formats_attr,
6668 };
6669
6670 static struct intel_uncore_type dmr_uncore_sca = {
6671 .name = "sca",
6672 .event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
6673 .format_group = &dmr_sca_uncore_format_group,
6674 .attr_update = uncore_alias_groups,
6675 };
6676
6677 static struct attribute *dmr_cxlcm_uncore_formats_attr[] = {
6678 &format_attr_event.attr,
6679 &format_attr_umask.attr,
6680 &format_attr_edge.attr,
6681 &format_attr_inv2.attr,
6682 &format_attr_thresh9_2.attr,
6683 &format_attr_port_en.attr,
6684 NULL,
6685 };
6686
6687 static const struct attribute_group dmr_cxlcm_uncore_format_group = {
6688 .name = "format",
6689 .attrs = dmr_cxlcm_uncore_formats_attr,
6690 };
6691
6692 static struct event_constraint dmr_uncore_cxlcm_constraints[] = {
6693 UNCORE_EVENT_CONSTRAINT_RANGE(0x1, 0x24, 0x0f),
6694 UNCORE_EVENT_CONSTRAINT_RANGE(0x41, 0x41, 0xf0),
6695 UNCORE_EVENT_CONSTRAINT_RANGE(0x50, 0x5e, 0xf0),
6696 UNCORE_EVENT_CONSTRAINT_RANGE(0x60, 0x61, 0xf0),
6697 EVENT_CONSTRAINT_END
6698 };
6699
6700 static struct intel_uncore_type dmr_uncore_cxlcm = {
6701 .name = "cxlcm",
6702 .event_mask = DMR_CXLCM_PMON_RAW_EVENT_MASK,
6703 .event_mask_ext = DMR_CXLCM_EVENT_MASK_EXT,
6704 .constraints = dmr_uncore_cxlcm_constraints,
6705 .format_group = &dmr_cxlcm_uncore_format_group,
6706 .attr_update = uncore_alias_groups,
6707 };
6708
6709 static struct intel_uncore_type dmr_uncore_hamvf = {
6710 .name = "hamvf",
6711 .event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
6712 .format_group = &dmr_sca_uncore_format_group,
6713 .attr_update = uncore_alias_groups,
6714 };
6715
6716 static struct event_constraint dmr_uncore_cbo_constraints[] = {
6717 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
6718 UNCORE_EVENT_CONSTRAINT_RANGE(0x19, 0x1a, 0x1),
6719 UNCORE_EVENT_CONSTRAINT(0x1f, 0x1),
6720 UNCORE_EVENT_CONSTRAINT(0x21, 0x1),
6721 UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
6722 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
6723 EVENT_CONSTRAINT_END
6724 };
6725
6726 static struct intel_uncore_type dmr_uncore_cbo = {
6727 .name = "cbo",
6728 .event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
6729 .constraints = dmr_uncore_cbo_constraints,
6730 .format_group = &dmr_sca_uncore_format_group,
6731 .attr_update = uncore_alias_groups,
6732 };
6733
6734 static struct intel_uncore_type dmr_uncore_santa = {
6735 .name = "santa",
6736 .attr_update = uncore_alias_groups,
6737 };
6738
6739 static struct intel_uncore_type dmr_uncore_cncu = {
6740 .name = "cncu",
6741 .attr_update = uncore_alias_groups,
6742 };
6743
6744 static struct intel_uncore_type dmr_uncore_sncu = {
6745 .name = "sncu",
6746 .attr_update = uncore_alias_groups,
6747 };
6748
6749 static struct intel_uncore_type dmr_uncore_ula = {
6750 .name = "ula",
6751 .event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
6752 .format_group = &dmr_sca_uncore_format_group,
6753 .attr_update = uncore_alias_groups,
6754 };
6755
6756 static struct intel_uncore_type dmr_uncore_dda = {
6757 .name = "dda",
6758 .event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
6759 .format_group = &dmr_sca_uncore_format_group,
6760 .attr_update = uncore_alias_groups,
6761 };
6762
6763 static struct event_constraint dmr_uncore_sbo_constraints[] = {
6764 UNCORE_EVENT_CONSTRAINT(0x1f, 0x01),
6765 UNCORE_EVENT_CONSTRAINT(0x25, 0x01),
6766 EVENT_CONSTRAINT_END
6767 };
6768
6769 static struct intel_uncore_type dmr_uncore_sbo = {
6770 .name = "sbo",
6771 .event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
6772 .constraints = dmr_uncore_sbo_constraints,
6773 .format_group = &dmr_sca_uncore_format_group,
6774 .attr_update = uncore_alias_groups,
6775 };
6776
6777 static struct intel_uncore_type dmr_uncore_ubr = {
6778 .name = "ubr",
6779 .event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
6780 .format_group = &dmr_sca_uncore_format_group,
6781 .attr_update = uncore_alias_groups,
6782 };
6783
6784 static struct attribute *dmr_pcie4_uncore_formats_attr[] = {
6785 &format_attr_event.attr,
6786 &format_attr_umask.attr,
6787 &format_attr_edge.attr,
6788 &format_attr_inv.attr,
6789 &format_attr_thresh8.attr,
6790 &format_attr_thresh_ext.attr,
6791 &format_attr_rs3_sel.attr,
6792 &format_attr_rx_sel.attr,
6793 &format_attr_tx_sel.attr,
6794 &format_attr_iep_sel.attr,
6795 &format_attr_vc_sel.attr,
6796 &format_attr_port_sel.attr,
6797 NULL,
6798 };
6799
6800 static const struct attribute_group dmr_pcie4_uncore_format_group = {
6801 .name = "format",
6802 .attrs = dmr_pcie4_uncore_formats_attr,
6803 };
6804
6805 static struct intel_uncore_type dmr_uncore_pcie4 = {
6806 .name = "pcie4",
6807 .event_mask_ext = DMR_PCIE4_EVENT_MASK_EXT,
6808 .format_group = &dmr_pcie4_uncore_format_group,
6809 .attr_update = uncore_alias_groups,
6810 };
6811
6812 static struct intel_uncore_type dmr_uncore_crs = {
6813 .name = "crs",
6814 .attr_update = uncore_alias_groups,
6815 };
6816
6817 static struct intel_uncore_type dmr_uncore_cpc = {
6818 .name = "cpc",
6819 .event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
6820 .format_group = &dmr_sca_uncore_format_group,
6821 .attr_update = uncore_alias_groups,
6822 };
6823
6824 static struct intel_uncore_type dmr_uncore_itc = {
6825 .name = "itc",
6826 .event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
6827 .format_group = &dmr_sca_uncore_format_group,
6828 .attr_update = uncore_alias_groups,
6829 };
6830
6831 static struct intel_uncore_type dmr_uncore_otc = {
6832 .name = "otc",
6833 .event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
6834 .format_group = &dmr_sca_uncore_format_group,
6835 .attr_update = uncore_alias_groups,
6836 };
6837
6838 static struct intel_uncore_type dmr_uncore_cms = {
6839 .name = "cms",
6840 .attr_update = uncore_alias_groups,
6841 };
6842
6843 static struct intel_uncore_type dmr_uncore_pcie6 = {
6844 .name = "pcie6",
6845 .event_mask_ext = DMR_PCIE4_EVENT_MASK_EXT,
6846 .format_group = &dmr_pcie4_uncore_format_group,
6847 .attr_update = uncore_alias_groups,
6848 };
6849
6850 static struct intel_uncore_type *dmr_uncores[UNCORE_DMR_NUM_UNCORE_TYPES] = {
6851 NULL, NULL, NULL, NULL,
6852 &spr_uncore_pcu,
6853 &gnr_uncore_ubox,
6854 &dmr_uncore_imc,
6855 NULL,
6856 NULL, NULL, NULL, NULL,
6857 NULL, NULL, NULL, NULL,
6858 NULL, NULL, NULL, NULL,
6859 NULL, NULL, NULL,
6860 &dmr_uncore_sca,
6861 &dmr_uncore_cxlcm,
6862 NULL, NULL, NULL,
6863 NULL, NULL,
6864 &dmr_uncore_hamvf,
6865 &dmr_uncore_cbo,
6866 &dmr_uncore_santa,
6867 &dmr_uncore_cncu,
6868 &dmr_uncore_sncu,
6869 &dmr_uncore_ula,
6870 &dmr_uncore_dda,
6871 NULL,
6872 &dmr_uncore_sbo,
6873 NULL,
6874 NULL, NULL, NULL,
6875 &dmr_uncore_ubr,
6876 NULL,
6877 &dmr_uncore_pcie4,
6878 &dmr_uncore_crs,
6879 &dmr_uncore_cpc,
6880 &dmr_uncore_itc,
6881 &dmr_uncore_otc,
6882 &dmr_uncore_cms,
6883 &dmr_uncore_pcie6,
6884 };
6885
6886 int dmr_uncore_imh_units_ignore[] = {
6887 0x13, /* MSE */
6888 UNCORE_IGNORE_END
6889 };
6890
6891 int dmr_uncore_cbb_units_ignore[] = {
6892 0x25, /* SB2UCIE */
6893 UNCORE_IGNORE_END
6894 };
6895
6896 static unsigned int dmr_iio_freerunning_box_offsets[] = {
6897 0x0, 0x8000, 0x18000, 0x20000
6898 };
6899
dmr_uncore_freerunning_init_box(struct intel_uncore_box * box)6900 static int dmr_uncore_freerunning_init_box(struct intel_uncore_box *box)
6901 {
6902 struct intel_uncore_type *type = box->pmu->type;
6903 u64 mmio_base;
6904
6905 if (box->pmu->pmu_idx >= type->num_boxes)
6906 return -ENODEV;
6907
6908 mmio_base = DMR_IMH1_HIOP_MMIO_BASE;
6909 mmio_base += dmr_iio_freerunning_box_offsets[box->pmu->pmu_idx];
6910
6911 box->io_addr = ioremap(mmio_base, type->mmio_map_size);
6912 if (!box->io_addr) {
6913 pr_warn("perf uncore: Failed to ioremap for %s.\n", type->name);
6914 return -ENOMEM;
6915 }
6916
6917 return 0;
6918 }
6919
6920 static struct intel_uncore_ops dmr_uncore_freerunning_ops = {
6921 .init_box = dmr_uncore_freerunning_init_box,
6922 .exit_box = uncore_mmio_exit_box,
6923 .read_counter = uncore_mmio_read_counter,
6924 .hw_config = uncore_freerunning_hw_config,
6925 };
6926
6927 enum perf_uncore_dmr_iio_freerunning_type_id {
6928 DMR_ITC_INB_DATA_BW,
6929 DMR_ITC_BW_IN,
6930 DMR_OTC_BW_OUT,
6931 DMR_OTC_CLOCK_TICKS,
6932
6933 DMR_IIO_FREERUNNING_TYPE_MAX,
6934 };
6935
6936 static struct freerunning_counters dmr_iio_freerunning[] = {
6937 [DMR_ITC_INB_DATA_BW] = { 0x4d40, 0x8, 0, 8, 48},
6938 [DMR_ITC_BW_IN] = { 0x6b00, 0x8, 0, 8, 48},
6939 [DMR_OTC_BW_OUT] = { 0x6b60, 0x8, 0, 8, 48},
6940 [DMR_OTC_CLOCK_TICKS] = { 0x6bb0, 0x8, 0, 1, 48},
6941 };
6942
6943 static struct uncore_event_desc dmr_uncore_iio_freerunning_events[] = {
6944 /* ITC Free Running Data BW counter for inbound traffic */
6945 INTEL_UNCORE_FR_EVENT_DESC(inb_data_port0, 0x10, 3.814697266e-6),
6946 INTEL_UNCORE_FR_EVENT_DESC(inb_data_port1, 0x11, 3.814697266e-6),
6947 INTEL_UNCORE_FR_EVENT_DESC(inb_data_port2, 0x12, 3.814697266e-6),
6948 INTEL_UNCORE_FR_EVENT_DESC(inb_data_port3, 0x13, 3.814697266e-6),
6949 INTEL_UNCORE_FR_EVENT_DESC(inb_data_port4, 0x14, 3.814697266e-6),
6950 INTEL_UNCORE_FR_EVENT_DESC(inb_data_port5, 0x15, 3.814697266e-6),
6951 INTEL_UNCORE_FR_EVENT_DESC(inb_data_port6, 0x16, 3.814697266e-6),
6952 INTEL_UNCORE_FR_EVENT_DESC(inb_data_port7, 0x17, 3.814697266e-6),
6953
6954 /* ITC Free Running BW IN counters */
6955 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port0, 0x20, 3.814697266e-6),
6956 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port1, 0x21, 3.814697266e-6),
6957 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port2, 0x22, 3.814697266e-6),
6958 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port3, 0x23, 3.814697266e-6),
6959 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port4, 0x24, 3.814697266e-6),
6960 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port5, 0x25, 3.814697266e-6),
6961 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port6, 0x26, 3.814697266e-6),
6962 INTEL_UNCORE_FR_EVENT_DESC(bw_in_port7, 0x27, 3.814697266e-6),
6963
6964 /* ITC Free Running BW OUT counters */
6965 INTEL_UNCORE_FR_EVENT_DESC(bw_out_port0, 0x30, 3.814697266e-6),
6966 INTEL_UNCORE_FR_EVENT_DESC(bw_out_port1, 0x31, 3.814697266e-6),
6967 INTEL_UNCORE_FR_EVENT_DESC(bw_out_port2, 0x32, 3.814697266e-6),
6968 INTEL_UNCORE_FR_EVENT_DESC(bw_out_port3, 0x33, 3.814697266e-6),
6969 INTEL_UNCORE_FR_EVENT_DESC(bw_out_port4, 0x34, 3.814697266e-6),
6970 INTEL_UNCORE_FR_EVENT_DESC(bw_out_port5, 0x35, 3.814697266e-6),
6971 INTEL_UNCORE_FR_EVENT_DESC(bw_out_port6, 0x36, 3.814697266e-6),
6972 INTEL_UNCORE_FR_EVENT_DESC(bw_out_port7, 0x37, 3.814697266e-6),
6973
6974 /* Free Running Clock Counter */
6975 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x40"),
6976 { /* end: all zeroes */ },
6977 };
6978
6979 static struct intel_uncore_type dmr_uncore_iio_free_running = {
6980 .name = "iio_free_running",
6981 .num_counters = 25,
6982 .mmio_map_size = DMR_HIOP_MMIO_SIZE,
6983 .num_freerunning_types = DMR_IIO_FREERUNNING_TYPE_MAX,
6984 .freerunning = dmr_iio_freerunning,
6985 .ops = &dmr_uncore_freerunning_ops,
6986 .event_descs = dmr_uncore_iio_freerunning_events,
6987 .format_group = &skx_uncore_iio_freerunning_format_group,
6988 };
6989
6990 #define UNCORE_DMR_MMIO_EXTRA_UNCORES 1
6991 static struct intel_uncore_type *dmr_mmio_uncores[UNCORE_DMR_MMIO_EXTRA_UNCORES] = {
6992 &dmr_uncore_iio_free_running,
6993 };
6994
dmr_uncore_pci_init(void)6995 int dmr_uncore_pci_init(void)
6996 {
6997 uncore_pci_uncores = uncore_get_uncores(UNCORE_ACCESS_PCI, 0, NULL,
6998 UNCORE_DMR_NUM_UNCORE_TYPES,
6999 dmr_uncores);
7000 return 0;
7001 }
7002
dmr_uncore_mmio_init(void)7003 void dmr_uncore_mmio_init(void)
7004 {
7005 uncore_mmio_uncores = uncore_get_uncores(UNCORE_ACCESS_MMIO,
7006 UNCORE_DMR_MMIO_EXTRA_UNCORES,
7007 dmr_mmio_uncores,
7008 UNCORE_DMR_NUM_UNCORE_TYPES,
7009 dmr_uncores);
7010
7011 dmr_uncore_iio_free_running.num_boxes =
7012 uncore_type_max_boxes(uncore_mmio_uncores, UNCORE_DMR_ITC);
7013 }
7014 /* end of DMR uncore support */
7015