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Searched refs:ah (Results 1 – 25 of 207) sorted by relevance

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/linux/drivers/net/wireless/ath/ath9k/
H A Dhw.c34 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
40 static void ath9k_hw_set_clockrate(struct ath_hw *ah) in ath9k_hw_set_clockrate() argument
42 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_clockrate()
43 struct ath9k_channel *chan = ah->curchan; in ath9k_hw_set_clockrate()
47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) in ath9k_hw_set_clockrate()
53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) in ath9k_hw_set_clockrate()
70 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) in ath9k_hw_mac_to_clks() argument
72 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_mac_to_clks()
77 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) in ath9k_hw_wait() argument
84 if ((REG_READ(ah, reg) & mask) == val) in ath9k_hw_wait()
[all …]
H A Dhw-ops.h24 static inline void ath9k_hw_configpcipowersave(struct ath_hw *ah, in ath9k_hw_configpcipowersave() argument
27 if (!ah->aspm_enabled) in ath9k_hw_configpcipowersave()
30 ath9k_hw_ops(ah)->config_pci_powersave(ah, power_off); in ath9k_hw_configpcipowersave()
33 static inline void ath9k_hw_rxena(struct ath_hw *ah) in ath9k_hw_rxena() argument
35 ath9k_hw_ops(ah)->rx_enable(ah); in ath9k_hw_rxena()
38 static inline void ath9k_hw_set_desc_link(struct ath_hw *ah, void *ds, in ath9k_hw_set_desc_link() argument
41 ath9k_hw_ops(ah)->set_desc_link(ds, link); in ath9k_hw_set_desc_link()
44 static inline int ath9k_hw_calibrate(struct ath_hw *ah, in ath9k_hw_calibrate() argument
48 return ath9k_hw_ops(ah)->calibrate(ah, chan, rxchainmask, longcal); in ath9k_hw_calibrate()
51 static inline bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked, in ath9k_hw_getisr() argument
[all …]
H A Dar9002_calib.c31 static bool ar9002_hw_is_cal_supported(struct ath_hw *ah, in ar9002_hw_is_cal_supported() argument
36 switch (ah->supp_cals & cal_type) { in ar9002_hw_is_cal_supported()
50 static void ar9002_hw_setup_calibration(struct ath_hw *ah, in ar9002_hw_setup_calibration() argument
53 struct ath_common *common = ath9k_hw_common(ah); in ar9002_hw_setup_calibration()
55 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
61 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); in ar9002_hw_setup_calibration()
66 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); in ar9002_hw_setup_calibration()
70 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); in ar9002_hw_setup_calibration()
75 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
79 static bool ar9002_hw_per_calibration(struct ath_hw *ah, in ar9002_hw_per_calibration() argument
[all …]
H A Dar9003_phy.c149 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) in ar9003_hw_set_channel() argument
156 ath9k_hw_get_channel_centers(ah, chan, &centers); in ar9003_hw_set_channel()
160 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || in ar9003_hw_set_channel()
161 AR_SREV_9531(ah) || AR_SREV_9550(ah) || in ar9003_hw_set_channel()
162 AR_SREV_9561(ah) || AR_SREV_9565(ah)) { in ar9003_hw_set_channel()
163 if (ah->is_clk_25mhz) in ar9003_hw_set_channel()
171 } else if (AR_SREV_9340(ah)) { in ar9003_hw_set_channel()
172 if (ah->is_clk_25mhz) { in ar9003_hw_set_channel()
185 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) || in ar9003_hw_set_channel()
186 AR_SREV_9531(ah) || AR_SREV_9561(ah)) && in ar9003_hw_set_channel()
[all …]
H A Dani.c107 static void ath9k_hw_update_mibstats(struct ath_hw *ah, in ath9k_hw_update_mibstats() argument
114 REG_READ_MULTI(ah, &addr[0], &data[0], 5); in ath9k_hw_update_mibstats()
127 static void ath9k_ani_restart(struct ath_hw *ah) in ath9k_ani_restart() argument
129 struct ar5416AniState *aniState = &ah->ani; in ath9k_ani_restart()
133 ENABLE_REGWRITE_BUFFER(ah); in ath9k_ani_restart()
135 REG_WRITE(ah, AR_PHY_ERR_1, 0); in ath9k_ani_restart()
136 REG_WRITE(ah, AR_PHY_ERR_2, 0); in ath9k_ani_restart()
137 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); in ath9k_ani_restart()
138 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); in ath9k_ani_restart()
140 REGWRITE_BUFFER_FLUSH(ah); in ath9k_ani_restart()
[all …]
H A Dmac.c21 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, in ath9k_hw_set_txq_interrupts() argument
24 ath_dbg(ath9k_hw_common(ah), INTERRUPT, in ath9k_hw_set_txq_interrupts()
26 ah->txok_interrupt_mask, ah->txerr_interrupt_mask, in ath9k_hw_set_txq_interrupts()
27 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, in ath9k_hw_set_txq_interrupts()
28 ah->txurn_interrupt_mask); in ath9k_hw_set_txq_interrupts()
30 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_txq_interrupts()
32 REG_WRITE(ah, AR_IMR_S0, in ath9k_hw_set_txq_interrupts()
33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) in ath9k_hw_set_txq_interrupts()
34 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC)); in ath9k_hw_set_txq_interrupts()
35 REG_WRITE(ah, AR_IMR_S1, in ath9k_hw_set_txq_interrupts()
[all …]
H A Dar9003_wow.c23 static void ath9k_hw_set_sta_powersave(struct ath_hw *ah) in ath9k_hw_set_sta_powersave() argument
25 if (!ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_set_sta_powersave()
31 if (ar9003_mci_state(ah, MCI_STATE_GET_WLAN_PS_STATE) != MCI_PS_DISABLE) in ath9k_hw_set_sta_powersave()
34 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_hw_set_sta_powersave()
37 static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah) in ath9k_hw_set_powermode_wow_sleep() argument
39 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_powermode_wow_sleep()
41 ath9k_hw_set_sta_powersave(ah); in ath9k_hw_set_powermode_wow_sleep()
44 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ath9k_hw_set_powermode_wow_sleep()
46 if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE(ah), 0, AH_WAIT_TIMEOUT)) { in ath9k_hw_set_powermode_wow_sleep()
48 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); in ath9k_hw_set_powermode_wow_sleep()
[all …]
H A Dar5008_phy.c89 static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt) in ar5008_write_bank6() argument
91 struct ar5416IniArray *array = &ah->iniBank6; in ar5008_write_bank6()
92 u32 *data = ah->analogBank6Data; in ar5008_write_bank6()
95 ENABLE_REGWRITE_BUFFER(ah); in ar5008_write_bank6()
98 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); in ar5008_write_bank6()
102 REGWRITE_BUFFER_FLUSH(ah); in ar5008_write_bank6()
164 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) in ar5008_hw_force_bias() argument
166 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_force_bias()
171 if (!AR_SREV_5416(ah) || synth_freq >= 3000) in ar5008_hw_force_bias()
174 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); in ar5008_hw_force_bias()
[all …]
H A Dar9003_calib.c38 static void ar9003_hw_setup_calibration(struct ath_hw *ah, in ar9003_hw_setup_calibration() argument
41 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_setup_calibration()
50 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_setup_calibration()
53 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); in ar9003_hw_setup_calibration()
59 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); in ar9003_hw_setup_calibration()
72 static bool ar9003_hw_per_calibration(struct ath_hw *ah, in ar9003_hw_per_calibration() argument
77 struct ath9k_hw_cal_data *caldata = ah->caldata; in ar9003_hw_per_calibration()
83 if (REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL) in ar9003_hw_per_calibration()
89 cur_caldata->calCollect(ah); in ar9003_hw_per_calibration()
90 ah->cal_samples++; in ar9003_hw_per_calibration()
[all …]
H A Dar9002_phy.c66 static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) in ar9002_hw_set_channel() argument
73 ath9k_hw_get_channel_centers(ah, chan, &centers); in ar9002_hw_set_channel()
76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9002_hw_set_channel()
88 if (AR_SREV_9287_11_OR_LATER(ah)) { in ar9002_hw_set_channel()
91 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484, in ar9002_hw_set_channel()
94 REG_WRITE_ARRAY(&ah->iniCckfirNormal, in ar9002_hw_set_channel()
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar9002_hw_set_channel()
101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
112 switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) { in ar9002_hw_set_channel()
[all …]
H A Dar9003_rtt.c38 void ar9003_hw_rtt_enable(struct ath_hw *ah) in ar9003_hw_rtt_enable() argument
40 REG_WRITE(ah, AR_PHY_RTT_CTRL, 1); in ar9003_hw_rtt_enable()
43 void ar9003_hw_rtt_disable(struct ath_hw *ah) in ar9003_hw_rtt_disable() argument
45 REG_WRITE(ah, AR_PHY_RTT_CTRL, 0); in ar9003_hw_rtt_disable()
48 void ar9003_hw_rtt_set_mask(struct ath_hw *ah, u32 rtt_mask) in ar9003_hw_rtt_set_mask() argument
50 REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL, in ar9003_hw_rtt_set_mask()
54 bool ar9003_hw_rtt_force_restore(struct ath_hw *ah) in ar9003_hw_rtt_force_restore() argument
56 if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL, in ar9003_hw_rtt_force_restore()
61 REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL, in ar9003_hw_rtt_force_restore()
64 if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL, in ar9003_hw_rtt_force_restore()
[all …]
H A Dar9003_paprd.c21 void ar9003_paprd_enable(struct ath_hw *ah, bool val) in ar9003_paprd_enable() argument
23 struct ath9k_channel *chan = ah->curchan; in ar9003_paprd_enable()
41 if (ar9003_get_paprd_rate_mask_ht20(ah, is2ghz) in ar9003_paprd_enable()
45 if (ar9003_get_paprd_rate_mask_ht20(ah, is2ghz) in ar9003_paprd_enable()
49 if (ar9003_get_paprd_rate_mask_ht20(ah, is2ghz) in ar9003_paprd_enable()
56 ah->paprd_table_write_done = true; in ar9003_paprd_enable()
57 ath9k_hw_apply_txpower(ah, chan, false); in ar9003_paprd_enable()
60 REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0, in ar9003_paprd_enable()
62 if (ah->caps.tx_chainmask & BIT(1)) in ar9003_paprd_enable()
63 REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B1, in ar9003_paprd_enable()
[all …]
H A Deeprom_def.c21 static void ath9k_get_txgain_index(struct ath_hw *ah, in ath9k_get_txgain_index() argument
31 ath9k_hw_get_channel_centers(ah, chan, &centers); in ath9k_get_txgain_index()
49 while (pcdac > ah->originalGain[i] && in ath9k_get_txgain_index()
56 static void ath9k_olc_get_pdadcs(struct ath_hw *ah, in ath9k_olc_get_pdadcs() argument
64 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0, in ath9k_olc_get_pdadcs()
66 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1, in ath9k_olc_get_pdadcs()
69 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7, in ath9k_olc_get_pdadcs()
80 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah) in ath9k_hw_def_get_eeprom_ver() argument
82 u16 version = le16_to_cpu(ah->eeprom.def.baseEepHeader.version); in ath9k_hw_def_get_eeprom_ver()
88 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah) in ath9k_hw_def_get_eeprom_rev() argument
[all …]
/linux/drivers/net/wireless/ath/ath5k/
H A Dattach.c35 static int ath5k_hw_post(struct ath5k_hw *ah) in ath5k_hw_post() argument
54 init_val = ath5k_hw_reg_read(ah, cur_reg); in ath5k_hw_post()
58 ath5k_hw_reg_write(ah, var_pattern, cur_reg); in ath5k_hw_post()
59 cur_val = ath5k_hw_reg_read(ah, cur_reg); in ath5k_hw_post()
62 ATH5K_ERR(ah, "POST Failed !!!\n"); in ath5k_hw_post()
68 ath5k_hw_reg_write(ah, var_pattern, cur_reg); in ath5k_hw_post()
73 ath5k_hw_reg_write(ah, var_pattern, cur_reg); in ath5k_hw_post()
74 cur_val = ath5k_hw_reg_read(ah, cur_reg); in ath5k_hw_post()
77 ATH5K_ERR(ah, "POST Failed !!!\n"); in ath5k_hw_post()
83 ath5k_hw_reg_write(ah, var_pattern, cur_reg); in ath5k_hw_post()
[all …]
H A Dreset.c67 ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, in ath5k_hw_register_timeout() argument
74 data = ath5k_hw_reg_read(ah, reg); in ath5k_hw_register_timeout()
101 ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec) in ath5k_hw_htoclock() argument
103 struct ath_common *common = ath5k_hw_common(ah); in ath5k_hw_htoclock()
118 ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock) in ath5k_hw_clocktoh() argument
120 struct ath_common *common = ath5k_hw_common(ah); in ath5k_hw_clocktoh()
132 ath5k_hw_init_core_clock(struct ath5k_hw *ah) in ath5k_hw_init_core_clock() argument
134 struct ieee80211_channel *channel = ah->ah_current_channel; in ath5k_hw_init_core_clock()
135 struct ath_common *common = ath5k_hw_common(ah); in ath5k_hw_init_core_clock()
156 switch (ah->ah_bwmode) { in ath5k_hw_init_core_clock()
[all …]
H A Dani.c66 ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level) in ath5k_ani_set_noise_immunity_level() argument
86 ATH5K_ERR(ah, "noise immunity level %d out of range", in ath5k_ani_set_noise_immunity_level()
91 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, in ath5k_ani_set_noise_immunity_level()
93 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_AGCCOARSE, in ath5k_ani_set_noise_immunity_level()
95 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_AGCCOARSE, in ath5k_ani_set_noise_immunity_level()
97 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG, in ath5k_ani_set_noise_immunity_level()
100 ah->ani_state.noise_imm_level = level; in ath5k_ani_set_noise_immunity_level()
101 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level); in ath5k_ani_set_noise_immunity_level()
111 ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level) in ath5k_ani_set_spur_immunity_level() argument
116 level > ah->ani_state.max_spur_level) { in ath5k_ani_set_spur_immunity_level()
[all …]
H A Dbase.c96 static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
200 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) in ath5k_extend_tsf() argument
202 u64 tsf = ath5k_hw_get_tsf64(ah); in ath5k_extend_tsf()
233 struct ath5k_hw *ah = hw_priv; in ath5k_ioread32() local
234 return ath5k_hw_reg_read(ah, reg_offset); in ath5k_ioread32()
239 struct ath5k_hw *ah = hw_priv; in ath5k_iowrite32() local
240 ath5k_hw_reg_write(ah, val, reg_offset); in ath5k_iowrite32()
256 struct ath5k_hw *ah = hw->priv; in ath5k_reg_notifier() local
257 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); in ath5k_reg_notifier()
295 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels, in ath5k_setup_channels() argument
[all …]
H A Dpcu.c114 ath5k_hw_get_frame_duration(struct ath5k_hw *ah, enum nl80211_band band, in ath5k_hw_get_frame_duration() argument
122 if (!ah->ah_bwmode) { in ath5k_hw_get_frame_duration()
123 __le16 raw_dur = ieee80211_generic_frame_duration(ah->hw, in ath5k_hw_get_frame_duration()
139 switch (ah->ah_bwmode) { in ath5k_hw_get_frame_duration()
176 ath5k_hw_get_default_slottime(struct ath5k_hw *ah) in ath5k_hw_get_default_slottime() argument
178 struct ieee80211_channel *channel = ah->ah_current_channel; in ath5k_hw_get_default_slottime()
181 switch (ah->ah_bwmode) { in ath5k_hw_get_default_slottime()
194 if ((channel->hw_value == AR5K_MODE_11B) && !ah->ah_short_slot) in ath5k_hw_get_default_slottime()
207 ath5k_hw_get_default_sifs(struct ath5k_hw *ah) in ath5k_hw_get_default_sifs() argument
209 struct ieee80211_channel *channel = ah->ah_current_channel; in ath5k_hw_get_default_sifs()
[all …]
H A Dqcu.c63 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue) in ath5k_hw_num_tx_pending() argument
66 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); in ath5k_hw_num_tx_pending()
69 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) in ath5k_hw_num_tx_pending()
73 if (ah->ah_version == AR5K_AR5210) in ath5k_hw_num_tx_pending()
76 pending = ath5k_hw_reg_read(ah, AR5K_QUEUE_STATUS(queue)); in ath5k_hw_num_tx_pending()
82 if (!pending && AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue)) in ath5k_hw_num_tx_pending()
94 ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue) in ath5k_hw_release_tx_queue() argument
96 if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num)) in ath5k_hw_release_tx_queue()
100 ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE; in ath5k_hw_release_tx_queue()
102 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue); in ath5k_hw_release_tx_queue()
[all …]
H A Dphy.c85 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum nl80211_band band) in ath5k_hw_radio_revision() argument
96 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
99 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
108 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); in ath5k_hw_radio_revision()
111 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); in ath5k_hw_radio_revision()
113 if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_radio_revision()
114 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(256)) >> 28) & 0xf; in ath5k_hw_radio_revision()
117 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; in ath5k_hw_radio_revision()
123 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
137 ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel) in ath5k_channel_ok() argument
[all …]
H A Ddma.c48 ath5k_hw_start_rx_dma(struct ath5k_hw *ah) in ath5k_hw_start_rx_dma() argument
50 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR); in ath5k_hw_start_rx_dma()
51 ath5k_hw_reg_read(ah, AR5K_CR); in ath5k_hw_start_rx_dma()
59 ath5k_hw_stop_rx_dma(struct ath5k_hw *ah) in ath5k_hw_stop_rx_dma() argument
63 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR); in ath5k_hw_stop_rx_dma()
69 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0; in ath5k_hw_stop_rx_dma()
74 ATH5K_DBG(ah, ATH5K_DEBUG_DMA, in ath5k_hw_stop_rx_dma()
85 ath5k_hw_get_rxdp(struct ath5k_hw *ah) in ath5k_hw_get_rxdp() argument
87 return ath5k_hw_reg_read(ah, AR5K_RXDP); in ath5k_hw_get_rxdp()
98 ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr) in ath5k_hw_set_rxdp() argument
[all …]
H A Drfkill.c39 static inline void ath5k_rfkill_disable(struct ath5k_hw *ah) in ath5k_rfkill_disable() argument
41 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "rfkill disable (gpio:%d polarity:%d)\n", in ath5k_rfkill_disable()
42 ah->rf_kill.gpio, ah->rf_kill.polarity); in ath5k_rfkill_disable()
43 ath5k_hw_set_gpio_output(ah, ah->rf_kill.gpio); in ath5k_rfkill_disable()
44 ath5k_hw_set_gpio(ah, ah->rf_kill.gpio, !ah->rf_kill.polarity); in ath5k_rfkill_disable()
48 static inline void ath5k_rfkill_enable(struct ath5k_hw *ah) in ath5k_rfkill_enable() argument
50 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "rfkill enable (gpio:%d polarity:%d)\n", in ath5k_rfkill_enable()
51 ah->rf_kill.gpio, ah->rf_kill.polarity); in ath5k_rfkill_enable()
52 ath5k_hw_set_gpio_output(ah, ah->rf_kill.gpio); in ath5k_rfkill_enable()
53 ath5k_hw_set_gpio(ah, ah->rf_kill.gpio, ah->rf_kill.polarity); in ath5k_rfkill_enable()
[all …]
H A Dmac80211-ops.c61 struct ath5k_hw *ah = hw->priv; in ath5k_tx() local
64 if (WARN_ON(qnum >= ah->ah_capabilities.cap_queues.q_tx_num)) { in ath5k_tx()
69 ath5k_tx_queue(hw, skb, &ah->txqs[qnum], control); in ath5k_tx()
76 struct ath5k_hw *ah = hw->priv; in ath5k_add_interface() local
80 mutex_lock(&ah->lock); in ath5k_add_interface()
84 && (ah->num_ap_vifs + ah->num_adhoc_vifs) >= ATH_BCBUF) { in ath5k_add_interface()
94 if (ah->num_adhoc_vifs || in ath5k_add_interface()
95 (ah->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) { in ath5k_add_interface()
96 ATH5K_ERR(ah, "Only one single ad-hoc interface is allowed.\n"); in ath5k_add_interface()
113 ah->nvifs++; in ath5k_add_interface()
[all …]
H A Dled.c90 void ath5k_led_enable(struct ath5k_hw *ah) in ath5k_led_enable() argument
93 test_bit(ATH_STAT_LEDSOFT, ah->status)) { in ath5k_led_enable()
94 ath5k_hw_set_gpio_output(ah, ah->led_pin); in ath5k_led_enable()
95 ath5k_led_off(ah); in ath5k_led_enable()
99 static void ath5k_led_on(struct ath5k_hw *ah) in ath5k_led_on() argument
101 if (!test_bit(ATH_STAT_LEDSOFT, ah->status)) in ath5k_led_on()
103 ath5k_hw_set_gpio(ah, ah->led_pin, ah->led_on); in ath5k_led_on()
106 void ath5k_led_off(struct ath5k_hw *ah) in ath5k_led_off() argument
109 !test_bit(ATH_STAT_LEDSOFT, ah->status)) in ath5k_led_off()
111 ath5k_hw_set_gpio(ah, ah->led_pin, !ah->led_on); in ath5k_led_off()
[all …]
H A Dath5k.h84 _ath5k_printk(const struct ath5k_hw *ah, const char *level,
124 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ argument
125 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
128 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ argument
129 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
132 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ argument
133 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
135 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ argument
136 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
139 #define AR5K_REG_READ_Q(ah, _reg, _queue) \ argument
[all …]

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