Searched refs:aenq (Results 1 – 4 of 4) sorted by relevance
200 struct efa_com_aenq *aenq = &edev->aenq; in efa_com_admin_init_aenq() local210 size = EFA_ASYNC_QUEUE_DEPTH * sizeof(*aenq->entries); in efa_com_admin_init_aenq()211 aenq->entries = dma_alloc_coherent(edev->dmadev, size, &aenq->dma_addr, in efa_com_admin_init_aenq()213 if (!aenq->entries) in efa_com_admin_init_aenq()216 aenq->aenq_handlers = aenq_handlers; in efa_com_admin_init_aenq()217 aenq->depth = EFA_ASYNC_QUEUE_DEPTH; in efa_com_admin_init_aenq()218 aenq->cc = 0; in efa_com_admin_init_aenq()219 aenq->phase = 1; in efa_com_admin_init_aenq()221 addr_low = lower_32_bits(aenq->dma_addr); in efa_com_admin_init_aenq()222 addr_high = upper_32_bits(aenq->dma_addr); in efa_com_admin_init_aenq()[all …]
131 struct ena_com_aenq *aenq = &ena_dev->aenq; in ena_com_admin_init_aenq() local135 ena_dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH; in ena_com_admin_init_aenq()137 aenq->entries = dma_alloc_coherent(ena_dev->dmadev, size, &aenq->dma_addr, GFP_KERNEL); in ena_com_admin_init_aenq()139 if (!aenq->entries) { in ena_com_admin_init_aenq()144 aenq->head = aenq->q_depth; in ena_com_admin_init_aenq()145 aenq->phase = 1; in ena_com_admin_init_aenq()147 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr); in ena_com_admin_init_aenq()148 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr); in ena_com_admin_init_aenq()154 aenq_caps |= ena_dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK; in ena_com_admin_init_aenq()165 aenq->aenq_handlers = aenq_handlers; in ena_com_admin_init_aenq()[all …]
304 struct ena_com_aenq aenq; member347 struct ena_admin_feature_aenq_desc aenq; member
1040 struct ena_admin_feature_aenq_desc aenq; member1075 struct ena_admin_feature_aenq_desc aenq; member