137 	struct ena_com_aenq *aenq = &ena_dev->aenq;  in ena_com_admin_init_aenq()  local
141 	ena_dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;  in ena_com_admin_init_aenq()
143 	aenq->entries = dma_alloc_coherent(ena_dev->dmadev, size, &aenq->dma_addr, GFP_KERNEL);  in ena_com_admin_init_aenq()
145 	if (!aenq->entries) {  in ena_com_admin_init_aenq()
150 	aenq->head = aenq->q_depth;  in ena_com_admin_init_aenq()
151 	aenq->phase = 1;  in ena_com_admin_init_aenq()
153 	addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);  in ena_com_admin_init_aenq()
154 	addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);  in ena_com_admin_init_aenq()
160 	aenq_caps |= ena_dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;  in ena_com_admin_init_aenq()
171 	aenq->aenq_handlers = aenq_handlers;  in ena_com_admin_init_aenq()
1478 	u16 depth = ena_dev->aenq.q_depth;  in ena_com_admin_aenq_enable()
1480 	WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");  in ena_com_admin_aenq_enable()
1502 	if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {  in ena_com_set_aenq_config()
1505 			    get_resp.u.aenq.supported_groups, groups_flag);  in ena_com_set_aenq_config()
1515 	cmd.u.aenq.enabled_groups = groups_flag;  in ena_com_set_aenq_config()
1618 	struct ena_com_aenq *aenq = &ena_dev->aenq;  in ena_com_admin_destroy()  local
1633 	size = ADMIN_AENQ_SIZE(aenq->q_depth);  in ena_com_admin_destroy()
1634 	if (ena_dev->aenq.entries)  in ena_com_admin_destroy()
1635 		dma_free_coherent(ena_dev->dmadev, size, aenq->entries, aenq->dma_addr);  in ena_com_admin_destroy()
1636 	aenq->entries = NULL;  in ena_com_admin_destroy()
2234 	memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,  in ena_com_get_dev_attr_feat()
2235 	       sizeof(get_resp.u.aenq));  in ena_com_get_dev_attr_feat()
2281 	struct ena_aenq_handlers *aenq_handlers = ena_dev->aenq.aenq_handlers;  in ena_com_get_specific_aenq_cb()
2297 	struct ena_com_aenq *aenq  = &ena_dev->aenq;  in ena_com_aenq_intr_handler()  local
2303 	masked_head = aenq->head & (aenq->q_depth - 1);  in ena_com_aenq_intr_handler()
2304 	phase = aenq->phase;  in ena_com_aenq_intr_handler()
2305 	aenq_e = &aenq->entries[masked_head]; /* Get first entry */  in ena_com_aenq_intr_handler()
2330 		if (unlikely(masked_head == aenq->q_depth)) {  in ena_com_aenq_intr_handler()
2334 		aenq_e = &aenq->entries[masked_head];  in ena_com_aenq_intr_handler()
2338 	aenq->head += processed;  in ena_com_aenq_intr_handler()
2339 	aenq->phase = phase;  in ena_com_aenq_intr_handler()
2347 	writel_relaxed((u32)aenq->head, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);  in ena_com_aenq_intr_handler()