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Searched refs:adev (Results 1 – 25 of 620) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_device.c184 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev);
185 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev);
186 static int amdgpu_device_ip_resume_phase3(struct amdgpu_device *adev);
188 static void amdgpu_device_load_switch_state(struct amdgpu_device *adev);
190 static inline bool amdgpu_ip_member_of_hwini(struct amdgpu_device *adev, in amdgpu_ip_member_of_hwini() argument
193 return (adev->init_lvl->hwini_ip_block_mask & (1U << block)) != 0; in amdgpu_ip_member_of_hwini()
196 void amdgpu_set_init_level(struct amdgpu_device *adev, in amdgpu_set_init_level() argument
201 adev->init_lvl = &amdgpu_init_minimal_xgmi; in amdgpu_set_init_level()
204 adev->init_lvl = &amdgpu_init_recovery; in amdgpu_set_init_level()
209 adev->init_lvl = &amdgpu_init_default; in amdgpu_set_init_level()
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H A Damdgpu_acp.c103 struct amdgpu_device *adev = ip_block->adev; in acp_sw_init() local
105 adev->acp.parent = adev->dev; in acp_sw_init()
107 adev->acp.cgs_device = in acp_sw_init()
108 amdgpu_cgs_create_device(adev); in acp_sw_init()
109 if (!adev->acp.cgs_device) in acp_sw_init()
117 struct amdgpu_device *adev = ip_block->adev; in acp_sw_fini() local
119 if (adev->acp.cgs_device) in acp_sw_fini()
120 amdgpu_cgs_destroy_device(adev->acp.cgs_device); in acp_sw_fini()
126 void *adev; member
133 struct amdgpu_device *adev; in acp_poweroff() local
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H A Dgmc_v11_0.c53 static int gmc_v11_0_ecc_interrupt_state(struct amdgpu_device *adev, in gmc_v11_0_ecc_interrupt_state() argument
62 gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev, in gmc_v11_0_vm_fault_interrupt_state() argument
69 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); in gmc_v11_0_vm_fault_interrupt_state()
76 if (!adev->in_s0ix && (adev->in_runpm || adev->in_suspend || in gmc_v11_0_vm_fault_interrupt_state()
77 amdgpu_in_reset(adev))) in gmc_v11_0_vm_fault_interrupt_state()
78 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); in gmc_v11_0_vm_fault_interrupt_state()
82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); in gmc_v11_0_vm_fault_interrupt_state()
89 if (!adev->in_s0ix) in gmc_v11_0_vm_fault_interrupt_state()
90 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); in gmc_v11_0_vm_fault_interrupt_state()
99 static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, in gmc_v11_0_process_interrupt() argument
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H A Dsoc24.c73 static int soc24_query_video_codecs(struct amdgpu_device *adev, bool encode, in soc24_query_video_codecs() argument
76 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) in soc24_query_video_codecs()
79 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in soc24_query_video_codecs()
91 static u32 soc24_get_config_memsize(struct amdgpu_device *adev) in soc24_get_config_memsize() argument
93 return adev->nbio.funcs->get_memsize(adev); in soc24_get_config_memsize()
96 static u32 soc24_get_xclk(struct amdgpu_device *adev) in soc24_get_xclk() argument
98 return adev->clock.spll.reference_freq; in soc24_get_xclk()
101 void soc24_grbm_select(struct amdgpu_device *adev, in soc24_grbm_select() argument
135 static uint32_t soc24_get_register_value(struct amdgpu_device *adev, in soc24_get_register_value() argument
140 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc24_get_register_value()
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H A Damdgpu_bios.c51 static bool check_atom_bios(struct amdgpu_device *adev, size_t size) in check_atom_bios() argument
54 uint8_t *bios = adev->bios; in check_atom_bios()
57 dev_dbg(adev->dev, "VBIOS mem is null or mem size is wrong\n"); in check_atom_bios()
62 dev_dbg(adev->dev, "VBIOS signature incorrect %x %x\n", bios[0], in check_atom_bios()
69 dev_dbg(adev->dev, "Can't locate VBIOS header\n"); in check_atom_bios()
75 dev_dbg(adev->dev, "VBIOS header is broken\n"); in check_atom_bios()
81 dev_dbg(adev->dev, "ATOMBIOS detected\n"); in check_atom_bios()
88 void amdgpu_bios_release(struct amdgpu_device *adev) in amdgpu_bios_release() argument
90 kfree(adev->bios); in amdgpu_bios_release()
91 adev->bios = NULL; in amdgpu_bios_release()
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H A Damdgpu_gfx.c48 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, in amdgpu_gfx_mec_queue_to_bit() argument
53 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
54 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
55 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
61 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, in amdgpu_queue_mask_bit_to_mec_queue() argument
64 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_queue_mask_bit_to_mec_queue()
65 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
66 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
67 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
68 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
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H A Dsoc21.c169 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, in soc21_query_video_codecs() argument
172 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) in soc21_query_video_codecs()
175 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in soc21_query_video_codecs()
180 if (amdgpu_sriov_vf(adev)) { in soc21_query_video_codecs()
181 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || in soc21_query_video_codecs()
182 !amdgpu_sriov_is_av1_support(adev)) { in soc21_query_video_codecs()
194 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) { in soc21_query_video_codecs()
224 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) in soc21_didt_rreg() argument
232 spin_lock_irqsave(&adev->reg.didt.lock, flags); in soc21_didt_rreg()
235 spin_unlock_irqrestore(&adev->reg.didt.lock, flags); in soc21_didt_rreg()
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H A Damdgpu_discovery.c265 static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev, in amdgpu_discovery_get_tmr_info() argument
272 if (!amdgpu_sriov_vf(adev)) { in amdgpu_discovery_get_tmr_info()
298 adev->discovery.size = DISCOVERY_TMR_SIZE; in amdgpu_discovery_get_tmr_info()
300 adev->discovery.offset = (vram_size << 20) - DISCOVERY_TMR_OFFSET; in amdgpu_discovery_get_tmr_info()
302 if (amdgpu_sriov_vf(adev)) { in amdgpu_discovery_get_tmr_info()
303 if (adev->virt.is_dynamic_crit_regn_enabled) { in amdgpu_discovery_get_tmr_info()
304 adev->discovery.offset = in amdgpu_discovery_get_tmr_info()
305 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset; in amdgpu_discovery_get_tmr_info()
306 adev->discovery.size = in amdgpu_discovery_get_tmr_info()
307 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb << 10; in amdgpu_discovery_get_tmr_info()
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H A Damdgpu_irq.c159 void amdgpu_irq_disable_all(struct amdgpu_device *adev) in amdgpu_irq_disable_all() argument
165 spin_lock_irqsave(&adev->irq.lock, irqflags); in amdgpu_irq_disable_all()
167 if (!adev->irq.client[i].sources) in amdgpu_irq_disable_all()
171 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; in amdgpu_irq_disable_all()
177 r = src->funcs->set(adev, src, k, in amdgpu_irq_disable_all()
180 dev_err(adev->dev, in amdgpu_irq_disable_all()
186 spin_unlock_irqrestore(&adev->irq.lock, irqflags); in amdgpu_irq_disable_all()
203 struct amdgpu_device *adev = drm_to_adev(dev); in amdgpu_irq_handler() local
206 ret = amdgpu_ih_process(adev, &adev->irq.ih); in amdgpu_irq_handler()
210 amdgpu_ras_interrupt_fatal_error_handler(adev); in amdgpu_irq_handler()
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H A Damdgpu_jpeg.c36 static void amdgpu_jpeg_reg_dump_fini(struct amdgpu_device *adev);
38 int amdgpu_jpeg_sw_init(struct amdgpu_device *adev) in amdgpu_jpeg_sw_init() argument
42 INIT_DELAYED_WORK(&adev->jpeg.idle_work, amdgpu_jpeg_idle_work_handler); in amdgpu_jpeg_sw_init()
43 mutex_init(&adev->jpeg.jpeg_pg_lock); in amdgpu_jpeg_sw_init()
44 atomic_set(&adev->jpeg.total_submission_cnt, 0); in amdgpu_jpeg_sw_init()
46 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && in amdgpu_jpeg_sw_init()
47 (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG)) in amdgpu_jpeg_sw_init()
48 adev->jpeg.indirect_sram = true; in amdgpu_jpeg_sw_init()
50 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { in amdgpu_jpeg_sw_init()
51 if (adev->jpeg.harvest_config & (1U << i)) in amdgpu_jpeg_sw_init()
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H A Damdgpu_amdkfd.c73 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) in amdgpu_amdkfd_device_probe() argument
75 bool vf = amdgpu_sriov_vf(adev); in amdgpu_amdkfd_device_probe()
80 adev->kfd.dev = kgd2kfd_probe(adev, vf); in amdgpu_amdkfd_device_probe()
96 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, in amdgpu_doorbell_get_kfd_info() argument
105 if (adev->enable_mes) { in amdgpu_doorbell_get_kfd_info()
112 *aperture_base = adev->doorbell.base; in amdgpu_doorbell_get_kfd_info()
115 } else if (adev->doorbell.size > adev->doorbell.num_kernel_doorbells * in amdgpu_doorbell_get_kfd_info()
117 *aperture_base = adev->doorbell.base; in amdgpu_doorbell_get_kfd_info()
118 *aperture_size = adev->doorbell.size; in amdgpu_doorbell_get_kfd_info()
119 *start_offset = adev->doorbell.num_kernel_doorbells * sizeof(u32); in amdgpu_doorbell_get_kfd_info()
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H A Damdgpu_gmc.c44 bool amdgpu_gmc_is_pdb0_enabled(struct amdgpu_device *adev) in amdgpu_gmc_is_pdb0_enabled() argument
46 return adev->gmc.xgmi.connected_to_cpu || amdgpu_virt_xgmi_migrate_enabled(adev); in amdgpu_gmc_is_pdb0_enabled()
57 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev) in amdgpu_gmc_pdb0_alloc() argument
61 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; in amdgpu_gmc_pdb0_alloc()
62 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21; in amdgpu_gmc_pdb0_alloc()
75 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
79 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false); in amdgpu_gmc_pdb0_alloc()
83 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM); in amdgpu_gmc_pdb0_alloc()
86 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0); in amdgpu_gmc_pdb0_alloc()
90 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
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H A Damdgpu_umc.c32 static int amdgpu_umc_convert_error_address(struct amdgpu_device *adev, in amdgpu_umc_convert_error_address() argument
36 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { in amdgpu_umc_convert_error_address()
38 umc_v6_7_convert_error_address(adev, in amdgpu_umc_convert_error_address()
42 dev_warn(adev->dev, in amdgpu_umc_convert_error_address()
50 int amdgpu_umc_page_retirement_mca(struct amdgpu_device *adev, in amdgpu_umc_page_retirement_mca() argument
62 adev->umc.max_ras_err_cnt_per_query); in amdgpu_umc_page_retirement_mca()
64 dev_warn(adev->dev, in amdgpu_umc_page_retirement_mca()
70 err_data.err_addr_len = adev->umc.max_ras_err_cnt_per_query; in amdgpu_umc_page_retirement_mca()
75 ret = amdgpu_umc_convert_error_address(adev, &err_data, err_addr, in amdgpu_umc_page_retirement_mca()
81 amdgpu_ras_add_bad_pages(adev, err_data.err_addr, in amdgpu_umc_page_retirement_mca()
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H A Damdgpu_gart.c75 static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev) in amdgpu_gart_dummy_page_init() argument
79 if (adev->dummy_page_addr) in amdgpu_gart_dummy_page_init()
81 adev->dummy_page_addr = dma_map_page_attrs(&adev->pdev->dev, dummy_page, 0, in amdgpu_gart_dummy_page_init()
84 if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) { in amdgpu_gart_dummy_page_init()
85 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); in amdgpu_gart_dummy_page_init()
86 adev->dummy_page_addr = 0; in amdgpu_gart_dummy_page_init()
99 void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev) in amdgpu_gart_dummy_page_fini() argument
101 if (!adev->dummy_page_addr) in amdgpu_gart_dummy_page_fini()
103 dma_unmap_page_attrs(&adev->pdev->dev, adev->dummy_page_addr, PAGE_SIZE, in amdgpu_gart_dummy_page_fini()
106 adev->dummy_page_addr = 0; in amdgpu_gart_dummy_page_fini()
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H A Dgfx_v12_0.c268 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev);
269 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev);
270 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev);
271 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev);
272 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev);
273 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev);
274 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev,
276 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev);
277 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
279 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
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H A Dvega20_reg_init.c29 int vega20_reg_base_init(struct amdgpu_device *adev) in vega20_reg_base_init() argument
34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega20_reg_base_init()
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega20_reg_base_init()
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in vega20_reg_base_init()
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega20_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega20_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega20_reg_base_init()
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega20_reg_base_init()
42 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega20_reg_base_init()
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H A Dvce_v1_0.c51 static void vce_v1_0_set_ring_funcs(struct amdgpu_device *adev);
52 static void vce_v1_0_set_irq_funcs(struct amdgpu_device *adev);
75 struct amdgpu_device *adev = ring->adev; in vce_v1_0_ring_get_rptr() local
92 struct amdgpu_device *adev = ring->adev; in vce_v1_0_ring_get_wptr() local
109 struct amdgpu_device *adev = ring->adev; in vce_v1_0_ring_set_wptr() local
117 static int vce_v1_0_lmi_clean(struct amdgpu_device *adev) in vce_v1_0_lmi_clean() argument
133 static int vce_v1_0_firmware_loaded(struct amdgpu_device *adev) in vce_v1_0_firmware_loaded() argument
144 dev_err(adev->dev, "VCE not responding, trying to reset the ECPU\n"); in vce_v1_0_firmware_loaded()
158 static void vce_v1_0_init_cg(struct amdgpu_device *adev) in vce_v1_0_init_cg() argument
189 static int vce_v1_0_load_fw(struct amdgpu_device *adev) in vce_v1_0_load_fw() argument
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H A Djpeg_v4_0_5.c65 static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev);
66 static void jpeg_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
87 struct amdgpu_device *adev = ip_block->adev; in jpeg_v4_0_5_early_init() local
89 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in jpeg_v4_0_5_early_init()
91 adev->jpeg.num_jpeg_inst = 1; in jpeg_v4_0_5_early_init()
94 adev->jpeg.num_jpeg_inst = 2; in jpeg_v4_0_5_early_init()
97 DRM_DEV_ERROR(adev->dev, in jpeg_v4_0_5_early_init()
99 amdgpu_ip_version(adev, UVD_HWIP, 0)); in jpeg_v4_0_5_early_init()
103 adev->jpeg.num_jpeg_rings = 1; in jpeg_v4_0_5_early_init()
105 jpeg_v4_0_5_set_dec_ring_funcs(adev); in jpeg_v4_0_5_early_init()
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H A Dvega10_reg_init.c29 int vega10_reg_base_init(struct amdgpu_device *adev) in vega10_reg_base_init() argument
34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega10_reg_base_init()
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega10_reg_base_init()
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in vega10_reg_base_init()
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega10_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega10_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega10_reg_base_init()
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega10_reg_base_init()
42 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega10_reg_base_init()
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H A Dgfx_v11_0.c341 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev);
342 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev);
343 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev);
344 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev);
345 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev);
346 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev);
347 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev);
348 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev,
350 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev);
351 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
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H A Djpeg_v5_3_0.c37 static void jpeg_v5_3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
38 static void jpeg_v5_3_0_set_irq_funcs(struct amdgpu_device *adev);
52 struct amdgpu_device *adev = ip_block->adev; in jpeg_v5_3_0_early_init() local
54 adev->jpeg.num_jpeg_inst = 1; in jpeg_v5_3_0_early_init()
55 adev->jpeg.num_jpeg_rings = 1; in jpeg_v5_3_0_early_init()
57 jpeg_v5_3_0_set_dec_ring_funcs(adev); in jpeg_v5_3_0_early_init()
58 jpeg_v5_3_0_set_irq_funcs(adev); in jpeg_v5_3_0_early_init()
72 struct amdgpu_device *adev = ip_block->adev; in jpeg_v5_3_0_sw_init() local
77 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, in jpeg_v5_3_0_sw_init()
78 VCN_5_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v5_3_0_sw_init()
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H A Dsienna_cichlid.c37 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; in sienna_cichlid_is_mode2_default()
39 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7) && in sienna_cichlid_is_mode2_default()
40 adev->pm.fw_version >= 0x3a5500 && !amdgpu_sriov_vf(adev)) in sienna_cichlid_is_mode2_default()
70 static int sienna_cichlid_mode2_suspend_ip(struct amdgpu_device *adev) in sienna_cichlid_mode2_suspend_ip() argument
74 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); in sienna_cichlid_mode2_suspend_ip()
75 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); in sienna_cichlid_mode2_suspend_ip()
77 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { in sienna_cichlid_mode2_suspend_ip()
78 if (!(adev->ip_blocks[i].version->type == in sienna_cichlid_mode2_suspend_ip()
80 adev->ip_blocks[i].version->type == in sienna_cichlid_mode2_suspend_ip()
84 r = amdgpu_ip_block_suspend(&adev->ip_blocks[i]); in sienna_cichlid_mode2_suspend_ip()
[all …]
/linux/drivers/gpu/drm/amd/pm/
H A Damdgpu_dpm.c36 #define amdgpu_dpm_notify_ac_dc(adev) \ argument
37 ((adev)->powerplay.pp_funcs->notify_ac_dc((adev)->powerplay.pp_handle))
39 #define amdgpu_dpm_is_legacy_dpm(adev) ((adev)->powerplay.pp_handle == (adev)) argument
41 int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) in amdgpu_dpm_get_sclk() argument
43 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_sclk()
49 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_sclk()
50 ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, in amdgpu_dpm_get_sclk()
52 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_sclk()
57 int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) in amdgpu_dpm_get_mclk() argument
59 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_mclk()
[all …]
/linux/sound/soc/intel/avs/
H A Dloader.c103 static int avs_fw_manifest_strip_verify(struct avs_dev *adev, struct firmware *fw, in avs_fw_manifest_strip_verify()
127 dev_warn(adev->dev, "bad FW version %d.%d.%d.%d, expected %d.%d.%d.%d or newer\n", in avs_fw_manifest_strip_verify()
139 int avs_cldma_load_basefw(struct avs_dev *adev, struct firmware *fw) in avs_cldma_load_basefw()
145 ret = avs_dsp_op(adev, power, AVS_MAIN_CORE_MASK, true); in avs_cldma_load_basefw()
149 ret = avs_dsp_op(adev, reset, AVS_MAIN_CORE_MASK, false); in avs_cldma_load_basefw()
155 dev_err(adev->dev, "cldma reset failed: %d\n", ret); in avs_cldma_load_basefw()
160 ret = avs_dsp_op(adev, stall, AVS_MAIN_CORE_MASK, false); in avs_cldma_load_basefw()
164 reinit_completion(&adev->fw_ready); in avs_cldma_load_basefw()
165 avs_dsp_op(adev, int_control, true); in avs_cldma_load_basefw()
168 ret = snd_hdac_adsp_readl_poll(adev, AVS_FW_REG_STATU in avs_cldma_load_basefw()
102 avs_fw_manifest_strip_verify(struct avs_dev * adev,struct firmware * fw,const struct avs_fw_version * min) avs_fw_manifest_strip_verify() argument
138 avs_cldma_load_basefw(struct avs_dev * adev,struct firmware * fw) avs_cldma_load_basefw() argument
194 avs_cldma_load_library(struct avs_dev * adev,struct firmware * lib,u32 id) avs_cldma_load_library() argument
215 avs_cldma_load_module(struct avs_dev * adev,struct avs_module_entry * mentry) avs_cldma_load_module() argument
254 avs_cldma_transfer_modules(struct avs_dev * adev,bool load,struct avs_module_entry * mods,u32 num_mods) avs_cldma_transfer_modules() argument
287 avs_hda_init_rom(struct avs_dev * adev,unsigned int dma_id,bool purge) avs_hda_init_rom() argument
338 avs_imr_load_basefw(struct avs_dev * adev) avs_imr_load_basefw() argument
360 avs_hda_load_basefw(struct avs_dev * adev,struct firmware * fw) avs_hda_load_basefw() argument
428 avs_hda_load_library(struct avs_dev * adev,struct firmware * lib,u32 id) avs_hda_load_library() argument
479 avs_hda_transfer_modules(struct avs_dev * adev,bool load,struct avs_module_entry * mods,u32 num_mods) avs_hda_transfer_modules() argument
489 avs_dsp_load_libraries(struct avs_dev * adev,struct avs_tplg_library * libs,u32 num_libs) avs_dsp_load_libraries() argument
554 avs_dsp_load_basefw(struct avs_dev * adev) avs_dsp_load_basefw() argument
607 avs_load_firmware(struct avs_dev * adev,bool purge) avs_load_firmware() argument
661 avs_config_basefw(struct avs_dev * adev) avs_config_basefw() argument
674 avs_dsp_boot_firmware(struct avs_dev * adev,bool purge) avs_dsp_boot_firmware() argument
685 avs_dsp_alloc_resources(struct avs_dev * adev) avs_dsp_alloc_resources() argument
726 avs_dsp_first_boot_firmware(struct avs_dev * adev) avs_dsp_first_boot_firmware() argument
[all...]
H A Dutils.c16 /* Caller responsible for holding adev->modres_mutex. */ in avs_module_entry_index() argument
17 static int avs_module_entry_index(struct avs_dev *adev, const guid_t *uuid) in avs_module_entry_index()
21 for (i = 0; i < adev->mods_info->count; i++) { in avs_module_entry_index()
24 module = &adev->mods_info->entries[i]; in avs_module_entry_index()
32 /* Caller responsible for holding adev->modres_mutex. */ in avs_module_id_entry_index() argument
33 static int avs_module_id_entry_index(struct avs_dev *adev, u32 module_id) in avs_module_id_entry_index()
37 for (i = 0; i < adev->mods_info->count; i++) { in avs_module_id_entry_index()
40 module = &adev->mods_info->entries[i]; in avs_module_id_entry_index()
48 int avs_get_module_entry(struct avs_dev *adev, const guid_t *uuid, struct avs_module_entry *entry) in avs_get_module_entry()
52 guard(mutex)(&adev in avs_get_module_entry()
47 avs_get_module_entry(struct avs_dev * adev,const guid_t * uuid,struct avs_module_entry * entry) avs_get_module_entry() argument
61 avs_get_module_id_entry(struct avs_dev * adev,u32 module_id,struct avs_module_entry * entry) avs_get_module_id_entry() argument
75 avs_get_module_id(struct avs_dev * adev,const guid_t * uuid) avs_get_module_id() argument
84 avs_is_module_ida_empty(struct avs_dev * adev,u32 module_id) avs_is_module_ida_empty() argument
100 avs_module_ida_destroy(struct avs_dev * adev) avs_module_ida_destroy() argument
113 avs_module_ida_alloc(struct avs_dev * adev,struct avs_mods_info * newinfo,bool purge) avs_module_ida_alloc() argument
157 avs_module_info_init(struct avs_dev * adev,bool purge) avs_module_info_init() argument
183 avs_module_info_free(struct avs_dev * adev) avs_module_info_free() argument
194 avs_module_id_alloc(struct avs_dev * adev,u16 module_id) avs_module_id_alloc() argument
213 avs_module_id_free(struct avs_dev * adev,u16 module_id,u8 instance_id) avs_module_id_free() argument
235 avs_request_firmware(struct avs_dev * adev,const struct firmware ** fw_p,const char * name) avs_request_firmware() argument
277 avs_release_last_firmware(struct avs_dev * adev) avs_release_last_firmware() argument
292 avs_release_firmwares(struct avs_dev * adev) avs_release_firmwares() argument
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