Lines Matching refs:adev
47 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
48 static int kv_enable_nb_dpm(struct amdgpu_device *adev,
50 static void kv_init_graphics_levels(struct amdgpu_device *adev);
51 static int kv_calculate_ds_divider(struct amdgpu_device *adev);
52 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev);
53 static int kv_calculate_dpm_settings(struct amdgpu_device *adev);
54 static void kv_enable_new_levels(struct amdgpu_device *adev);
55 static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
57 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);
58 static int kv_set_enabled_levels(struct amdgpu_device *adev);
59 static int kv_force_dpm_highest(struct amdgpu_device *adev);
60 static int kv_force_dpm_lowest(struct amdgpu_device *adev);
61 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
64 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
66 static int kv_init_fps_limits(struct amdgpu_device *adev);
68 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
69 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
72 static u32 kv_convert_vid2_to_vid7(struct amdgpu_device *adev, in kv_convert_vid2_to_vid7() argument
77 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
94 static u32 kv_convert_vid7_to_vid2(struct amdgpu_device *adev, in kv_convert_vid7_to_vid2() argument
99 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
118 static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable) in sumo_take_smu_control() argument
137 static void sumo_construct_sclk_voltage_mapping_table(struct amdgpu_device *adev, in sumo_construct_sclk_voltage_mapping_table() argument
159 static void sumo_construct_vid_mapping_table(struct amdgpu_device *adev, in sumo_construct_vid_mapping_table() argument
367 static struct kv_power_info *kv_get_pi(struct amdgpu_device *adev) in kv_get_pi() argument
369 struct kv_power_info *pi = adev->pm.dpm.priv; in kv_get_pi()
375 static void kv_program_local_cac_table(struct amdgpu_device *adev,
400 static int kv_program_pt_config_registers(struct amdgpu_device *adev, in kv_program_pt_config_registers() argument
449 static void kv_do_enable_didt(struct amdgpu_device *adev, bool enable) in kv_do_enable_didt() argument
451 struct kv_power_info *pi = kv_get_pi(adev); in kv_do_enable_didt()
491 static int kv_enable_didt(struct amdgpu_device *adev, bool enable) in kv_enable_didt() argument
493 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_didt()
500 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in kv_enable_didt()
503 ret = kv_program_pt_config_registers(adev, didt_config_kv); in kv_enable_didt()
505 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in kv_enable_didt()
510 kv_do_enable_didt(adev, enable); in kv_enable_didt()
512 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in kv_enable_didt()
519 static void kv_initialize_hardware_cac_manager(struct amdgpu_device *adev)
521 struct kv_power_info *pi = kv_get_pi(adev);
526 kv_program_local_cac_table(adev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
530 kv_program_local_cac_table(adev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
534 kv_program_local_cac_table(adev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
538 kv_program_local_cac_table(adev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
542 kv_program_local_cac_table(adev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
546 kv_program_local_cac_table(adev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
551 static int kv_enable_smc_cac(struct amdgpu_device *adev, bool enable) in kv_enable_smc_cac() argument
553 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_smc_cac()
558 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_EnableCac); in kv_enable_smc_cac()
564 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DisableCac); in kv_enable_smc_cac()
572 static int kv_process_firmware_header(struct amdgpu_device *adev) in kv_process_firmware_header() argument
574 struct kv_power_info *pi = kv_get_pi(adev); in kv_process_firmware_header()
578 ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION + in kv_process_firmware_header()
585 ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION + in kv_process_firmware_header()
595 static int kv_enable_dpm_voltage_scaling(struct amdgpu_device *adev) in kv_enable_dpm_voltage_scaling() argument
597 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_dpm_voltage_scaling()
602 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_enable_dpm_voltage_scaling()
611 static int kv_set_dpm_interval(struct amdgpu_device *adev) in kv_set_dpm_interval() argument
613 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_dpm_interval()
618 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_set_dpm_interval()
627 static int kv_set_dpm_boot_state(struct amdgpu_device *adev) in kv_set_dpm_boot_state() argument
629 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_dpm_boot_state()
632 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_set_dpm_boot_state()
641 static void kv_program_vc(struct amdgpu_device *adev) in kv_program_vc() argument
646 static void kv_clear_vc(struct amdgpu_device *adev) in kv_clear_vc() argument
651 static int kv_set_divider_value(struct amdgpu_device *adev, in kv_set_divider_value() argument
654 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_divider_value()
658 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_set_divider_value()
669 static u16 kv_convert_8bit_index_to_voltage(struct amdgpu_device *adev, in kv_convert_8bit_index_to_voltage() argument
675 static u16 kv_convert_2bit_index_to_voltage(struct amdgpu_device *adev, in kv_convert_2bit_index_to_voltage() argument
678 struct kv_power_info *pi = kv_get_pi(adev); in kv_convert_2bit_index_to_voltage()
679 u32 vid_8bit = kv_convert_vid2_to_vid7(adev, in kv_convert_2bit_index_to_voltage()
683 return kv_convert_8bit_index_to_voltage(adev, (u16)vid_8bit); in kv_convert_2bit_index_to_voltage()
687 static int kv_set_vid(struct amdgpu_device *adev, u32 index, u32 vid) in kv_set_vid() argument
689 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_vid()
693 cpu_to_be32(kv_convert_2bit_index_to_voltage(adev, vid)); in kv_set_vid()
698 static int kv_set_at(struct amdgpu_device *adev, u32 index, u32 at) in kv_set_at() argument
700 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_at()
707 static void kv_dpm_power_level_enable(struct amdgpu_device *adev, in kv_dpm_power_level_enable() argument
710 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_power_level_enable()
715 static void kv_start_dpm(struct amdgpu_device *adev) in kv_start_dpm() argument
722 amdgpu_kv_smc_dpm_enable(adev, true); in kv_start_dpm()
725 static void kv_stop_dpm(struct amdgpu_device *adev) in kv_stop_dpm() argument
727 amdgpu_kv_smc_dpm_enable(adev, false); in kv_stop_dpm()
730 static void kv_start_am(struct amdgpu_device *adev) in kv_start_am() argument
741 static void kv_reset_am(struct amdgpu_device *adev) in kv_reset_am() argument
751 static int kv_freeze_sclk_dpm(struct amdgpu_device *adev, bool freeze) in kv_freeze_sclk_dpm() argument
753 return amdgpu_kv_notify_message_to_smu(adev, freeze ? in kv_freeze_sclk_dpm()
757 static int kv_force_lowest_valid(struct amdgpu_device *adev) in kv_force_lowest_valid() argument
759 return kv_force_dpm_lowest(adev); in kv_force_lowest_valid()
762 static int kv_unforce_levels(struct amdgpu_device *adev) in kv_unforce_levels() argument
764 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_unforce_levels()
765 return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NoForcedLevel); in kv_unforce_levels()
767 return kv_set_enabled_levels(adev); in kv_unforce_levels()
770 static int kv_update_sclk_t(struct amdgpu_device *adev) in kv_update_sclk_t() argument
772 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_sclk_t()
779 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_sclk_t()
788 static int kv_program_bootup_state(struct amdgpu_device *adev) in kv_program_bootup_state() argument
790 struct kv_power_info *pi = kv_get_pi(adev); in kv_program_bootup_state()
793 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
802 kv_dpm_power_level_enable(adev, i, true); in kv_program_bootup_state()
816 kv_dpm_power_level_enable(adev, i, true); in kv_program_bootup_state()
821 static int kv_enable_auto_thermal_throttling(struct amdgpu_device *adev) in kv_enable_auto_thermal_throttling() argument
823 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_auto_thermal_throttling()
828 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_enable_auto_thermal_throttling()
837 static int kv_upload_dpm_settings(struct amdgpu_device *adev) in kv_upload_dpm_settings() argument
839 struct kv_power_info *pi = kv_get_pi(adev); in kv_upload_dpm_settings()
842 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_upload_dpm_settings()
852 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_upload_dpm_settings()
866 static u32 kv_get_clk_bypass(struct amdgpu_device *adev, u32 clk) in kv_get_clk_bypass() argument
868 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_clk_bypass()
891 static int kv_populate_uvd_table(struct amdgpu_device *adev) in kv_populate_uvd_table() argument
893 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_uvd_table()
895 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_populate_uvd_table()
914 (u8)kv_get_clk_bypass(adev, table->entries[i].vclk); in kv_populate_uvd_table()
916 (u8)kv_get_clk_bypass(adev, table->entries[i].dclk); in kv_populate_uvd_table()
918 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_uvd_table()
924 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_uvd_table()
933 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_uvd_table()
943 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_uvd_table()
951 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_uvd_table()
962 static int kv_populate_vce_table(struct amdgpu_device *adev) in kv_populate_vce_table() argument
964 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_vce_table()
968 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_populate_vce_table()
984 (u8)kv_get_clk_bypass(adev, table->entries[i].evclk); in kv_populate_vce_table()
986 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_vce_table()
995 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_vce_table()
1006 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_vce_table()
1015 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_vce_table()
1025 static int kv_populate_samu_table(struct amdgpu_device *adev) in kv_populate_samu_table() argument
1027 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_samu_table()
1029 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_populate_samu_table()
1047 (u8)kv_get_clk_bypass(adev, table->entries[i].clk); in kv_populate_samu_table()
1049 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_samu_table()
1058 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_samu_table()
1069 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_samu_table()
1078 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_samu_table()
1091 static int kv_populate_acp_table(struct amdgpu_device *adev) in kv_populate_acp_table() argument
1093 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_acp_table()
1095 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_populate_acp_table()
1108 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_acp_table()
1117 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_acp_table()
1128 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_acp_table()
1137 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_acp_table()
1149 static void kv_calculate_dfs_bypass_settings(struct amdgpu_device *adev) in kv_calculate_dfs_bypass_settings() argument
1151 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_dfs_bypass_settings()
1154 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1199 static int kv_enable_ulv(struct amdgpu_device *adev, bool enable) in kv_enable_ulv() argument
1201 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_ulv()
1205 static void kv_reset_acp_boot_level(struct amdgpu_device *adev) in kv_reset_acp_boot_level() argument
1207 struct kv_power_info *pi = kv_get_pi(adev); in kv_reset_acp_boot_level()
1212 static void kv_update_current_ps(struct amdgpu_device *adev, in kv_update_current_ps() argument
1216 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_current_ps()
1221 adev->pm.dpm.current_ps = &pi->current_rps; in kv_update_current_ps()
1224 static void kv_update_requested_ps(struct amdgpu_device *adev, in kv_update_requested_ps() argument
1228 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_requested_ps()
1233 adev->pm.dpm.requested_ps = &pi->requested_rps; in kv_update_requested_ps()
1238 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_enable_bapm() local
1239 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_enable_bapm()
1243 ret = amdgpu_kv_smc_bapm_enable(adev, enable); in kv_dpm_enable_bapm()
1245 drm_err(adev_to_drm(adev), "amdgpu_kv_smc_bapm_enable failed\n"); in kv_dpm_enable_bapm()
1262 static int kv_dpm_enable(struct amdgpu_device *adev) in kv_dpm_enable() argument
1264 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_enable()
1267 ret = kv_process_firmware_header(adev); in kv_dpm_enable()
1269 drm_err(adev_to_drm(adev), "kv_process_firmware_header failed\n"); in kv_dpm_enable()
1272 kv_init_fps_limits(adev); in kv_dpm_enable()
1273 kv_init_graphics_levels(adev); in kv_dpm_enable()
1274 ret = kv_program_bootup_state(adev); in kv_dpm_enable()
1276 drm_err(adev_to_drm(adev), "kv_program_bootup_state failed\n"); in kv_dpm_enable()
1279 kv_calculate_dfs_bypass_settings(adev); in kv_dpm_enable()
1280 ret = kv_upload_dpm_settings(adev); in kv_dpm_enable()
1282 drm_err(adev_to_drm(adev), "kv_upload_dpm_settings failed\n"); in kv_dpm_enable()
1285 ret = kv_populate_uvd_table(adev); in kv_dpm_enable()
1287 drm_err(adev_to_drm(adev), "kv_populate_uvd_table failed\n"); in kv_dpm_enable()
1290 ret = kv_populate_vce_table(adev); in kv_dpm_enable()
1292 drm_err(adev_to_drm(adev), "kv_populate_vce_table failed\n"); in kv_dpm_enable()
1295 ret = kv_populate_samu_table(adev); in kv_dpm_enable()
1297 drm_err(adev_to_drm(adev), "kv_populate_samu_table failed\n"); in kv_dpm_enable()
1300 ret = kv_populate_acp_table(adev); in kv_dpm_enable()
1302 drm_err(adev_to_drm(adev), "kv_populate_acp_table failed\n"); in kv_dpm_enable()
1305 kv_program_vc(adev); in kv_dpm_enable()
1307 kv_initialize_hardware_cac_manager(adev); in kv_dpm_enable()
1309 kv_start_am(adev); in kv_dpm_enable()
1311 ret = kv_enable_auto_thermal_throttling(adev); in kv_dpm_enable()
1313 drm_err(adev_to_drm(adev), "kv_enable_auto_thermal_throttling failed\n"); in kv_dpm_enable()
1317 ret = kv_enable_dpm_voltage_scaling(adev); in kv_dpm_enable()
1319 drm_err(adev_to_drm(adev), "kv_enable_dpm_voltage_scaling failed\n"); in kv_dpm_enable()
1322 ret = kv_set_dpm_interval(adev); in kv_dpm_enable()
1324 drm_err(adev_to_drm(adev), "kv_set_dpm_interval failed\n"); in kv_dpm_enable()
1327 ret = kv_set_dpm_boot_state(adev); in kv_dpm_enable()
1329 drm_err(adev_to_drm(adev), "kv_set_dpm_boot_state failed\n"); in kv_dpm_enable()
1332 ret = kv_enable_ulv(adev, true); in kv_dpm_enable()
1334 drm_err(adev_to_drm(adev), "kv_enable_ulv failed\n"); in kv_dpm_enable()
1337 kv_start_dpm(adev); in kv_dpm_enable()
1338 ret = kv_enable_didt(adev, true); in kv_dpm_enable()
1340 drm_err(adev_to_drm(adev), "kv_enable_didt failed\n"); in kv_dpm_enable()
1343 ret = kv_enable_smc_cac(adev, true); in kv_dpm_enable()
1345 drm_err(adev_to_drm(adev), "kv_enable_smc_cac failed\n"); in kv_dpm_enable()
1349 kv_reset_acp_boot_level(adev); in kv_dpm_enable()
1351 ret = amdgpu_kv_smc_bapm_enable(adev, false); in kv_dpm_enable()
1353 drm_err(adev_to_drm(adev), "amdgpu_kv_smc_bapm_enable failed\n"); in kv_dpm_enable()
1357 if (adev->irq.installed && in kv_dpm_enable()
1358 kv_is_internal_thermal_sensor(adev->pm.int_thermal_type)) { in kv_dpm_enable()
1359 ret = kv_set_thermal_temperature_range(adev, KV_TEMP_RANGE_MIN, KV_TEMP_RANGE_MAX); in kv_dpm_enable()
1361 drm_err(adev_to_drm(adev), "kv_set_thermal_temperature_range failed\n"); in kv_dpm_enable()
1364 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_enable()
1366 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_enable()
1373 static void kv_dpm_disable(struct amdgpu_device *adev) in kv_dpm_disable() argument
1375 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_disable()
1378 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_disable()
1380 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_disable()
1383 err = amdgpu_kv_smc_bapm_enable(adev, false); in kv_dpm_disable()
1385 drm_err(adev_to_drm(adev), "amdgpu_kv_smc_bapm_enable failed\n"); in kv_dpm_disable()
1387 if (adev->asic_type == CHIP_MULLINS) in kv_dpm_disable()
1388 kv_enable_nb_dpm(adev, false); in kv_dpm_disable()
1391 kv_dpm_powergate_acp(adev, false); in kv_dpm_disable()
1392 kv_dpm_powergate_samu(adev, false); in kv_dpm_disable()
1394 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON); in kv_dpm_disable()
1396 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON); in kv_dpm_disable()
1398 kv_enable_smc_cac(adev, false); in kv_dpm_disable()
1399 kv_enable_didt(adev, false); in kv_dpm_disable()
1400 kv_clear_vc(adev); in kv_dpm_disable()
1401 kv_stop_dpm(adev); in kv_dpm_disable()
1402 kv_enable_ulv(adev, false); in kv_dpm_disable()
1403 kv_reset_am(adev); in kv_dpm_disable()
1405 kv_update_current_ps(adev, adev->pm.dpm.boot_ps); in kv_dpm_disable()
1409 static int kv_write_smc_soft_register(struct amdgpu_device *adev,
1412 struct kv_power_info *pi = kv_get_pi(adev);
1414 return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,
1418 static int kv_read_smc_soft_register(struct amdgpu_device *adev,
1421 struct kv_power_info *pi = kv_get_pi(adev);
1423 return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
1428 static void kv_init_sclk_t(struct amdgpu_device *adev) in kv_init_sclk_t() argument
1430 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_sclk_t()
1435 static int kv_init_fps_limits(struct amdgpu_device *adev) in kv_init_fps_limits() argument
1437 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_fps_limits()
1445 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_init_fps_limits()
1454 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_init_fps_limits()
1464 static void kv_init_powergate_state(struct amdgpu_device *adev) in kv_init_powergate_state() argument
1466 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_powergate_state()
1475 static int kv_enable_uvd_dpm(struct amdgpu_device *adev, bool enable) in kv_enable_uvd_dpm() argument
1477 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_uvd_dpm()
1481 static int kv_enable_vce_dpm(struct amdgpu_device *adev, bool enable) in kv_enable_vce_dpm() argument
1483 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_vce_dpm()
1487 static int kv_enable_samu_dpm(struct amdgpu_device *adev, bool enable) in kv_enable_samu_dpm() argument
1489 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_samu_dpm()
1493 static int kv_enable_acp_dpm(struct amdgpu_device *adev, bool enable) in kv_enable_acp_dpm() argument
1495 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_acp_dpm()
1499 static int kv_update_uvd_dpm(struct amdgpu_device *adev, bool gate) in kv_update_uvd_dpm() argument
1501 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_uvd_dpm()
1503 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_update_uvd_dpm()
1519 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_uvd_dpm()
1527 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_uvd_dpm()
1532 return kv_enable_uvd_dpm(adev, !gate); in kv_update_uvd_dpm()
1535 static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk) in kv_get_vce_boot_level() argument
1539 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_get_vce_boot_level()
1549 static int kv_update_vce_dpm(struct amdgpu_device *adev, in kv_update_vce_dpm() argument
1553 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_vce_dpm()
1555 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_update_vce_dpm()
1562 pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk); in kv_update_vce_dpm()
1564 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_vce_dpm()
1574 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_vce_dpm()
1577 kv_enable_vce_dpm(adev, true); in kv_update_vce_dpm()
1579 kv_enable_vce_dpm(adev, false); in kv_update_vce_dpm()
1585 static int kv_update_samu_dpm(struct amdgpu_device *adev, bool gate) in kv_update_samu_dpm() argument
1587 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_samu_dpm()
1589 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_update_samu_dpm()
1598 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_samu_dpm()
1608 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_samu_dpm()
1613 return kv_enable_samu_dpm(adev, !gate); in kv_update_samu_dpm()
1616 static u8 kv_get_acp_boot_level(struct amdgpu_device *adev) in kv_get_acp_boot_level() argument
1621 static void kv_update_acp_boot_level(struct amdgpu_device *adev) in kv_update_acp_boot_level() argument
1623 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_acp_boot_level()
1627 acp_boot_level = kv_get_acp_boot_level(adev); in kv_update_acp_boot_level()
1630 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_acp_boot_level()
1637 static int kv_update_acp_dpm(struct amdgpu_device *adev, bool gate) in kv_update_acp_dpm() argument
1639 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_acp_dpm()
1641 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_update_acp_dpm()
1648 pi->acp_boot_level = kv_get_acp_boot_level(adev); in kv_update_acp_dpm()
1650 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_acp_dpm()
1660 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_acp_dpm()
1665 return kv_enable_acp_dpm(adev, !gate); in kv_update_acp_dpm()
1670 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_powergate_uvd() local
1671 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_uvd()
1677 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, in kv_dpm_powergate_uvd()
1679 kv_update_uvd_dpm(adev, gate); in kv_dpm_powergate_uvd()
1682 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF); in kv_dpm_powergate_uvd()
1686 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON); in kv_dpm_powergate_uvd()
1688 kv_update_uvd_dpm(adev, gate); in kv_dpm_powergate_uvd()
1690 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, in kv_dpm_powergate_uvd()
1697 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_powergate_vce() local
1698 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_vce()
1704 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, in kv_dpm_powergate_vce()
1706 kv_enable_vce_dpm(adev, false); in kv_dpm_powergate_vce()
1708 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF); in kv_dpm_powergate_vce()
1711 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON); in kv_dpm_powergate_vce()
1712 kv_enable_vce_dpm(adev, true); in kv_dpm_powergate_vce()
1714 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, in kv_dpm_powergate_vce()
1720 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate) in kv_dpm_powergate_samu() argument
1722 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_samu()
1730 kv_update_samu_dpm(adev, true); in kv_dpm_powergate_samu()
1732 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerOFF); in kv_dpm_powergate_samu()
1735 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerON); in kv_dpm_powergate_samu()
1736 kv_update_samu_dpm(adev, false); in kv_dpm_powergate_samu()
1740 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate) in kv_dpm_powergate_acp() argument
1742 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_acp()
1747 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_dpm_powergate_acp()
1753 kv_update_acp_dpm(adev, true); in kv_dpm_powergate_acp()
1755 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerOFF); in kv_dpm_powergate_acp()
1758 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerON); in kv_dpm_powergate_acp()
1759 kv_update_acp_dpm(adev, false); in kv_dpm_powergate_acp()
1763 static void kv_set_valid_clock_range(struct amdgpu_device *adev, in kv_set_valid_clock_range() argument
1767 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_valid_clock_range()
1770 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_set_valid_clock_range()
1825 static int kv_update_dfs_bypass_settings(struct amdgpu_device *adev, in kv_update_dfs_bypass_settings() argument
1829 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_dfs_bypass_settings()
1836 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_dfs_bypass_settings()
1848 static int kv_enable_nb_dpm(struct amdgpu_device *adev, in kv_enable_nb_dpm() argument
1851 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_nb_dpm()
1856 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Enable); in kv_enable_nb_dpm()
1862 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Disable); in kv_enable_nb_dpm()
1875 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_force_performance_level() local
1878 ret = kv_force_dpm_highest(adev); in kv_dpm_force_performance_level()
1882 ret = kv_force_dpm_lowest(adev); in kv_dpm_force_performance_level()
1886 ret = kv_unforce_levels(adev); in kv_dpm_force_performance_level()
1891 adev->pm.dpm.forced_level = level; in kv_dpm_force_performance_level()
1898 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_pre_set_power_state() local
1899 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_pre_set_power_state()
1900 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; in kv_dpm_pre_set_power_state()
1903 kv_update_requested_ps(adev, new_ps); in kv_dpm_pre_set_power_state()
1905 kv_apply_state_adjust_rules(adev, in kv_dpm_pre_set_power_state()
1914 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_set_power_state() local
1915 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_set_power_state()
1921 ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.ac_power); in kv_dpm_set_power_state()
1923 drm_err(adev_to_drm(adev), "amdgpu_kv_smc_bapm_enable failed\n"); in kv_dpm_set_power_state()
1928 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { in kv_dpm_set_power_state()
1930 kv_set_valid_clock_range(adev, new_ps); in kv_dpm_set_power_state()
1931 kv_update_dfs_bypass_settings(adev, new_ps); in kv_dpm_set_power_state()
1932 ret = kv_calculate_ds_divider(adev); in kv_dpm_set_power_state()
1934 drm_err(adev_to_drm(adev), "kv_calculate_ds_divider failed\n"); in kv_dpm_set_power_state()
1937 kv_calculate_nbps_level_settings(adev); in kv_dpm_set_power_state()
1938 kv_calculate_dpm_settings(adev); in kv_dpm_set_power_state()
1939 kv_force_lowest_valid(adev); in kv_dpm_set_power_state()
1940 kv_enable_new_levels(adev); in kv_dpm_set_power_state()
1941 kv_upload_dpm_settings(adev); in kv_dpm_set_power_state()
1942 kv_program_nbps_index_settings(adev, new_ps); in kv_dpm_set_power_state()
1943 kv_unforce_levels(adev); in kv_dpm_set_power_state()
1944 kv_set_enabled_levels(adev); in kv_dpm_set_power_state()
1945 kv_force_lowest_valid(adev); in kv_dpm_set_power_state()
1946 kv_unforce_levels(adev); in kv_dpm_set_power_state()
1948 ret = kv_update_vce_dpm(adev, new_ps, old_ps); in kv_dpm_set_power_state()
1950 drm_err(adev_to_drm(adev), "kv_update_vce_dpm failed\n"); in kv_dpm_set_power_state()
1953 kv_update_sclk_t(adev); in kv_dpm_set_power_state()
1954 if (adev->asic_type == CHIP_MULLINS) in kv_dpm_set_power_state()
1955 kv_enable_nb_dpm(adev, true); in kv_dpm_set_power_state()
1959 kv_set_valid_clock_range(adev, new_ps); in kv_dpm_set_power_state()
1960 kv_update_dfs_bypass_settings(adev, new_ps); in kv_dpm_set_power_state()
1961 ret = kv_calculate_ds_divider(adev); in kv_dpm_set_power_state()
1963 drm_err(adev_to_drm(adev), "kv_calculate_ds_divider failed\n"); in kv_dpm_set_power_state()
1966 kv_calculate_nbps_level_settings(adev); in kv_dpm_set_power_state()
1967 kv_calculate_dpm_settings(adev); in kv_dpm_set_power_state()
1968 kv_freeze_sclk_dpm(adev, true); in kv_dpm_set_power_state()
1969 kv_upload_dpm_settings(adev); in kv_dpm_set_power_state()
1970 kv_program_nbps_index_settings(adev, new_ps); in kv_dpm_set_power_state()
1971 kv_freeze_sclk_dpm(adev, false); in kv_dpm_set_power_state()
1972 kv_set_enabled_levels(adev); in kv_dpm_set_power_state()
1973 ret = kv_update_vce_dpm(adev, new_ps, old_ps); in kv_dpm_set_power_state()
1975 drm_err(adev_to_drm(adev), "kv_update_vce_dpm failed\n"); in kv_dpm_set_power_state()
1978 kv_update_acp_boot_level(adev); in kv_dpm_set_power_state()
1979 kv_update_sclk_t(adev); in kv_dpm_set_power_state()
1980 kv_enable_nb_dpm(adev, true); in kv_dpm_set_power_state()
1989 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_post_set_power_state() local
1990 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_post_set_power_state()
1993 kv_update_current_ps(adev, new_ps); in kv_dpm_post_set_power_state()
1996 static void kv_dpm_setup_asic(struct amdgpu_device *adev) in kv_dpm_setup_asic() argument
1998 sumo_take_smu_control(adev, true); in kv_dpm_setup_asic()
1999 kv_init_powergate_state(adev); in kv_dpm_setup_asic()
2000 kv_init_sclk_t(adev); in kv_dpm_setup_asic()
2004 static void kv_dpm_reset_asic(struct amdgpu_device *adev)
2006 struct kv_power_info *pi = kv_get_pi(adev);
2008 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2009 kv_force_lowest_valid(adev);
2010 kv_init_graphics_levels(adev);
2011 kv_program_bootup_state(adev);
2012 kv_upload_dpm_settings(adev);
2013 kv_force_lowest_valid(adev);
2014 kv_unforce_levels(adev);
2016 kv_init_graphics_levels(adev);
2017 kv_program_bootup_state(adev);
2018 kv_freeze_sclk_dpm(adev, true);
2019 kv_upload_dpm_settings(adev);
2020 kv_freeze_sclk_dpm(adev, false);
2021 kv_set_enabled_level(adev, pi->graphics_boot_level);
2026 static void kv_construct_max_power_limits_table(struct amdgpu_device *adev, in kv_construct_max_power_limits_table() argument
2029 struct kv_power_info *pi = kv_get_pi(adev); in kv_construct_max_power_limits_table()
2036 kv_convert_2bit_index_to_voltage(adev, in kv_construct_max_power_limits_table()
2043 static void kv_patch_voltage_values(struct amdgpu_device *adev) in kv_patch_voltage_values() argument
2047 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_patch_voltage_values()
2049 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_patch_voltage_values()
2051 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_patch_voltage_values()
2053 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_patch_voltage_values()
2058 kv_convert_8bit_index_to_voltage(adev, in kv_patch_voltage_values()
2065 kv_convert_8bit_index_to_voltage(adev, in kv_patch_voltage_values()
2072 kv_convert_8bit_index_to_voltage(adev, in kv_patch_voltage_values()
2079 kv_convert_8bit_index_to_voltage(adev, in kv_patch_voltage_values()
2085 static void kv_construct_boot_state(struct amdgpu_device *adev) in kv_construct_boot_state() argument
2087 struct kv_power_info *pi = kv_get_pi(adev); in kv_construct_boot_state()
2099 static int kv_force_dpm_highest(struct amdgpu_device *adev) in kv_force_dpm_highest() argument
2104 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask); in kv_force_dpm_highest()
2113 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_force_dpm_highest()
2114 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i); in kv_force_dpm_highest()
2116 return kv_set_enabled_level(adev, i); in kv_force_dpm_highest()
2119 static int kv_force_dpm_lowest(struct amdgpu_device *adev) in kv_force_dpm_lowest() argument
2124 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask); in kv_force_dpm_lowest()
2133 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_force_dpm_lowest()
2134 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i); in kv_force_dpm_lowest()
2136 return kv_set_enabled_level(adev, i); in kv_force_dpm_lowest()
2139 static u8 kv_get_sleep_divider_id_from_clock(struct amdgpu_device *adev, in kv_get_sleep_divider_id_from_clock() argument
2142 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_sleep_divider_id_from_clock()
2162 static int kv_get_high_voltage_limit(struct amdgpu_device *adev, int *limit) in kv_get_high_voltage_limit() argument
2164 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_high_voltage_limit()
2166 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_get_high_voltage_limit()
2172 (kv_convert_8bit_index_to_voltage(adev, table->entries[i].v) <= in kv_get_high_voltage_limit()
2184 (kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit) <= in kv_get_high_voltage_limit()
2196 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev, in kv_apply_state_adjust_rules() argument
2201 struct kv_power_info *pi = kv_get_pi(adev); in kv_apply_state_adjust_rules()
2207 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_apply_state_adjust_rules()
2210 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_apply_state_adjust_rules()
2213 new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; in kv_apply_state_adjust_rules()
2214 new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; in kv_apply_state_adjust_rules()
2240 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) in kv_apply_state_adjust_rules()
2241 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; in kv_apply_state_adjust_rules()
2255 kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) { in kv_apply_state_adjust_rules()
2256 kv_get_high_voltage_limit(adev, &limit); in kv_apply_state_adjust_rules()
2267 kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) { in kv_apply_state_adjust_rules()
2268 kv_get_high_voltage_limit(adev, &limit); in kv_apply_state_adjust_rules()
2289 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { in kv_apply_state_adjust_rules()
2302 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) || in kv_apply_state_adjust_rules()
2312 static void kv_dpm_power_level_enabled_for_throttle(struct amdgpu_device *adev, in kv_dpm_power_level_enabled_for_throttle() argument
2315 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_power_level_enabled_for_throttle()
2320 static int kv_calculate_ds_divider(struct amdgpu_device *adev) in kv_calculate_ds_divider() argument
2322 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_ds_divider()
2331 kv_get_sleep_divider_id_from_clock(adev, in kv_calculate_ds_divider()
2338 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev) in kv_calculate_nbps_level_settings() argument
2340 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_nbps_level_settings()
2344 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_calculate_nbps_level_settings()
2350 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { in kv_calculate_nbps_level_settings()
2361 (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); in kv_calculate_nbps_level_settings()
2392 static int kv_calculate_dpm_settings(struct amdgpu_device *adev) in kv_calculate_dpm_settings() argument
2394 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_dpm_settings()
2406 static void kv_init_graphics_levels(struct amdgpu_device *adev) in kv_init_graphics_levels() argument
2408 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_graphics_levels()
2411 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_init_graphics_levels()
2420 kv_convert_8bit_index_to_voltage(adev, table->entries[i].v))) in kv_init_graphics_levels()
2423 kv_set_divider_value(adev, i, table->entries[i].clk); in kv_init_graphics_levels()
2424 vid_2bit = kv_convert_vid7_to_vid2(adev, in kv_init_graphics_levels()
2427 kv_set_vid(adev, i, vid_2bit); in kv_init_graphics_levels()
2428 kv_set_at(adev, i, pi->at[i]); in kv_init_graphics_levels()
2429 kv_dpm_power_level_enabled_for_throttle(adev, i, true); in kv_init_graphics_levels()
2440 kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit)) in kv_init_graphics_levels()
2443 kv_set_divider_value(adev, i, table->entries[i].sclk_frequency); in kv_init_graphics_levels()
2444 kv_set_vid(adev, i, table->entries[i].vid_2bit); in kv_init_graphics_levels()
2445 kv_set_at(adev, i, pi->at[i]); in kv_init_graphics_levels()
2446 kv_dpm_power_level_enabled_for_throttle(adev, i, true); in kv_init_graphics_levels()
2452 kv_dpm_power_level_enable(adev, i, false); in kv_init_graphics_levels()
2455 static void kv_enable_new_levels(struct amdgpu_device *adev) in kv_enable_new_levels() argument
2457 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_new_levels()
2462 kv_dpm_power_level_enable(adev, i, true); in kv_enable_new_levels()
2466 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level) in kv_set_enabled_level() argument
2470 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_set_enabled_level()
2475 static int kv_set_enabled_levels(struct amdgpu_device *adev) in kv_set_enabled_levels() argument
2477 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_enabled_levels()
2483 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_set_enabled_levels()
2488 static void kv_program_nbps_index_settings(struct amdgpu_device *adev, in kv_program_nbps_index_settings() argument
2492 struct kv_power_info *pi = kv_get_pi(adev); in kv_program_nbps_index_settings()
2495 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_program_nbps_index_settings()
2512 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev, in kv_set_thermal_temperature_range() argument
2524 drm_err(adev_to_drm(adev), "invalid thermal range: %d - %d\n", low_temp, high_temp); in kv_set_thermal_temperature_range()
2535 adev->pm.dpm.thermal.min_temp = low_temp; in kv_set_thermal_temperature_range()
2536 adev->pm.dpm.thermal.max_temp = high_temp; in kv_set_thermal_temperature_range()
2550 static int kv_parse_sys_info_table(struct amdgpu_device *adev) in kv_parse_sys_info_table() argument
2552 struct kv_power_info *pi = kv_get_pi(adev); in kv_parse_sys_info_table()
2553 struct amdgpu_mode_info *mode_info = &adev->mode_info; in kv_parse_sys_info_table()
2566 drm_err(adev_to_drm(adev), "Unsupported IGP table: %d %d\n", frev, crev); in kv_parse_sys_info_table()
2582 drm_err(adev_to_drm(adev), "The htcTmpLmt should be larger than htcHystLmt.\n"); in kv_parse_sys_info_table()
2600 sumo_construct_sclk_voltage_mapping_table(adev, in kv_parse_sys_info_table()
2604 sumo_construct_vid_mapping_table(adev, in kv_parse_sys_info_table()
2608 kv_construct_max_power_limits_table(adev, in kv_parse_sys_info_table()
2609 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac); in kv_parse_sys_info_table()
2635 static void kv_patch_boot_state(struct amdgpu_device *adev, in kv_patch_boot_state() argument
2638 struct kv_power_info *pi = kv_get_pi(adev); in kv_patch_boot_state()
2644 static void kv_parse_pplib_non_clock_info(struct amdgpu_device *adev, in kv_parse_pplib_non_clock_info() argument
2664 adev->pm.dpm.boot_ps = rps; in kv_parse_pplib_non_clock_info()
2665 kv_patch_boot_state(adev, ps); in kv_parse_pplib_non_clock_info()
2668 adev->pm.dpm.uvd_ps = rps; in kv_parse_pplib_non_clock_info()
2671 static void kv_parse_pplib_clock_info(struct amdgpu_device *adev, in kv_parse_pplib_clock_info() argument
2675 struct kv_power_info *pi = kv_get_pi(adev); in kv_parse_pplib_clock_info()
2693 static int kv_parse_power_table(struct amdgpu_device *adev) in kv_parse_power_table() argument
2695 struct amdgpu_mode_info *mode_info = &adev->mode_info; in kv_parse_power_table()
2715 amdgpu_add_thermal_controller(adev); in kv_parse_power_table()
2727 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in kv_parse_power_table()
2730 if (!adev->pm.dpm.ps) in kv_parse_power_table()
2742 adev->pm.dpm.ps[i].ps_priv = ps; in kv_parse_power_table()
2754 kv_parse_pplib_clock_info(adev, in kv_parse_power_table()
2755 &adev->pm.dpm.ps[i], k, in kv_parse_power_table()
2759 kv_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], in kv_parse_power_table()
2764 adev->pm.dpm.num_ps = state_array->ucNumEntries; in kv_parse_power_table()
2767 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { in kv_parse_power_table()
2769 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; in kv_parse_power_table()
2774 adev->pm.dpm.vce_states[i].sclk = sclk; in kv_parse_power_table()
2775 adev->pm.dpm.vce_states[i].mclk = 0; in kv_parse_power_table()
2781 static int kv_dpm_init(struct amdgpu_device *adev) in kv_dpm_init() argument
2789 adev->pm.dpm.priv = pi; in kv_dpm_init()
2791 ret = amdgpu_get_platform_caps(adev); in kv_dpm_init()
2795 ret = amdgpu_parse_extended_power_table(adev); in kv_dpm_init()
2816 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) in kv_dpm_init()
2830 pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false; in kv_dpm_init()
2832 pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false; in kv_dpm_init()
2833 pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false; in kv_dpm_init()
2834 pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false; in kv_dpm_init()
2837 ret = kv_parse_sys_info_table(adev); in kv_dpm_init()
2841 kv_patch_voltage_values(adev); in kv_dpm_init()
2842 kv_construct_boot_state(adev); in kv_dpm_init()
2844 ret = kv_parse_power_table(adev); in kv_dpm_init()
2857 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_debugfs_print_current_performance_level() local
2858 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_debugfs_print_current_performance_level()
2873 vddc = kv_convert_8bit_index_to_voltage(adev, (u16)tmp); in kv_dpm_debugfs_print_current_performance_level()
2887 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_print_power_state() local
2889 amdgpu_dpm_dbg_print_class_info(adev, rps->class, rps->class2); in kv_dpm_print_power_state()
2890 amdgpu_dpm_dbg_print_cap_info(adev, rps->caps); in kv_dpm_print_power_state()
2891 drm_dbg(adev_to_drm(adev), "vclk: %d, dclk: %d\n", in kv_dpm_print_power_state()
2895 drm_dbg(adev_to_drm(adev), in kv_dpm_print_power_state()
2898 kv_convert_8bit_index_to_voltage(adev, pl->vddc_index)); in kv_dpm_print_power_state()
2900 amdgpu_dpm_dbg_print_ps_status(adev, rps); in kv_dpm_print_power_state()
2903 static void kv_dpm_fini(struct amdgpu_device *adev) in kv_dpm_fini() argument
2907 for (i = 0; i < adev->pm.dpm.num_ps; i++) { in kv_dpm_fini()
2908 kfree(adev->pm.dpm.ps[i].ps_priv); in kv_dpm_fini()
2910 kfree(adev->pm.dpm.ps); in kv_dpm_fini()
2911 kfree(adev->pm.dpm.priv); in kv_dpm_fini()
2912 amdgpu_free_extended_power_table(adev); in kv_dpm_fini()
2922 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_get_sclk() local
2923 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_get_sclk()
2934 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_get_mclk() local
2935 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_get_mclk()
2945 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_get_temp() local
2961 struct amdgpu_device *adev = ip_block->adev; in kv_dpm_early_init() local
2963 adev->powerplay.pp_funcs = &kv_dpm_funcs; in kv_dpm_early_init()
2964 adev->powerplay.pp_handle = adev; in kv_dpm_early_init()
2965 kv_dpm_set_irq_funcs(adev); in kv_dpm_early_init()
2973 struct amdgpu_device *adev = ip_block->adev; in kv_dpm_late_init() local
2975 if (!adev->pm.dpm_enabled) in kv_dpm_late_init()
2978 kv_dpm_powergate_acp(adev, true); in kv_dpm_late_init()
2979 kv_dpm_powergate_samu(adev, true); in kv_dpm_late_init()
2987 struct amdgpu_device *adev = ip_block->adev; in kv_dpm_sw_init() local
2988 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, in kv_dpm_sw_init()
2989 &adev->pm.dpm.thermal.irq); in kv_dpm_sw_init()
2993 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, in kv_dpm_sw_init()
2994 &adev->pm.dpm.thermal.irq); in kv_dpm_sw_init()
2999 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; in kv_dpm_sw_init()
3000 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in kv_dpm_sw_init()
3001 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO; in kv_dpm_sw_init()
3002 adev->pm.default_sclk = adev->clock.default_sclk; in kv_dpm_sw_init()
3003 adev->pm.default_mclk = adev->clock.default_mclk; in kv_dpm_sw_init()
3004 adev->pm.current_sclk = adev->clock.default_sclk; in kv_dpm_sw_init()
3005 adev->pm.current_mclk = adev->clock.default_mclk; in kv_dpm_sw_init()
3006 adev->pm.int_thermal_type = THERMAL_TYPE_NONE; in kv_dpm_sw_init()
3011 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); in kv_dpm_sw_init()
3012 ret = kv_dpm_init(adev); in kv_dpm_sw_init()
3015 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in kv_dpm_sw_init()
3017 amdgpu_pm_print_power_states(adev); in kv_dpm_sw_init()
3018 drm_info(adev_to_drm(adev), "dpm initialized\n"); in kv_dpm_sw_init()
3023 kv_dpm_fini(adev); in kv_dpm_sw_init()
3024 drm_err(adev_to_drm(adev), "dpm initialization failed: %d\n", ret); in kv_dpm_sw_init()
3030 struct amdgpu_device *adev = ip_block->adev; in kv_dpm_sw_fini() local
3032 flush_work(&adev->pm.dpm.thermal.work); in kv_dpm_sw_fini()
3034 kv_dpm_fini(adev); in kv_dpm_sw_fini()
3042 struct amdgpu_device *adev = ip_block->adev; in kv_dpm_hw_init() local
3047 mutex_lock(&adev->pm.mutex); in kv_dpm_hw_init()
3048 kv_dpm_setup_asic(adev); in kv_dpm_hw_init()
3049 ret = kv_dpm_enable(adev); in kv_dpm_hw_init()
3051 adev->pm.dpm_enabled = false; in kv_dpm_hw_init()
3053 adev->pm.dpm_enabled = true; in kv_dpm_hw_init()
3054 amdgpu_legacy_dpm_compute_clocks(adev); in kv_dpm_hw_init()
3055 mutex_unlock(&adev->pm.mutex); in kv_dpm_hw_init()
3062 struct amdgpu_device *adev = ip_block->adev; in kv_dpm_hw_fini() local
3064 if (adev->pm.dpm_enabled) in kv_dpm_hw_fini()
3065 kv_dpm_disable(adev); in kv_dpm_hw_fini()
3072 struct amdgpu_device *adev = ip_block->adev; in kv_dpm_suspend() local
3074 cancel_work_sync(&adev->pm.dpm.thermal.work); in kv_dpm_suspend()
3076 if (adev->pm.dpm_enabled) { in kv_dpm_suspend()
3077 mutex_lock(&adev->pm.mutex); in kv_dpm_suspend()
3078 adev->pm.dpm_enabled = false; in kv_dpm_suspend()
3080 kv_dpm_disable(adev); in kv_dpm_suspend()
3082 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in kv_dpm_suspend()
3083 mutex_unlock(&adev->pm.mutex); in kv_dpm_suspend()
3091 struct amdgpu_device *adev = ip_block->adev; in kv_dpm_resume() local
3096 if (!adev->pm.dpm_enabled) { in kv_dpm_resume()
3097 mutex_lock(&adev->pm.mutex); in kv_dpm_resume()
3099 kv_dpm_setup_asic(adev); in kv_dpm_resume()
3100 ret = kv_dpm_enable(adev); in kv_dpm_resume()
3102 adev->pm.dpm_enabled = false; in kv_dpm_resume()
3104 adev->pm.dpm_enabled = true; in kv_dpm_resume()
3105 amdgpu_legacy_dpm_compute_clocks(adev); in kv_dpm_resume()
3107 mutex_unlock(&adev->pm.mutex); in kv_dpm_resume()
3117 static int kv_dpm_set_interrupt_state(struct amdgpu_device *adev, in kv_dpm_set_interrupt_state() argument
3165 static int kv_dpm_process_interrupt(struct amdgpu_device *adev, in kv_dpm_process_interrupt() argument
3177 adev->pm.dpm.thermal.high_to_low = false; in kv_dpm_process_interrupt()
3182 adev->pm.dpm.thermal.high_to_low = true; in kv_dpm_process_interrupt()
3190 schedule_work(&adev->pm.dpm.thermal.work); in kv_dpm_process_interrupt()
3226 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_check_state_equal() local
3228 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) in kv_check_state_equal()
3262 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_read_sensor() local
3263 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_read_sensor()
3285 *((uint32_t *)value) = kv_dpm_get_temp(adev); in kv_dpm_read_sensor()
3357 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev) in kv_dpm_set_irq_funcs() argument
3359 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; in kv_dpm_set_irq_funcs()
3360 adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs; in kv_dpm_set_irq_funcs()