/linux/tools/perf/Documentation/ |
H A D | perf-c2c.txt | 37 for cachelines with highest contention - highest number of HITM accesses. 196 - cacheline percentage of all Remote/Local HITM accesses 199 - cacheline percentage of all peer accesses 208 - sum of all cachelines accesses 211 - sum of all load accesses 214 - sum of all store accesses 217 L1Hit - store accesses that hit L1 218 L1Miss - store accesses that missed L1 219 N/A - store accesses with memory level is not available 225 - count of LLC load accesses, includes LLC hits and LLC HITMs [all …]
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/linux/tools/memory-model/Documentation/ |
H A D | ordering.txt | 15 2. Ordered memory accesses. These operations order themselves 16 against some or all of the CPU's prior accesses or some or all 17 of the CPU's subsequent accesses, depending on the subcategory 20 3. Unordered accesses, as the name indicates, have no ordering 48 a device driver, which must correctly order accesses to a physical 68 accesses against all subsequent accesses from the viewpoint of all CPUs. 89 CPU's accesses into three groups: 245 The Linux kernel provides a wide variety of ordered memory accesses: 264 of the CPU's prior memory accesses. Release operations often provide 323 memory accesses. Acquire operations often provide improved performance [all …]
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H A D | access-marking.txt | 5 normal accesses to shared memory, that is "normal" as in accesses that do 7 document these accesses, both with comments and with special assertions 18 1. Plain C-language accesses (unmarked), for example, "a = b;" 39 Neither plain C-language accesses nor data_race() (#1 and #2 above) place 46 C-language accesses. It is permissible to combine #2 and #3, for example, 51 C-language accesses, but marking all accesses involved in a given data 60 data_race() and even plain C-language accesses is preferable to 88 reads can enable better checking of the remaining accesses implementing 135 the other accesses to the relevant shared variables. But please note 172 Here are some example situations where plain C-language accesses should [all …]
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H A D | glossary.txt | 83 each pair of memory accesses, the outcome where r0, r1, and r2 118 its CPU's prior accesses with all of that CPU's subsequent 119 accesses, or a marked access such as atomic_add_return() 120 that orders all of its CPU's prior accesses, itself, and 121 all of its CPU's subsequent accesses. 123 Happens-Before (hb): A relation between two accesses in which LKMM 134 data between two CPUs requires that both CPUs their accesses.
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H A D | cheatsheet.txt | 34 SELF: Orders self, as opposed to accesses before and/or after 35 SV: Orders later accesses to the same variable
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H A D | explanation.txt | 87 factors such as DMA and mixed-size accesses.) But on multiprocessor 88 systems, with multiple CPUs making concurrent accesses to shared 141 This pattern of memory accesses, where one CPU stores values to two 152 accesses by the CPUs. 277 In short, if a memory model requires certain accesses to be ordered, 279 if those accesses would form a cycle, then the memory model predicts 306 Atomic read-modify-write accesses, such as atomic_inc() or xchg(), 313 logical computations, control-flow instructions, or accesses to 343 po-loc is a sub-relation of po. It links two memory accesses when the 358 that add memory accesses, eliminate accesses, combine them, split them [all …]
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/linux/Documentation/i2c/ |
H A D | i2c-topology.rst | 83 This means that accesses to D2 are lockout out for the full duration 84 of the entire operation. But accesses to D3 are possibly interleaved 165 This means that accesses to both D2 and D3 are locked out for the full 231 When device D1 is accessed, accesses to D2 are locked out for the 233 are locked). But accesses to D3 and D4 are possibly interleaved at 236 Accesses to D3 locks out D1 and D2, but accesses to D4 are still possibly 254 When device D1 is accessed, accesses to D2 and D3 are locked out 256 root adapter). But accesses to D4 are possibly interleaved at any 267 mux. In that case, any interleaved accesses to D4 might close M2 288 When D1 is accessed, accesses to D2 are locked out for the full [all …]
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/linux/arch/mips/kvm/ |
H A D | Kconfig | 34 bool "Maintain counters for COP0 accesses" 37 Maintain statistics for Guest COP0 accesses. 38 A histogram of COP0 accesses is printed when the VM is
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/linux/Documentation/core-api/ |
H A D | unaligned-memory-access.rst | 15 unaligned accesses, why you need to write code that doesn't cause them, 22 Unaligned memory accesses occur when you try to read N bytes of data starting 59 - Some architectures are able to perform unaligned memory accesses 61 - Some architectures raise processor exceptions when unaligned accesses 64 - Some architectures raise processor exceptions when unaligned accesses 72 memory accesses to happen, your code will not work correctly on certain 103 to pad structures so that accesses to fields are suitably aligned (assuming 136 lead to unaligned accesses when accessing fields that do not satisfy 183 Here is another example of some code that could cause unaligned accesses:: 192 This code will cause unaligned accesses every time the data parameter points [all …]
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/linux/drivers/acpi/acpica/ |
H A D | exprep.c | 65 u32 accesses; in acpi_ex_generate_access() local 115 accesses = field_end_offset - field_start_offset; in acpi_ex_generate_access() 124 accesses)); in acpi_ex_generate_access() 128 if (accesses <= 1) { in acpi_ex_generate_access() 140 if (accesses < minimum_accesses) { in acpi_ex_generate_access() 141 minimum_accesses = accesses; in acpi_ex_generate_access()
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/linux/Documentation/ABI/testing/ |
H A D | sysfs-fs-ubifs | 8 This counter keeps track of the number of accesses of nodes 20 This counter keeps track of the number of accesses of nodes 32 This counter keeps track of the number of accesses of nodes
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/linux/Documentation/admin-guide/hw-vuln/ |
H A D | special-register-buffer-data-sampling.rst | 8 infer values returned from special register accesses. Special register 9 accesses are accesses to off core registers. According to Intel's evaluation, 70 accesses from other logical processors will be delayed until the special 82 #. Executing RDRAND, RDSEED or EGETKEY will delay memory accesses from other 84 legacy locked cache-line-split accesses. 91 processors memory accesses. The opt-out mechanism does not affect Intel SGX
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/linux/Documentation/devicetree/bindings/ |
H A D | common-properties.txt | 13 - big-endian: Boolean; force big endian register accesses 16 - little-endian: Boolean; force little endian register accesses 19 - native-endian: Boolean; always use register accesses matched to the 30 default to LE for their MMIO accesses.
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/linux/tools/memory-model/ |
H A D | linux-kernel.cat | 173 (* Plain accesses and data races *) 176 (* Warn about plain writes and marked accesses in the same region *) 177 let mixed-accesses = ([Plain & W] ; (po-loc \ barrier) ; [Marked]) | 179 flag ~empty mixed-accesses as mixed-accesses 186 (* Boundaries for lifetimes of plain accesses *) 194 (* Visibility and executes-before for plain accesses *) 204 (* Coherence requirements for plain accesses *)
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/linux/Documentation/devicetree/bindings/mtd/ |
H A D | gpio-control-nand.txt | 10 resource describes the data bus connected to the NAND flash and all accesses 23 location used to guard against bus reordering with regards to accesses to 26 read to ensure that the GPIO accesses have completed.
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/linux/Documentation/hwmon/ |
H A D | w83627hf.rst | 5 * Winbond W83627HF (ISA accesses ONLY) 41 This driver implements support for ISA accesses *only* for 45 This driver supports ISA accesses, which should be more reliable 46 than i2c accesses. Also, for Tyan boards which contain both a 51 If you really want i2c accesses for these Super I/O chips,
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/linux/tools/memory-model/litmus-tests/ |
H A D | dep+plain.litmus | 6 * This litmus test demonstrates that in LKMM, plain accesses 7 * carry dependencies much like accesses to registers:
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H A D | LB+unlocklockonceonce+poacquireonce.litmus | 6 * If two locked critical sections execute on the same CPU, all accesses 7 * in the first must execute before any accesses in the second, even if the
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H A D | MP+porevlocks.litmus | 9 * given lock), a CPU is not only guaranteed to see the accesses that other 11 * see all prior accesses by those other CPUs.
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H A D | MP+polocks.litmus | 9 * given lock), a CPU is not only guaranteed to see the accesses that other 11 * to see all prior accesses by those other CPUs.
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H A D | README | 40 litmus test is visible to an external process whose accesses are 149 spin_lock() sufficient to make ordering apparent to accesses 158 to make ordering apparent to accesses by a process that does 181 Each class defines the pattern of accesses and of the variables accessed. 214 accesses with descriptions of the second access in the pair. 228 to a different variable ("d"), and both accesses are reads ("RR"). 254 The descriptors that describe connections between consecutive accesses
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/linux/Documentation/arch/riscv/ |
H A D | hwprobe.rst | 247 the performance of misaligned scalar native word accesses on the selected set 251 misaligned scalar accesses is unknown. 254 accesses are emulated via software, either in or below the kernel. These 255 accesses are always extremely slow. 258 word sized accesses are slower than the equivalent quantity of byte 259 accesses. Misaligned accesses may be supported directly in hardware, or 263 word sized accesses are faster than the equivalent quantity of byte 264 accesses. 267 accesses are not supported at all and will generate a misaligned address
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/linux/Documentation/process/ |
H A D | volatile-considered-harmful.rst | 39 meaning that data accesses will not be optimized across them. So the 43 accesses to that data. 53 registers. Within the kernel, register accesses, too, should be protected 55 accesses within a critical section. But, within the kernel, I/O memory 56 accesses are always done through accessor functions; accessing I/O memory
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/linux/Documentation/driver-api/ |
H A D | device-io.rst | 30 part of the CPU's address space is interpreted not as accesses to 31 memory, but as accesses to a device. Some architectures define devices 54 historical accident, these are named byte, word, long and quad accesses. 55 Both read and write accesses are supported; there is no prefetch support 127 addresses is generally not as fast as accesses to the memory mapped 137 allow 8-bit, 16-bit and 32-bit accesses; also known as byte, word and 143 that accesses to their ports are slowed down. This functionality is 172 MMIO accesses and DMA accesses as well as fixed endianness for accessing 223 on 32-bit architectures but allow two consecutive 32-bit accesses instead. 238 multiple consecutive accesses can be combined on the bus. In portable code, it [all …]
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/linux/lib/ |
H A D | Kconfig.kcsan | 39 distinguish them from other plain accesses. This is currently 199 plain accesses by default (depending on !KCSAN_STRICT) reduce the 200 ability to detect any data races invoving reordered accesses, in 223 races due to conflicts where the only plain accesses are aligned 230 bool "Do not instrument marked atomic accesses" 233 Never instrument marked atomic accesses. This option can be used for 242 accesses, conflicting marked atomic reads and plain writes will not
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