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/linux/drivers/clk/sunxi-ng/
H A Dccu_mux.h32 #define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table) \ argument
35 .width = _width, \
39 #define _SUNXI_CCU_MUX(_shift, _width) \ argument
40 _SUNXI_CCU_MUX_TABLE(_shift, _width, NULL)
50 _reg, _shift, _width, _gate, \ argument
54 .mux = _SUNXI_CCU_MUX_TABLE(_shift, _width, _table), \
67 _width, _gate, _flags) \ argument
70 _width, _gate, _flags, \
74 _reg, _shift, _width, _gate, \ argument
78 _width, _gate, _flags, 0)
[all …]
H A Dccu_div.h43 #define _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, _flags) \ argument
46 .width = _width, \
51 #define _SUNXI_CCU_DIV_TABLE(_shift, _width, _table) \ argument
52 _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, 0)
54 #define _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _off, _max, _flags) \ argument
57 .width = _width, \
63 #define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \ argument
64 _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, 1, _max, _flags)
66 #define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \ argument
67 _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, 0, _flags)
[all …]
H A Dccu_mult.h17 #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \ argument
23 .width = _width, \
26 #define _SUNXI_CCU_MULT_MIN(_shift, _width, _min) \ argument
27 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, _min, 0)
29 #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \ argument
30 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, 1, 0)
32 #define _SUNXI_CCU_MULT(_shift, _width) \ argument
33 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, 1, 0)
H A Dccu_phase.h20 #define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \ argument
23 .width = _width, \
/linux/drivers/clk/mediatek/
H A Dclk-mux.h49 _mux_clr_ofs, _shift, _width, _gate, _upd_ofs, \ argument
58 .mux_width = _width, \
69 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
73 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
78 _width, _gate, _upd_ofs, _upd, _flags, _ops) \ argument
81 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
90 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
93 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
99 _shift, _width, _gate, _upd_ofs, _upd, _flags) \ argument
102 _shift, _width, _gate, _upd_ofs, _upd, _flags, \
[all …]
H A Dclk-mtk.h115 _width, _gate, _flags, _muxflags) { \ argument
120 .mux_width = _width, \
134 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
137 _shift, _width, _gate, _flags, 0)
143 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
144 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
147 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
149 _shift, _width, CLK_SET_RATE_PARENT)
151 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ argument
156 .mux_width = _width, \
[all …]
H A Dclk-mt6795-topckgen.c21 #define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
23 (_reg + 0x4), (_reg + 0x8), _shift, _width, \
26 #define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
27 TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, \
H A Dclk-mt8173-topckgen.c22 #define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
24 (_reg + 0x4), (_reg + 0x8), _shift, _width, \
27 #define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
28 TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, \
/linux/drivers/clk/sprd/
H A Dmux.h32 #define _SPRD_MUX_CLK(_shift, _width, _table) \ argument
35 .width = _width, \
40 _reg, _shift, _width, _flags, _fn) \ argument
42 .mux = _SPRD_MUX_CLK(_shift, _width, _table), \
52 _reg, _shift, _width, _flags) \ argument
54 _reg, _shift, _width, _flags, \
58 _shift, _width, _flags) \ argument
60 _reg, _shift, _width, _flags)
63 _reg, _shift, _width, _flags) \ argument
65 _reg, _shift, _width, _flags, \
[all …]
H A Ddiv.h28 #define _SPRD_DIV_CLK(_offset, _shift, _width) \ argument
32 .width = _width, \
41 _shift, _width, _flags, _fn) \ argument
43 .div = _SPRD_DIV_CLK(_offset, _shift, _width), \
53 _shift, _width, _flags) \ argument
55 _shift, _width, _flags, CLK_HW_INIT)
58 _shift, _width, _flags) \ argument
60 _shift, _width, _flags, CLK_HW_INIT_FW_NAME)
63 _shift, _width, _flags) \ argument
65 _shift, _width, _flags, CLK_HW_INIT_HW)
/linux/drivers/clk/actions/
H A Dowl-pll.h42 _width, _min_mul, _max_mul, _delay, _table) \ argument
48 .width = _width, \
56 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
59 _width, _min_mul, _max_mul, \
71 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
74 _width, _min_mul, _max_mul, \
85 _shift, _width, _min_mul, _max_mul, _delay, _table, \ argument
89 _width, _min_mul, _max_mul, \
H A Dowl-mux.h27 #define OWL_MUX_HW(_reg, _shift, _width) \ argument
31 .width = _width, \
35 _shift, _width, _flags) \ argument
37 .mux_hw = OWL_MUX_HW(_reg, _shift, _width), \
H A Dowl-divider.h29 #define OWL_DIVIDER_HW(_reg, _shift, _width, _div_flags, _table) \ argument
33 .width = _width, \
39 _shift, _width, _table, _div_flags, _flags) \ argument
41 .div_hw = OWL_DIVIDER_HW(_reg, _shift, _width, \
H A Dowl-factor.h35 #define OWL_FACTOR_HW(_reg, _shift, _width, _fct_flags, _table) \ argument
39 .width = _width, \
45 _shift, _width, _table, _fct_flags, _flags) \ argument
48 _width, _fct_flags, _table), \
/linux/drivers/clk/spacemit/
H A Dccu_mix.h49 #define CCU_MUX_INIT(_shift, _width) { .shift = _shift, .width = _width } argument
50 #define CCU_DIV_INIT(_shift, _width) { .shift = _shift, .width = _width } argument
85 #define CCU_MUX_DEFINE(_name, _parents, _reg_ctrl, _shift, _width, _flags) \ argument
87 .mux = CCU_MUX_INIT(_shift, _width), \
95 #define CCU_DIV_DEFINE(_name, _parent, _reg_ctrl, _shift, _width, _flags) \ argument
97 .div = CCU_DIV_INIT(_shift, _width), \
120 #define CCU_MUX_GATE_DEFINE(_name, _parents, _reg_ctrl, _shift, _width, \ argument
124 .mux = CCU_MUX_INIT(_shift, _width), \
132 #define CCU_DIV_GATE_DEFINE(_name, _parent, _reg_ctrl, _shift, _width, \ argument
136 .div = CCU_DIV_INIT(_shift, _width), \
/linux/drivers/clk/x86/
H A Dclk-cgu.h204 _shift, _width, _cf, _v) \ argument
214 .mux_width = _width, \
219 #define LGM_DIV(_id, _name, _pname, _f, _reg, _shift, _width, \ argument
233 .div_width = _width, \
260 _shift, _width, _cf, _freq, _v) \ argument
273 .div_width = _width, \
280 _shift, _width, _cf, _v, _m, _d) \ argument
293 .div_width = _width, \
/linux/drivers/clk/pistachio/
H A Dclk.h59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
63 .width = _width, \
69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
73 .width = _width, \
/linux/drivers/clk/renesas/
H A Drzv2h-cpg.h68 #define DDIV_PACK(_offset, _shift, _width, _monbit) \ argument
72 .width = _width, \
76 #define DDIV_PACK_NO_RMW(_offset, _shift, _width, _monbit) \ argument
80 .width = (_width), \
98 #define SMUX_PACK(_offset, _shift, _width) \ argument
102 .width = (_width), \
/linux/drivers/clk/sophgo/
H A Dclk-sg2042-clkgen.c279 _r_ctrl, _shift, _width, \ argument
289 .width = _width, \
295 _r_ctrl, _shift, _width, \ argument
305 .width = _width, \
311 _r_ctrl, _shift, _width, \ argument
321 .width = _width, \
327 _r_ctrl, _shift, _width, \ argument
337 .width = _width, \
343 _r_ctrl, _shift, _width, \ argument
353 .width = _width, \
[all …]
H A Dclk-cv18xx-common.h51 #define CV1800_CLK_REG(_reg, _shift, _width, _initval, _flags) \ argument
55 .width = _width, \
/linux/drivers/clk/bcm/
H A Dclk-kona.h291 #define DIVIDER(_offset, _shift, _width) \ argument
295 .u.s.width = (_width), \
301 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ argument
305 .u.s.width = (_width), \
342 #define SELECTOR(_offset, _shift, _width) \ argument
346 .width = (_width), \
/linux/drivers/pinctrl/berlin/
H A Dberlin.h31 #define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \ argument
35 .bit_width = _width, \
/linux/drivers/clk/microchip/
H A Dclk-mpfs-ccc.c101 #define CLK_CCC_PLL(_id, _parents, _shift, _width, _flags, _offset) { \ argument
104 .width = _width, \
124 #define CLK_CCC_OUT(_id, _shift, _width, _flags, _offset) { \ argument
127 .divider.width = _width, \
H A Dclk-mpfs.c166 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ argument
170 .width = _width, \
205 #define CLK_PLL_OUT(_id, _name, _parent, _flags, _shift, _width, _offset) { \ argument
208 .output.width = _width, \
299 #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ argument
302 .cfg.width = _width, \
/linux/drivers/clk/meson/
H A Dmeson-clkc-utils.h71 #define MESON_COMP_DIV(_prefix, _name, _reg, _shift, _width, \ argument
77 .width = (_width), \

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