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/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-common.h1439 #define XGMAC_IOREAD(_pdata, _reg) \ argument
1440 ioread32((_pdata)->xgmac_regs + _reg)
1442 #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \ argument
1443 GET_BITS(XGMAC_IOREAD((_pdata), _reg), \
1444 _reg##_##_field##_INDEX, \
1445 _reg##_##_field##_WIDTH)
1447 #define XGMAC_IOWRITE(_pdata, _reg, _val) \ argument
1448 iowrite32((_val), (_pdata)->xgmac_regs + _reg)
1450 #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ argument
1452 u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \
[all …]
/linux/drivers/clk/sophgo/
H A Dclk-cv18xx-common.h45 #define CV1800_CLK_BIT(_reg, _shift) \ argument
47 .reg = _reg, \
51 #define CV1800_CLK_REG(_reg, _shift, _width, _initval, _flags) \ argument
53 .reg = _reg, \
60 #define cv1800_clk_regfield_genmask(_reg) \ argument
61 GENMASK((_reg)->shift + (_reg)->width - 1, (_reg)->shift)
62 #define cv1800_clk_regfield_get(_val, _reg) \ argument
63 (((_val) >> (_reg)->shift) & GENMASK((_reg)->width - 1, 0))
64 #define cv1800_clk_regfield_set(_val, _new, _reg) \ argument
65 (((_val) & ~cv1800_clk_regfield_genmask((_reg))) | \
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H A Dclk-cv18xx-pll.h50 #define PLL_GET_PRE_DIV_SEL(_reg) \ argument
51 FIELD_GET(_PLL_PRE_DIV_SEL_FIELD, (_reg))
52 #define PLL_GET_POST_DIV_SEL(_reg) \ argument
53 FIELD_GET(_PLL_POST_DIV_SEL_FIELD, (_reg))
54 #define PLL_GET_SEL_MODE(_reg) \ argument
55 FIELD_GET(_PLL_SEL_MODE_FIELD, (_reg))
56 #define PLL_GET_DIV_SEL(_reg) \ argument
57 FIELD_GET(_PLL_DIV_SEL_FIELD, (_reg))
58 #define PLL_GET_ICTRL(_reg) \ argument
59 FIELD_GET(_PLL_ICTRL_FIELD, (_reg))
[all …]
/linux/drivers/clk/sunxi-ng/
H A Dccu_div.h87 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
95 .reg = _reg, \
104 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
107 SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
111 #define SUNXI_CCU_DIV_TABLE_HW(_struct, _name, _parent, _reg, \ argument
118 .reg = _reg, \
129 _reg, \ argument
138 .reg = _reg, \
148 _reg, \ argument
157 .reg = _reg, \
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H A Dccu_mp.h34 #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ argument
46 .reg = _reg, \
56 _reg, \ argument
68 .reg = _reg, \
77 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
88 .reg = _reg, \
96 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument
101 SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
107 #define SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(_struct, _name, _parents, _reg, \ argument
120 .reg = _reg, \
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H A Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
23 .reg = _reg, \
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
35 .reg = _reg, \
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
47 .reg = _reg, \
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
63 .reg = _reg, \
71 #define SUNXI_CCU_GATE_HWS_WITH_PREDIV(_struct, _name, _parent, _reg, \ argument
76 .reg = _reg, \
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H A Dccu_nm.h38 #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
52 .reg = _reg, \
61 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
76 .reg = _reg, \
86 _reg, _min_rate, \ argument
102 .reg = _reg, \
112 _parent, _reg, \ argument
132 .reg = _reg, \
142 _parent, _reg, \ argument
151 _parent, _reg, \
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/linux/drivers/clk/sprd/
H A Dcomposite.h21 #define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ argument
29 .reg = _reg, \
35 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument
37 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
41 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument
43 SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, NULL, \
46 #define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table, \ argument
49 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
54 #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \ argument
56 SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, NULL, \
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H A Dpll.h64 #define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
79 .reg = _reg, \
85 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ argument
88 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
92 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \ argument
95 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
99 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \ argument
101 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
105 #define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \ argument
108 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
[all …]
H A Dmux.h40 _reg, _shift, _width, _flags, _fn) \ argument
45 .reg = _reg, \
52 _reg, _shift, _width, _flags) \ argument
54 _reg, _shift, _width, _flags, \
57 #define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \ argument
60 _reg, _shift, _width, _flags)
63 _reg, _shift, _width, _flags) \ argument
65 _reg, _shift, _width, _flags, \
68 #define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg, \ argument
71 _reg, _shift, _width, _flags)
H A Ddiv.h40 #define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _offset, \ argument
46 .reg = _reg, \
52 #define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \ argument
54 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, 0x0, \
57 #define SPRD_DIV_CLK_FW_NAME(_struct, _name, _parent, _reg, \ argument
59 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, 0x0, \
62 #define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \ argument
64 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, 0x0, \
/linux/drivers/regulator/
H A Dmc13xxx.h55 #define MC13xxx_DEFINE(prefix, _name, _node, _reg, _vsel_reg, _voltages, _ops) \ argument
66 .reg = prefix ## _reg, \
67 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
73 #define MC13xxx_FIXED_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument
84 .reg = prefix ## _reg, \
85 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
88 #define MC13xxx_GPO_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument
99 .reg = prefix ## _reg, \
100 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
103 #define MC13xxx_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages, ops) \ argument
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/linux/drivers/clk/meson/
H A Dmeson-clkc-utils.h30 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pdata, _flags) \ argument
33 .offset = (_reg), \
45 #define MESON_PCLK(_name, _reg, _bit, _pdata, _flags) \ argument
46 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pdata, _flags)
48 #define MESON_PCLK_RO(_name, _reg, _bit, _pdata, _flags) \ argument
49 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pdata, _flags)
52 #define MESON_COMP_SEL(_prefix, _name, _reg, _shift, _mask, _pdata, \ argument
56 .offset = (_reg), \
71 #define MESON_COMP_DIV(_prefix, _name, _reg, _shift, _width, \ argument
75 .offset = (_reg), \
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/linux/drivers/clk/pistachio/
H A Dclk.h19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
22 .reg = _reg, \
39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
42 .reg = _reg, \
59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
62 .reg = _reg, \
69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
72 .reg = _reg, \
119 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ argument
122 .reg_base = _reg, \
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/linux/drivers/clk/x86/
H A Dclk-cgu.h118 _reg, _type) \ argument
125 .reg = _reg, \
146 #define LGM_DDIV(_id, _name, _pname, _flags, _reg, \ argument
157 .reg = _reg, \
203 #define LGM_MUX(_id, _name, _pdata, _f, _reg, \ argument
212 .mux_off = _reg, \
219 #define LGM_DIV(_id, _name, _pname, _f, _reg, _shift, _width, \ argument
231 .div_off = _reg, \
241 #define LGM_GATE(_id, _name, _pname, _f, _reg, \ argument
253 .gate_off = _reg, \
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/linux/drivers/clk/mediatek/
H A Dclk-mtk.h114 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument
118 .mux_reg = _reg, \
121 .gate_reg = _reg, \
134 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
136 MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \
143 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
144 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
147 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
148 MUX_FLAGS(_id, _name, _parents, _reg, \
151 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ argument
[all …]
/linux/drivers/clk/actions/
H A Dowl-pll.h41 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ argument
44 .reg = _reg, \
55 #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \ argument
58 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
70 #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
73 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
84 #define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
88 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
H A Dowl-gate.h27 #define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \ argument
29 .reg = _reg, \
34 #define OWL_GATE(_struct, _name, _parent, _reg, \ argument
37 .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
47 #define OWL_GATE_NO_PARENT(_struct, _name, _reg, \ argument
50 .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
/linux/drivers/dpll/zl3073x/
H A Dregs.h30 #define ZL_REG_OFFSET(_reg) FIELD_GET(ZL_REG_OFFSET_MASK, _reg) argument
31 #define ZL_REG_PAGE(_reg) FIELD_GET(ZL_REG_PAGE_MASK, _reg) argument
32 #define ZL_REG_MAX_OFFSET(_reg) FIELD_GET(ZL_REG_MAX_OFFSET_MASK, _reg) argument
33 #define ZL_REG_SIZE(_reg) FIELD_GET(ZL_REG_SIZE_MASK, _reg) argument
34 #define ZL_REG_ADDR(_reg) FIELD_GET(ZL_REG_ADDR_MASK, _reg) argument
/linux/tools/testing/selftests/powerpc/mm/
H A Dlarge_vm_gpr_corruption.c54 #define CHECK_REG(_reg) \ argument
55 if (_reg != _reg##_orig) { \
56 printf(str(_reg) " corrupted! Expected 0x%lx != 0x%lx\n", _reg##_orig, \
57 _reg); \
/linux/drivers/media/tuners/
H A Dmc44s803_priv.h179 #define MC44S803_REG_SM(_val, _reg) \ argument
180 (((_val) << _reg##_S) & (_reg))
183 #define MC44S803_REG_MS(_val, _reg) \ argument
184 (((_val) & (_reg)) >> _reg##_S)
/linux/drivers/gpu/drm/i915/gvt/
H A Dreg.h76 #define REG_50080_TO_PIPE(_reg) ({ \ argument
77 typeof(_reg) (reg) = (_reg); \
83 #define REG_50080_TO_PLANE(_reg) ({ \ argument
84 typeof(_reg) (reg) = (_reg); \
/linux/include/linux/
H A Dsh_clk.h151 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ argument
154 .enable_reg = (void __iomem *)_reg, \
175 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ argument
178 .enable_reg = (void __iomem *)_reg, \
188 #define SH_CLK_DIV6(_parent, _reg, _flags) \ argument
191 .enable_reg = (void __iomem *)_reg, \
205 #define SH_CLK_FSIDIV(_reg, _parent) \ argument
207 .enable_reg = (void __iomem *)_reg, \
/linux/drivers/reset/sti/
H A Dreset-stih407.c57 #define STIH407_SRST_CORE(_reg, _bit) \ argument
58 _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
60 #define STIH407_SRST_SBC(_reg, _bit) \ argument
61 _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
63 #define STIH407_SRST_LPM(_reg, _bit) \ argument
64 _SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit)
/linux/drivers/net/wireless/ath/ath5k/
H A Dath5k.h124 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ argument
125 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
126 (((_val) << _flags##_S) & (_flags)), _reg)
128 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ argument
129 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
130 (_mask)) | (_flags), _reg)
132 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ argument
133 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
135 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ argument
136 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
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