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Searched refs:_offset (Results 1 – 25 of 88) sorted by relevance

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/linux/drivers/clk/bcm/
H A Dclk-kona.h91 #define POLICY(_offset, _bit) \ argument
93 .offset = (_offset), \
151 #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
153 .offset = (_offset), \
163 #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
165 .offset = (_offset), \
174 #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
176 .offset = (_offset), \
185 #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ argument
187 .offset = (_offset), \
[all …]
/linux/drivers/clk/tegra/
H A Dclk-tegra-periph.c132 #define MUX(_name, _parents, _offset, \ argument
134 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
139 #define MUX_FLAGS(_name, _parents, _offset,\ argument
141 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
146 #define MUX8(_name, _parents, _offset, \ argument
148 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
153 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
154 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
159 #define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \ argument
160 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
[all …]
H A Dclk-tegra-audio.c52 #define AUDIO(_name, _offset) \ argument
56 .offset = _offset,\
71 #define AUDIO2X(_name, _num, _offset) \ argument
79 .div_offset = _offset,\
/linux/drivers/net/ethernet/mellanox/mlxsw/
H A Ditem.h270 #define MLXSW_ITEM8(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
272 .offset = _offset, \
288 #define MLXSW_ITEM8_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
291 .offset = _offset, \
313 #define MLXSW_ITEM16(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
315 .offset = _offset, \
331 #define MLXSW_ITEM16_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
334 .offset = _offset, \
356 #define MLXSW_ITEM32(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
358 .offset = _offset, \
[all …]
H A Dspectrum_acl.c538 #define MLXSW_SP_ACL_MANGLE_ACTION(_htype, _offset, _mask, _shift, _field) \
541 .offset = _offset, \ argument
547 #define MLXSW_SP_ACL_MANGLE_ACTION_IP4(_offset, _mask, _shift, _field) \
549 _offset, _mask, _shift, _field) argument
551 #define MLXSW_SP_ACL_MANGLE_ACTION_IP6(_offset, _mask, _shift, _field) \
553 _offset, _mask, _shift, _field)
555 #define MLXSW_SP_ACL_MANGLE_ACTION_TCP(_offset, _mask, _shift, _field) \
556 MLXSW_SP_ACL_MANGLE_ACTION(FLOW_ACT_MANGLE_HDR_TYPE_TCP, _offset, _mask, _shift, _field)
558 #define MLXSW_SP_ACL_MANGLE_ACTION_UDP(_offset, _mask, _shift, _field) \
559 MLXSW_SP_ACL_MANGLE_ACTION(FLOW_ACT_MANGLE_HDR_TYPE_UDP, _offset, _mas
532 MLXSW_SP_ACL_MANGLE_ACTION(_htype,_offset,_mask,_shift,_field) global() argument
545 MLXSW_SP_ACL_MANGLE_ACTION_IP6(_offset,_mask,_shift,_field) global() argument
552 MLXSW_SP_ACL_MANGLE_ACTION_UDP(_offset,_mask,_shift,_field) global() argument
[all...]
/linux/drivers/clk/renesas/
H A Drzv2h-cpg.h28 #define PLL_PACK_LIMITS(_offset, _has_clkn, _instance, _limits) \ argument
30 .offset = _offset, \
36 #define PLL_PACK(_offset, _has_clkn, _instance) \ argument
37 PLL_PACK_LIMITS(_offset, _has_clkn, _instance, NULL)
68 #define DDIV_PACK(_offset, _shift, _width, _monbit) \ argument
70 .offset = _offset, \
76 #define DDIV_PACK_NO_RMW(_offset, _shift, _width, _monbit) \ argument
78 .offset = (_offset), \
98 #define SMUX_PACK(_offset, _shift, _width) \ argument
100 .offset = (_offset), \
/linux/drivers/clk/
H A Dclk-loongson2.c59 #define CLK_DIV(_id, _name, _pname, _offset, _dshift, _dwidth) \ argument
65 .reg_offset = _offset, \
70 #define CLK_PLL(_id, _name, _offset, _mshift, _mwidth, \ argument
77 .reg_offset = _offset, \
84 #define CLK_SCALE(_id, _name, _pname, _offset, \ argument
91 .reg_offset = _offset, \
96 #define CLK_SCALE_MODE(_id, _name, _pname, _offset, \ argument
103 .reg_offset = _offset, \
109 #define CLK_GATE(_id, _name, _pname, _offset, _bidx) \ argument
115 .reg_offset = _offset, \
[all …]
/linux/drivers/clk/sunxi-ng/
H A Dccu_mult.h17 #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \ argument
21 .offset = _offset, \
29 #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \ argument
30 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, 1, 0)
/linux/drivers/bcma/
H A Dsprom.c185 #define SPEX(_field, _offset, _mask, _shift) \ argument
186 bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift))
188 #define SPEX32(_field, _offset, _mask, _shift) \ argument
189 bus->sprom._field = ((((u32)sprom[SPOFF((_offset)+2)] << 16 | \
190 sprom[SPOFF(_offset)]) & (_mask)) >> (_shift))
192 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
194 SPEX(_field[0], _offset + 0, _mask, _shift); \
195 SPEX(_field[1], _offset + 2, _mask, _shift); \
196 SPEX(_field[2], _offset + 4, _mask, _shift); \
197 SPEX(_field[3], _offset + 6, _mask, _shift); \
[all …]
/linux/include/crypto/
H A Dkrb5.h120 size_t data_size, size_t *_offset);
123 size_t *_buffer_size, size_t *_offset);
126 size_t *_offset, size_t *_len);
145 size_t *_offset, size_t *_len);
156 size_t *_offset, size_t *_len);
/linux/drivers/clk/sprd/
H A Ddiv.h28 #define _SPRD_DIV_CLK(_offset, _shift, _width) \ argument
30 .offset = _offset, \
40 #define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _offset, \ argument
43 .div = _SPRD_DIV_CLK(_offset, _shift, _width), \
/linux/arch/riscv/include/asm/
H A Dvdso.h36 (void __user *)((unsigned long)(base) + __vdso_##name##_offset))
39 ((void __user *)((unsigned long)(base) + __vdso_##name##_offset))
46 (void __user *)((unsigned long)(base) + compat__vdso_##name##_offset)
/linux/drivers/net/wireless/mediatek/mt76/
H A Ddma.h107 u32 _offset = offsetof(struct mt76_queue_regs, _field); \
109 if (!mt76_dma_handle_read(_q, _offset, &_val)) \
115 u32 _offset = offsetof(struct mt76_queue_regs, _field); \
116 if (!mt76_dma_handle_write(_q, _offset, _val)) \
/linux/tools/testing/selftests/vfio/lib/include/libvfio/
H A Dvfio_pci_device.h52 #define vfio_pci_config_read(_device, _offset, _type) ({ \ argument
54 vfio_pci_config_access((_device), false, _offset, sizeof(__data), &__data); \
62 #define vfio_pci_config_write(_device, _offset, _value, _type) do { \ argument
64 vfio_pci_config_access((_device), true, _offset, sizeof(_type), &__data); \
/linux/tools/testing/selftests/powerpc/nx-gzip/include/
H A Dnxu.h428 #define getnn(ST, REG) ((be32toh(ST.REG) >> (31-REG##_offset)) \
430 #define getpnn(ST, REG) ((be32toh((ST)->REG) >> (31-REG##_offset)) \
438 << (31-REG##_offset)))
442 << (31-REG##_offset)))
453 & REG##_mask) << (31-REG##_offset))))
455 | (((X) & REG##_mask) << (31-REG##_offset))))
/linux/drivers/ssb/
H A Dpci.c171 #define SPEX16(_outvar, _offset, _mask, _shift) \ argument
172 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
173 #define SPEX32(_outvar, _offset, _mask, _shift) \ argument
174 out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
175 in[SPOFF(_offset)]) & (_mask)) >> (_shift))
176 #define SPEX(_outvar, _offset, _mask, _shift) \ argument
177 SPEX16(_outvar, _offset, _mask, _shift)
179 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
181 SPEX(_field[0], _offset + 0, _mask, _shift); \
182 SPEX(_field[1], _offset + 2, _mask, _shift); \
[all …]
/linux/drivers/dpll/zl3073x/
H A Dregs.h61 #define ZL_REG_IDX(_idx, _page, _offset, _size, _items, _stride) \ argument
63 (_offset) + (_idx) * (_stride)) | \
67 (_offset) + ((_items) - 1) * (_stride)))
77 #define ZL_REG(_page, _offset, _size) \ argument
78 ZL_REG_IDX(0, _page, _offset, _size, 1, 0)
/linux/drivers/pinctrl/berlin/
H A Dberlin.h31 #define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \ argument
34 .offset = _offset, \
/linux/drivers/clk/st/
H A Dclkgen.h38 #define CLKGEN_FIELD(_offset, _mask, _shift) { \ argument
39 .offset = _offset, \
/linux/tools/objtool/include/objtool/
H A Delf.h558 #define for_offset_range(_offset, _start, _end) \
559 for (_offset = ((_start) & OFFSET_STRIDE_MASK); \
560 _offset >= ((_start) & OFFSET_STRIDE_MASK) && \
561 _offset <= ((_end) & OFFSET_STRIDE_MASK); \
562 _offset += OFFSET_STRIDE)
355 for_offset_range(_offset,_start,_end) global() argument
/linux/arch/powerpc/boot/
H A Dlibfdt-wrapper.c33 unsigned long _offset = (off); \
34 check_err(_offset) ? NULL : (void *)(_offset+1); \
/linux/drivers/clk/microchip/
H A Dclk-mpfs-ccc.c102 #define CLK_CCC_PLL(_id, _parents, _shift, _width, _flags, _offset) { \ argument
106 .reg_offset = _offset, \
125 #define CLK_CCC_OUT(_id, _shift, _width, _flags, _offset) { \ argument
129 .reg_offset = _offset, \
H A Dclk-mpfs.c166 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ argument
171 .reg_offset = _offset, \
205 #define CLK_PLL_OUT(_id, _name, _parent, _flags, _shift, _width, _offset) { \ argument
210 .reg_offset = _offset, \
299 #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ argument
304 .cfg.map_offset = _offset, \
/linux/drivers/clk/stm32/
H A Dclk-stm32mp13.c140 #define _CFG_GATE(_id, _offset, _bit_idx, _offset_clr)\ argument
142 .offset = (_offset),\
147 #define CFG_GATE(_id, _offset, _bit_idx)\ argument
148 _CFG_GATE(_id, _offset, _bit_idx, 0)
150 #define CFG_GATE_SETCLR(_id, _offset, _bit_idx)\ argument
151 _CFG_GATE(_id, _offset, _bit_idx, RCC_CLR_OFFSET)
290 #define CFG_DIV(_id, _offset, _shift, _width, _flags, _table, _ready)\ argument
292 .offset = (_offset),\
352 #define _CFG_MUX(_id, _offset, _shift, _witdh, _ready, _flags)\ argument
354 .offset = (_offset),\
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/
H A Defuse.h74 void read_efuse_byte(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
79 void read_efuse(struct ieee80211_hw *hw, u16 _offset,

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