| /linux/drivers/clk/actions/ |
| H A D | owl-pll.h | 41 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ argument
46 .bit_idx = _bit_idx, \
55 #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \ argument
58 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
70 #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
73 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
84 #define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
88 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
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| H A D | owl-gate.h | 27 #define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \ argument
30 .bit_idx = _bit_idx, \
35 _bit_idx, _gate_flags, _flags) \ argument
37 .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
48 _bit_idx, _gate_flags, _flags) \ argument
50 .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
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| /linux/drivers/clk/ |
| H A D | clk-stm32h7.c | 598 #define OSC_CLKF(_name, _parent, _gate_offset, _bit_idx, _bit_rdy, _flags)\ argument
603 .bit_idx = _bit_idx,\
608 #define OSC_CLK(_name, _parent, _gate_offset, _bit_idx, _bit_rdy)\ argument
609 OSC_CLKF(_name, _parent, _gate_offset, _bit_idx, _bit_rdy, 0)
937 #define M_ODF_F(_name, _parent, _gate_offset, _bit_idx, _rate_offset,\ argument
942 .gate = &(struct gate_cfg) {_gate_offset, _bit_idx },\
949 #define M_ODF(_name, _parent, _gate_offset, _bit_idx, _rate_offset,\ argument
951 M_ODF_F(_name, _parent, _gate_offset, _bit_idx, _rate_offset,\
985 #define PER_CLKF(_gate_offset, _bit_idx, _name, _parent, _flags)\ argument
988 .bit_idx = _bit_idx,\
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| /linux/drivers/clk/keystone/ |
| H A D | syscon-clk.c | 160 #define TI_SYSCON_CLK_GATE(_name, _offset, _bit_idx) \ argument
164 .bit_idx = (_bit_idx), \
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| /linux/drivers/clk/sophgo/ |
| H A D | clk-sg2042-clkgen.c | 374 _r_enable, _bit_idx) { \ argument
382 .bit_idx = _bit_idx, \
386 _r_enable, _bit_idx) { \ argument
394 .bit_idx = _bit_idx, \
398 _r_enable, _bit_idx) { \ argument
406 .bit_idx = _bit_idx, \
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| H A D | clk-sg2042-rpgate.c | 73 _r_enable, _bit_idx) { \ argument
81 .bit_idx = _bit_idx, \
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| /linux/drivers/clk/stm32/ |
| H A D | clk-stm32mp13.c | 140 #define _CFG_GATE(_id, _offset, _bit_idx, _offset_clr)\ argument
143 .bit_idx = (_bit_idx),\
147 #define CFG_GATE(_id, _offset, _bit_idx)\ argument
148 _CFG_GATE(_id, _offset, _bit_idx, 0)
150 #define CFG_GATE_SETCLR(_id, _offset, _bit_idx)\ argument
151 _CFG_GATE(_id, _offset, _bit_idx, RCC_CLR_OFFSET)
471 #define SECF(_sec_id, _offset, _bit_idx)[_sec_id] = {\ argument
473 .bit_idx = _bit_idx,\
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| H A D | clk-stm32mp1.c | 1170 #define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ argument
1178 .bit_idx = _bit_idx,\
1261 #define STM32_TIM(_id, _name, _parent, _offset_set, _bit_idx)\ argument
1263 _offset_set, _bit_idx, 0)
1311 #define GATE_MP1(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ argument
1313 _GATE_MP1(_offset, _bit_idx, _gate_flags))
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| H A D | clk-stm32mp25.c | 342 #define GATE_CFG(id, _offset, _bit_idx, _offset_clr) \ argument
345 .bit_idx = (_bit_idx), \
1829 #define RESET_MP25(id, _offset, _bit_idx, _set_clr) \ argument
1832 .bit_idx = (_bit_idx), \
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