1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013-2014 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 *
6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
7 */
8
9 #include "adreno_gpu.h"
10 #include "a6xx_gpu.h"
11 #include "a6xx.xml.h"
12 #include "a6xx_gmu.xml.h"
13
14 static const struct adreno_reglist a612_hwcg[] = {
15 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
16 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
17 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081},
18 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
19 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
20 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
21 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
22 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
23 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
24 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
25 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
26 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
27 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
28 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
29 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
30 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
31 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
32 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222},
33 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
34 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
35 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022},
36 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
37 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
38 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
39 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
40 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
41 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
42 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
43 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
44 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
45 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
46 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
47 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
48 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
49 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
50 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
51 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
52 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
53 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
54 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
55 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
56 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
57 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
58 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
59 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
60 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
61 {},
62 };
63
64 /* For a615 family (a615, a616, a618 and a619) */
65 static const struct adreno_reglist a615_hwcg[] = {
66 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
67 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
68 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
69 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
70 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
71 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
72 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
73 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
74 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
75 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
76 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
77 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
78 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
79 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
80 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
81 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
82 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
83 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
84 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
85 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
86 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
87 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
88 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
89 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
90 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
91 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
92 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
93 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
94 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
95 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
96 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
97 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
98 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
99 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
100 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
101 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
102 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002020},
103 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
104 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
105 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
106 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
107 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00},
108 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00},
109 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00},
110 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
111 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
112 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
113 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
114 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
115 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
116 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
117 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
118 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
119 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
120 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
121 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
122 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
123 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
124 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
125 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
126 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
127 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
128 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
129 {},
130 };
131
132 static const struct adreno_reglist a620_hwcg[] = {
133 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
134 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
135 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
136 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
137 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
138 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
139 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
140 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
141 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
142 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
143 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
144 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
145 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
146 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
147 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
148 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
149 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
150 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
151 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
152 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
153 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
154 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
155 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
156 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
157 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
158 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
159 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
160 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
161 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
162 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
163 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
164 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
165 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
166 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
167 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
168 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
169 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
170 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
171 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
172 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
173 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
174 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
175 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
176 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
177 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
178 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
179 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
180 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
181 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
182 {},
183 };
184
185 static const struct adreno_reglist a630_hwcg[] = {
186 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
187 {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
188 {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
189 {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
190 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
191 {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
192 {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
193 {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
194 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
195 {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
196 {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
197 {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
198 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
199 {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf},
200 {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf},
201 {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf},
202 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
203 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
204 {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
205 {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
206 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
207 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
208 {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
209 {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
210 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
211 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
212 {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
213 {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
214 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
215 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
216 {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
217 {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
218 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
219 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
220 {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
221 {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
222 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
223 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
224 {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
225 {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
226 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
227 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
228 {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
229 {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
230 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
231 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
232 {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
233 {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
234 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
235 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
236 {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
237 {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
238 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
239 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
240 {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
241 {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
242 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
243 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
244 {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
245 {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
246 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
247 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
248 {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
249 {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
250 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
251 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
252 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
253 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
254 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
255 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
256 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
257 {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
258 {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
259 {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
260 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
261 {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
262 {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
263 {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
264 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
265 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
266 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
267 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
268 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
269 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00},
270 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00},
271 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00},
272 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
273 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
274 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
275 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
276 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
277 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
278 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
279 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
280 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
281 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
282 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
283 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
284 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
285 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
286 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
287 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
288 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
289 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
290 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
291 {},
292 };
293
294 static const struct adreno_reglist a640_hwcg[] = {
295 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
296 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
297 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
298 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
299 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
300 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
301 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
302 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
303 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
304 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
305 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
306 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
307 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
308 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
309 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
310 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
311 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
312 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
313 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
314 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
315 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
316 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
317 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
318 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
319 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
320 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
321 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
322 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
323 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
324 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
325 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
326 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
327 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
328 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
329 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
330 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
331 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
332 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
333 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
334 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
335 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
336 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
337 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
338 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
339 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
340 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
341 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
342 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
343 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
344 {},
345 };
346
347 static const struct adreno_reglist a650_hwcg[] = {
348 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
349 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
350 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
351 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
352 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
353 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
354 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
355 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
356 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
357 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
358 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
359 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
360 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
361 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
362 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
363 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
364 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
365 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
366 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
367 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
368 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
369 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
370 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
371 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
372 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
373 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
374 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
375 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
376 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
377 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
378 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
379 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
380 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
381 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
382 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
383 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
384 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
385 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
386 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
387 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
388 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
389 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
390 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
391 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
392 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
393 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
394 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
395 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
396 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
397 {},
398 };
399
400 static const struct adreno_reglist a660_hwcg[] = {
401 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
402 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
403 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
404 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
405 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
406 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
407 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
408 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
409 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
410 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
411 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
412 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
413 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
414 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
415 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
416 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
417 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
418 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
419 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
420 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
421 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
422 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
423 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
424 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
425 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
426 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
427 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
428 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
429 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
430 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
431 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
432 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
433 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
434 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
435 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
436 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
437 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
438 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
439 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
440 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
441 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
442 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
443 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
444 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
445 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
446 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
447 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
448 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
449 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
450 {},
451 };
452
453 static const struct adreno_reglist a690_hwcg[] = {
454 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
455 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
456 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
457 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
458 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
459 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
460 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
461 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
462 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
463 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
464 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
465 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
466 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
467 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
468 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
469 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
470 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
471 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
472 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
473 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
474 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
475 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
476 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
477 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
478 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
479 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
480 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
481 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
482 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
483 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
484 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
485 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
486 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
487 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
488 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
489 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
490 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
491 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
492 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
493 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
494 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
495 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
496 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
497 {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
498 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
499 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
500 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
501 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
502 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
503 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
504 {}
505 };
506
507 /* For a615, a616, a618, a619, a630, a640 and a680 */
508 static const u32 a630_protect_regs[] = {
509 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
510 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
511 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
512 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
513 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
514 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
515 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
516 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
517 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
518 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
519 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
520 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
521 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
522 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
523 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
524 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
525 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
526 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
527 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
528 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
529 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
530 A6XX_PROTECT_NORDWR(0x09e70, 0x0001),
531 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
532 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
533 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
534 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
535 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
536 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
537 A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
538 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
539 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
540 A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */
541 };
542 DECLARE_ADRENO_PROTECT(a630_protect, 32);
543
544 static const u32 a650_protect_regs[] = {
545 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
546 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
547 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
548 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
549 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
550 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
551 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
552 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
553 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
554 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
555 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
556 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
557 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
558 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
559 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
560 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
561 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
562 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
563 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
564 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
565 A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
566 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
567 A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
568 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
569 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
570 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
571 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
572 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
573 A6XX_PROTECT_NORDWR(0x0b608, 0x0007),
574 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
575 A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
576 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
577 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
578 A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
579 A6XX_PROTECT_NORDWR(0x1a800, 0x1fff),
580 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
581 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
582 A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
583 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
584 };
585 DECLARE_ADRENO_PROTECT(a650_protect, 48);
586
587 /* These are for a635 and a660 */
588 static const u32 a660_protect_regs[] = {
589 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
590 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
591 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
592 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
593 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
594 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
595 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
596 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
597 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
598 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
599 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
600 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
601 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
602 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
603 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
604 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
605 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
606 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
607 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
608 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
609 A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
610 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
611 A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
612 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
613 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
614 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
615 A6XX_PROTECT_NORDWR(0x0ae50, 0x012f),
616 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
617 A6XX_PROTECT_NORDWR(0x0b608, 0x0006),
618 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
619 A6XX_PROTECT_NORDWR(0x0be20, 0x015f),
620 A6XX_PROTECT_NORDWR(0x0d000, 0x05ff),
621 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
622 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
623 A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
624 A6XX_PROTECT_NORDWR(0x1a400, 0x1fff),
625 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
626 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
627 A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
628 A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
629 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
630 };
631 DECLARE_ADRENO_PROTECT(a660_protect, 48);
632
633 /* These are for a690 */
634 static const u32 a690_protect_regs[] = {
635 A6XX_PROTECT_RDONLY(0x00000, 0x004ff),
636 A6XX_PROTECT_RDONLY(0x00501, 0x00001),
637 A6XX_PROTECT_RDONLY(0x0050b, 0x002f4),
638 A6XX_PROTECT_NORDWR(0x0050e, 0x00000),
639 A6XX_PROTECT_NORDWR(0x00510, 0x00000),
640 A6XX_PROTECT_NORDWR(0x00534, 0x00000),
641 A6XX_PROTECT_NORDWR(0x00800, 0x00082),
642 A6XX_PROTECT_NORDWR(0x008a0, 0x00008),
643 A6XX_PROTECT_NORDWR(0x008ab, 0x00024),
644 A6XX_PROTECT_RDONLY(0x008de, 0x000ae),
645 A6XX_PROTECT_NORDWR(0x00900, 0x0004d),
646 A6XX_PROTECT_NORDWR(0x0098d, 0x00272),
647 A6XX_PROTECT_NORDWR(0x00e00, 0x00001),
648 A6XX_PROTECT_NORDWR(0x00e03, 0x0000c),
649 A6XX_PROTECT_NORDWR(0x03c00, 0x000c3),
650 A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff),
651 A6XX_PROTECT_NORDWR(0x08630, 0x001cf),
652 A6XX_PROTECT_NORDWR(0x08e00, 0x00000),
653 A6XX_PROTECT_NORDWR(0x08e08, 0x00007),
654 A6XX_PROTECT_NORDWR(0x08e50, 0x0001f),
655 A6XX_PROTECT_NORDWR(0x08e80, 0x0027f),
656 A6XX_PROTECT_NORDWR(0x09624, 0x001db),
657 A6XX_PROTECT_NORDWR(0x09e60, 0x00011),
658 A6XX_PROTECT_NORDWR(0x09e78, 0x00187),
659 A6XX_PROTECT_NORDWR(0x0a630, 0x001cf),
660 A6XX_PROTECT_NORDWR(0x0ae02, 0x00000),
661 A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f),
662 A6XX_PROTECT_NORDWR(0x0b604, 0x00000),
663 A6XX_PROTECT_NORDWR(0x0b608, 0x00006),
664 A6XX_PROTECT_NORDWR(0x0be02, 0x00001),
665 A6XX_PROTECT_NORDWR(0x0be20, 0x0015f),
666 A6XX_PROTECT_NORDWR(0x0d000, 0x005ff),
667 A6XX_PROTECT_NORDWR(0x0f000, 0x00bff),
668 A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff),
669 A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */
670 };
671 DECLARE_ADRENO_PROTECT(a690_protect, 48);
672
673 static const struct adreno_reglist a640_gbif[] = {
674 { REG_A6XX_GBIF_QSB_SIDE0, 0x00071620 },
675 { REG_A6XX_GBIF_QSB_SIDE1, 0x00071620 },
676 { REG_A6XX_GBIF_QSB_SIDE2, 0x00071620 },
677 { REG_A6XX_GBIF_QSB_SIDE3, 0x00071620 },
678 { },
679 };
680
681 static const struct adreno_info a6xx_gpus[] = {
682 {
683 .chip_ids = ADRENO_CHIP_IDS(0x06010000),
684 .family = ADRENO_6XX_GEN1,
685 .revn = 610,
686 .fw = {
687 [ADRENO_FW_SQE] = "a630_sqe.fw",
688 },
689 .gmem = (SZ_128K + SZ_4K),
690 .quirks = ADRENO_QUIRK_4GB_VA,
691 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
692 .funcs = &a6xx_gmuwrapper_funcs,
693 .zapfw = "a610_zap.mdt",
694 .a6xx = &(const struct a6xx_info) {
695 .hwcg = a612_hwcg,
696 .protect = &a630_protect,
697 .gbif_cx = a640_gbif,
698 .gmu_cgc_mode = 0x00020202,
699 .prim_fifo_threshold = 0x00080000,
700 },
701 /*
702 * There are (at least) three SoCs implementing A610: SM6125
703 * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does
704 * not have speedbinning, as only a single SKU exists and we
705 * don't support khaje upstream yet. Hence, this matching
706 * table is only valid for bengal.
707 */
708 .speedbins = ADRENO_SPEEDBINS(
709 { 0, 0 },
710 { 206, 1 },
711 { 200, 2 },
712 { 157, 3 },
713 { 127, 4 },
714 ),
715 }, {
716 .chip_ids = ADRENO_CHIP_IDS(0x06010200),
717 .family = ADRENO_6XX_GEN1,
718 .fw = {
719 [ADRENO_FW_SQE] = "a630_sqe.fw",
720 [ADRENO_FW_GMU] = "a612_rgmu.bin",
721 },
722 .gmem = (SZ_128K + SZ_4K),
723 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
724 .funcs = &a6xx_gmuwrapper_funcs,
725 .a6xx = &(const struct a6xx_info) {
726 .hwcg = a612_hwcg,
727 .protect = &a630_protect,
728 .gmu_cgc_mode = 0x00000022,
729 .prim_fifo_threshold = 0x00080000,
730 },
731 }, {
732 .chip_ids = ADRENO_CHIP_IDS(0x06010500),
733 .family = ADRENO_6XX_GEN1,
734 .revn = 615,
735 .fw = {
736 [ADRENO_FW_SQE] = "a630_sqe.fw",
737 [ADRENO_FW_GMU] = "a630_gmu.bin",
738 },
739 .gmem = SZ_512K,
740 .quirks = ADRENO_QUIRK_4GB_VA,
741 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
742 .funcs = &a6xx_gpu_funcs,
743 .zapfw = "a615_zap.mdt",
744 .a6xx = &(const struct a6xx_info) {
745 .hwcg = a615_hwcg,
746 .protect = &a630_protect,
747 .gmu_cgc_mode = 0x00000222,
748 .prim_fifo_threshold = 0x0018000,
749 },
750 .speedbins = ADRENO_SPEEDBINS(
751 /*
752 * The default speed bin (0) has the same values as
753 * speed bin 90 which goes up to 432 MHz.
754 */
755 { 0, 0 },
756 { 90, 0 },
757 { 105, 1 },
758 { 146, 2 },
759 { 163, 3 },
760 ),
761 }, {
762 .machine = "qcom,sm7150",
763 .chip_ids = ADRENO_CHIP_IDS(0x06010800),
764 .family = ADRENO_6XX_GEN1,
765 .fw = {
766 [ADRENO_FW_SQE] = "a630_sqe.fw",
767 [ADRENO_FW_GMU] = "a630_gmu.bin",
768 },
769 .gmem = SZ_512K,
770 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
771 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
772 ADRENO_QUIRK_4GB_VA,
773 .funcs = &a6xx_gpu_funcs,
774 .zapfw = "a615_zap.mbn",
775 .a6xx = &(const struct a6xx_info) {
776 .hwcg = a615_hwcg,
777 .protect = &a630_protect,
778 .gmu_cgc_mode = 0x00000222,
779 .prim_fifo_threshold = 0x00180000,
780 },
781 .speedbins = ADRENO_SPEEDBINS(
782 { 0, 0 },
783 { 128, 1 },
784 { 146, 2 },
785 { 167, 3 },
786 { 172, 4 },
787 ),
788 }, {
789 .chip_ids = ADRENO_CHIP_IDS(0x06010800),
790 .family = ADRENO_6XX_GEN1,
791 .revn = 618,
792 .fw = {
793 [ADRENO_FW_SQE] = "a630_sqe.fw",
794 [ADRENO_FW_GMU] = "a630_gmu.bin",
795 },
796 .gmem = SZ_512K,
797 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
798 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
799 ADRENO_QUIRK_4GB_VA,
800 .funcs = &a6xx_gpu_funcs,
801 .a6xx = &(const struct a6xx_info) {
802 .protect = &a630_protect,
803 .gmu_cgc_mode = 0x00000222,
804 .prim_fifo_threshold = 0x00180000,
805 },
806 .speedbins = ADRENO_SPEEDBINS(
807 { 0, 0 },
808 { 169, 1 },
809 { 174, 2 },
810 ),
811 }, {
812 .machine = "qcom,sm4350",
813 .chip_ids = ADRENO_CHIP_IDS(0x06010900),
814 .family = ADRENO_6XX_GEN1,
815 .revn = 619,
816 .fw = {
817 [ADRENO_FW_SQE] = "a630_sqe.fw",
818 [ADRENO_FW_GMU] = "a619_gmu.bin",
819 },
820 .gmem = SZ_512K,
821 .quirks = ADRENO_QUIRK_4GB_VA,
822 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
823 .funcs = &a6xx_gpu_funcs,
824 .zapfw = "a615_zap.mdt",
825 .a6xx = &(const struct a6xx_info) {
826 .hwcg = a615_hwcg,
827 .protect = &a630_protect,
828 .gmu_cgc_mode = 0x00000222,
829 .prim_fifo_threshold = 0x00018000,
830 },
831 .speedbins = ADRENO_SPEEDBINS(
832 { 0, 0 },
833 { 138, 1 },
834 { 92, 2 },
835 ),
836 }, {
837 .machine = "qcom,sm6375",
838 .chip_ids = ADRENO_CHIP_IDS(0x06010901),
839 .family = ADRENO_6XX_GEN1,
840 .revn = 619,
841 .fw = {
842 [ADRENO_FW_SQE] = "a630_sqe.fw",
843 [ADRENO_FW_GMU] = "a619_gmu.bin",
844 },
845 .gmem = SZ_512K,
846 .quirks = ADRENO_QUIRK_4GB_VA,
847 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
848 .funcs = &a6xx_gpu_funcs,
849 .zapfw = "a615_zap.mdt",
850 .a6xx = &(const struct a6xx_info) {
851 .hwcg = a615_hwcg,
852 .protect = &a630_protect,
853 .gmu_cgc_mode = 0x00000222,
854 .prim_fifo_threshold = 0x00018000,
855 },
856 .speedbins = ADRENO_SPEEDBINS(
857 { 0, 0 },
858 { 190, 1 },
859 { 177, 2 },
860 ),
861 }, {
862 .chip_ids = ADRENO_CHIP_IDS(0x06010900),
863 .family = ADRENO_6XX_GEN1,
864 .revn = 619,
865 .fw = {
866 [ADRENO_FW_SQE] = "a630_sqe.fw",
867 [ADRENO_FW_GMU] = "a619_gmu.bin",
868 },
869 .gmem = SZ_512K,
870 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
871 ADRENO_QUIRK_4GB_VA,
872 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
873 .funcs = &a6xx_gpu_funcs,
874 .zapfw = "a615_zap.mdt",
875 .a6xx = &(const struct a6xx_info) {
876 .hwcg = a615_hwcg,
877 .protect = &a630_protect,
878 .gmu_cgc_mode = 0x00000222,
879 .prim_fifo_threshold = 0x00018000,
880 },
881 .speedbins = ADRENO_SPEEDBINS(
882 { 0, 0 },
883 { 120, 4 },
884 { 138, 3 },
885 { 169, 2 },
886 { 180, 1 },
887 ),
888 }, {
889 .chip_ids = ADRENO_CHIP_IDS(0x06020100),
890 .family = ADRENO_6XX_GEN3,
891 .fw = {
892 [ADRENO_FW_SQE] = "a650_sqe.fw",
893 [ADRENO_FW_GMU] = "a621_gmu.bin",
894 },
895 .gmem = SZ_512K,
896 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
897 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
898 ADRENO_QUIRK_HAS_HW_APRIV,
899 .funcs = &a6xx_gpu_funcs,
900 .zapfw = "a620_zap.mbn",
901 .a6xx = &(const struct a6xx_info) {
902 .hwcg = a620_hwcg,
903 .protect = &a650_protect,
904 .gbif_cx = a640_gbif,
905 .gmu_cgc_mode = 0x00020200,
906 .prim_fifo_threshold = 0x00010000,
907 },
908 .speedbins = ADRENO_SPEEDBINS(
909 { 0, 0 },
910 { 137, 1 },
911 ),
912 }, {
913 .chip_ids = ADRENO_CHIP_IDS(0x06020300),
914 .family = ADRENO_6XX_GEN3,
915 .fw = {
916 [ADRENO_FW_SQE] = "a650_sqe.fw",
917 [ADRENO_FW_GMU] = "a623_gmu.bin",
918 },
919 .gmem = SZ_512K,
920 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
921 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
922 ADRENO_QUIRK_HAS_HW_APRIV,
923 .funcs = &a6xx_gpu_funcs,
924 .a6xx = &(const struct a6xx_info) {
925 .hwcg = a690_hwcg,
926 .protect = &a650_protect,
927 .gbif_cx = a640_gbif,
928 .gmu_cgc_mode = 0x00020200,
929 .prim_fifo_threshold = 0x00010000,
930 .bcms = (const struct a6xx_bcm[]) {
931 { .name = "SH0", .buswidth = 16 },
932 { .name = "MC0", .buswidth = 4 },
933 {
934 .name = "ACV",
935 .fixed = true,
936 .perfmode = BIT(3),
937 },
938 { /* sentinel */ },
939 },
940 },
941 .speedbins = ADRENO_SPEEDBINS(
942 { 0, 0 },
943 { 185, 0 },
944 { 127, 1 },
945 ),
946 }, {
947 .chip_ids = ADRENO_CHIP_IDS(
948 0x06030001,
949 0x06030002
950 ),
951 .family = ADRENO_6XX_GEN1,
952 .revn = 630,
953 .fw = {
954 [ADRENO_FW_SQE] = "a630_sqe.fw",
955 [ADRENO_FW_GMU] = "a630_gmu.bin",
956 },
957 .gmem = SZ_1M,
958 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
959 ADRENO_QUIRK_4GB_VA,
960 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
961 .funcs = &a6xx_gpu_funcs,
962 .zapfw = "a630_zap.mdt",
963 .a6xx = &(const struct a6xx_info) {
964 .hwcg = a630_hwcg,
965 .protect = &a630_protect,
966 .gmu_cgc_mode = 0x00020202,
967 .prim_fifo_threshold = 0x00180000,
968 },
969 }, {
970 .chip_ids = ADRENO_CHIP_IDS(0x06040001),
971 .family = ADRENO_6XX_GEN2,
972 .revn = 640,
973 .fw = {
974 [ADRENO_FW_SQE] = "a630_sqe.fw",
975 [ADRENO_FW_GMU] = "a640_gmu.bin",
976 },
977 .gmem = SZ_1M,
978 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
979 ADRENO_QUIRK_4GB_VA,
980 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
981 .funcs = &a6xx_gpu_funcs,
982 .zapfw = "a640_zap.mdt",
983 .a6xx = &(const struct a6xx_info) {
984 .hwcg = a640_hwcg,
985 .protect = &a630_protect,
986 .gmu_cgc_mode = 0x00020202,
987 .prim_fifo_threshold = 0x00180000,
988 },
989 .speedbins = ADRENO_SPEEDBINS(
990 { 0, 0 },
991 { 1, 1 },
992 ),
993 }, {
994 .chip_ids = ADRENO_CHIP_IDS(0x06050002),
995 .family = ADRENO_6XX_GEN3,
996 .revn = 650,
997 .fw = {
998 [ADRENO_FW_SQE] = "a650_sqe.fw",
999 [ADRENO_FW_GMU] = "a650_gmu.bin",
1000 },
1001 .gmem = SZ_1M + SZ_128K,
1002 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1003 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1004 ADRENO_QUIRK_HAS_HW_APRIV,
1005 .funcs = &a6xx_gpu_funcs,
1006 .zapfw = "a650_zap.mdt",
1007 .a6xx = &(const struct a6xx_info) {
1008 .hwcg = a650_hwcg,
1009 .protect = &a650_protect,
1010 .gbif_cx = a640_gbif,
1011 .gmu_cgc_mode = 0x00020202,
1012 .prim_fifo_threshold = 0x00300200,
1013 },
1014 .speedbins = ADRENO_SPEEDBINS(
1015 { 0, 0 },
1016 { 1, 1 },
1017 { 2, 3 }, /* Yep, 2 and 3 are swapped! :/ */
1018 { 3, 2 },
1019 ),
1020 }, {
1021 .chip_ids = ADRENO_CHIP_IDS(0x06060001),
1022 .family = ADRENO_6XX_GEN4,
1023 .revn = 660,
1024 .fw = {
1025 [ADRENO_FW_SQE] = "a660_sqe.fw",
1026 [ADRENO_FW_GMU] = "a660_gmu.bin",
1027 },
1028 .gmem = SZ_1M + SZ_512K,
1029 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1030 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1031 ADRENO_QUIRK_HAS_HW_APRIV,
1032 .funcs = &a6xx_gpu_funcs,
1033 .zapfw = "a660_zap.mdt",
1034 .a6xx = &(const struct a6xx_info) {
1035 .hwcg = a660_hwcg,
1036 .protect = &a660_protect,
1037 .gbif_cx = a640_gbif,
1038 .gmu_cgc_mode = 0x00020000,
1039 .prim_fifo_threshold = 0x00300200,
1040 },
1041 }, {
1042 .chip_ids = ADRENO_CHIP_IDS(0x06060300),
1043 .family = ADRENO_6XX_GEN4,
1044 .fw = {
1045 [ADRENO_FW_SQE] = "a660_sqe.fw",
1046 [ADRENO_FW_GMU] = "a663_gmu.bin",
1047 },
1048 .gmem = SZ_1M + SZ_512K,
1049 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1050 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1051 ADRENO_QUIRK_HAS_HW_APRIV,
1052 .funcs = &a6xx_gpu_funcs,
1053 .a6xx = &(const struct a6xx_info) {
1054 .hwcg = a690_hwcg,
1055 .protect = &a660_protect,
1056 .gbif_cx = a640_gbif,
1057 .gmu_cgc_mode = 0x00020200,
1058 .prim_fifo_threshold = 0x00300200,
1059 },
1060 .speedbins = ADRENO_SPEEDBINS(
1061 { 0, 0 },
1062 { 169, 0 },
1063 { 113, 1 },
1064 ),
1065 }, {
1066 .chip_ids = ADRENO_CHIP_IDS(0x06030500),
1067 .family = ADRENO_6XX_GEN4,
1068 .fw = {
1069 [ADRENO_FW_SQE] = "a660_sqe.fw",
1070 [ADRENO_FW_GMU] = "a660_gmu.bin",
1071 },
1072 .gmem = SZ_512K,
1073 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1074 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1075 ADRENO_QUIRK_HAS_HW_APRIV,
1076 .funcs = &a6xx_gpu_funcs,
1077 .zapfw = "a660_zap.mbn",
1078 .a6xx = &(const struct a6xx_info) {
1079 .hwcg = a660_hwcg,
1080 .protect = &a660_protect,
1081 .gbif_cx = a640_gbif,
1082 .gmu_cgc_mode = 0x00020202,
1083 .prim_fifo_threshold = 0x00200200,
1084 },
1085 .speedbins = ADRENO_SPEEDBINS(
1086 { 0, 0 },
1087 { 117, 0 },
1088 { 129, 4 },
1089 { 172, 2 }, /* Called speedbin 1 downstream, but let's not break things! */
1090 { 190, 1 },
1091 ),
1092 }, {
1093 .chip_ids = ADRENO_CHIP_IDS(0x06080001),
1094 .family = ADRENO_6XX_GEN2,
1095 .revn = 680,
1096 .fw = {
1097 [ADRENO_FW_SQE] = "a630_sqe.fw",
1098 [ADRENO_FW_GMU] = "a640_gmu.bin",
1099 },
1100 .gmem = SZ_2M,
1101 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1102 ADRENO_QUIRK_4GB_VA,
1103 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1104 .funcs = &a6xx_gpu_funcs,
1105 .zapfw = "a640_zap.mdt",
1106 .a6xx = &(const struct a6xx_info) {
1107 .hwcg = a640_hwcg,
1108 .protect = &a630_protect,
1109 .gmu_cgc_mode = 0x00020202,
1110 .prim_fifo_threshold = 0x00200200,
1111 },
1112 }, {
1113 .chip_ids = ADRENO_CHIP_IDS(0x06090000),
1114 .family = ADRENO_6XX_GEN4,
1115 .fw = {
1116 [ADRENO_FW_SQE] = "a660_sqe.fw",
1117 [ADRENO_FW_GMU] = "a660_gmu.bin",
1118 },
1119 .gmem = SZ_4M,
1120 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1121 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1122 ADRENO_QUIRK_HAS_HW_APRIV,
1123 .funcs = &a6xx_gpu_funcs,
1124 .zapfw = "a690_zap.mdt",
1125 .a6xx = &(const struct a6xx_info) {
1126 .hwcg = a690_hwcg,
1127 .protect = &a690_protect,
1128 .gbif_cx = a640_gbif,
1129 .gmu_cgc_mode = 0x00020200,
1130 .prim_fifo_threshold = 0x00800200,
1131 },
1132 }
1133 };
1134 DECLARE_ADRENO_GPULIST(a6xx);
1135
1136 static const struct adreno_reglist a702_hwcg[] = {
1137 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222 },
1138 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220 },
1139 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081 },
1140 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf },
1141 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222 },
1142 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
1143 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
1144 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222 },
1145 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
1146 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
1147 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
1148 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
1149 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
1150 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
1151 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
1152 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
1153 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
1154 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222 },
1155 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
1156 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00 },
1157 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022 },
1158 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555 },
1159 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
1160 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044 },
1161 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
1162 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 },
1163 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222 },
1164 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 },
1165 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
1166 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 },
1167 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 },
1168 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
1169 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
1170 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
1171 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
1172 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
1173 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
1174 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
1175 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 },
1176 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 },
1177 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
1178 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
1179 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
1180 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
1181 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
1182 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
1183 { REG_A6XX_RBBM_CLOCK_CNTL_FCHE, 0x00000222 },
1184 { REG_A6XX_RBBM_CLOCK_DELAY_FCHE, 0x00000000 },
1185 { REG_A6XX_RBBM_CLOCK_HYST_FCHE, 0x00000000 },
1186 { REG_A6XX_RBBM_CLOCK_CNTL_GLC, 0x00222222 },
1187 { REG_A6XX_RBBM_CLOCK_DELAY_GLC, 0x00000000 },
1188 { REG_A6XX_RBBM_CLOCK_HYST_GLC, 0x00000000 },
1189 { REG_A6XX_RBBM_CLOCK_CNTL_MHUB, 0x00000002 },
1190 { REG_A6XX_RBBM_CLOCK_DELAY_MHUB, 0x00000000 },
1191 { REG_A6XX_RBBM_CLOCK_HYST_MHUB, 0x00000000 },
1192 {}
1193 };
1194
1195 static const struct adreno_reglist a730_hwcg[] = {
1196 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
1197 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 },
1198 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf },
1199 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
1200 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
1201 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
1202 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
1203 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
1204 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
1205 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
1206 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
1207 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
1208 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
1209 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
1210 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
1211 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
1212 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
1213 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 },
1214 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 },
1215 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
1216 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
1217 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
1218 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
1219 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
1220 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
1221 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
1222 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
1223 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
1224 { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
1225 { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
1226 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
1227 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 },
1228 { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
1229 { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
1230 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
1231 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
1232 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
1233 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 },
1234 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
1235 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 },
1236 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
1237 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
1238 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
1239 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 },
1240 { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
1241 { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000223 },
1242 { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
1243 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
1244 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
1245 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
1246 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
1247 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
1248 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
1249 {},
1250 };
1251
1252 static const struct adreno_reglist a740_hwcg[] = {
1253 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
1254 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x22022222 },
1255 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x003cf3cf },
1256 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
1257 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
1258 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
1259 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
1260 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
1261 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
1262 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
1263 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
1264 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
1265 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
1266 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
1267 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
1268 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
1269 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
1270 { REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x00222222 },
1271 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000444 },
1272 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000222 },
1273 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
1274 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
1275 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
1276 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
1277 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
1278 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
1279 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
1280 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
1281 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
1282 { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
1283 { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
1284 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
1285 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00222222 },
1286 { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
1287 { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
1288 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
1289 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
1290 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
1291 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000000 },
1292 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
1293 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00000000 },
1294 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
1295 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
1296 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
1297 { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
1298 { REG_A7XX_RBBM_CLOCK_HYST2_VFD, 0x00000000 },
1299 { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000222 },
1300 { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
1301 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
1302 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
1303 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
1304 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
1305 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
1306 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
1307 {},
1308 };
1309
1310 static const u32 a730_protect_regs[] = {
1311 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
1312 A6XX_PROTECT_RDONLY(0x0050b, 0x0058),
1313 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
1314 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
1315 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
1316 A6XX_PROTECT_RDONLY(0x005fb, 0x009d),
1317 A6XX_PROTECT_NORDWR(0x00699, 0x01e9),
1318 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
1319 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
1320 /* 0x008d0-0x008dd and 0x008e0-0x008e6 are unprotected on purpose for tools like perfetto */
1321 A6XX_PROTECT_NORDWR(0x008de, 0x0001),
1322 A6XX_PROTECT_RDONLY(0x008e7, 0x014b),
1323 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
1324 A6XX_PROTECT_NORDWR(0x0098d, 0x00b2),
1325 A6XX_PROTECT_NORDWR(0x00a41, 0x01be),
1326 A6XX_PROTECT_NORDWR(0x00df0, 0x0001),
1327 A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
1328 A6XX_PROTECT_NORDWR(0x00e07, 0x0008),
1329 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
1330 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
1331 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
1332 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
1333 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
1334 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
1335 A6XX_PROTECT_NORDWR(0x08e80, 0x0280),
1336 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
1337 A6XX_PROTECT_NORDWR(0x09e40, 0x0000),
1338 A6XX_PROTECT_NORDWR(0x09e64, 0x000d),
1339 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
1340 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
1341 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
1342 A6XX_PROTECT_NORDWR(0x0ae50, 0x000f),
1343 A6XX_PROTECT_NORDWR(0x0ae66, 0x0003),
1344 A6XX_PROTECT_NORDWR(0x0ae6f, 0x0003),
1345 A6XX_PROTECT_NORDWR(0x0b604, 0x0003),
1346 A6XX_PROTECT_NORDWR(0x0ec00, 0x0fff),
1347 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
1348 A6XX_PROTECT_NORDWR(0x18400, 0x0053),
1349 A6XX_PROTECT_RDONLY(0x18454, 0x0004),
1350 A6XX_PROTECT_NORDWR(0x18459, 0x1fff),
1351 A6XX_PROTECT_NORDWR(0x1a459, 0x1fff),
1352 A6XX_PROTECT_NORDWR(0x1c459, 0x1fff),
1353 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
1354 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
1355 A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
1356 A6XX_PROTECT_NORDWR(0x1f878, 0x002a),
1357 /* CP_PROTECT_REG[45, 46] are left untouched! */
1358 0,
1359 0,
1360 A6XX_PROTECT_NORDWR(0x1f8c0, 0x00000),
1361 };
1362 DECLARE_ADRENO_PROTECT(a730_protect, 48);
1363
1364 static const uint32_t a7xx_pwrup_reglist_regs[] = {
1365 REG_A6XX_UCHE_TRAP_BASE,
1366 REG_A6XX_UCHE_TRAP_BASE + 1,
1367 REG_A6XX_UCHE_WRITE_THRU_BASE,
1368 REG_A6XX_UCHE_WRITE_THRU_BASE + 1,
1369 REG_A6XX_UCHE_GMEM_RANGE_MIN,
1370 REG_A6XX_UCHE_GMEM_RANGE_MIN + 1,
1371 REG_A6XX_UCHE_GMEM_RANGE_MAX,
1372 REG_A6XX_UCHE_GMEM_RANGE_MAX + 1,
1373 REG_A6XX_UCHE_CACHE_WAYS,
1374 REG_A6XX_UCHE_MODE_CNTL,
1375 REG_A6XX_RB_NC_MODE_CNTL,
1376 REG_A6XX_RB_CMP_DBG_ECO_CNTL,
1377 REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE,
1378 REG_A6XX_UCHE_GBIF_GX_CONFIG,
1379 REG_A6XX_UCHE_CLIENT_PF,
1380 REG_A6XX_TPL1_DBG_ECO_CNTL1,
1381 };
1382
1383 DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist);
1384
1385 /* Applicable for X185, A750 */
1386 static const u32 a750_ifpc_reglist_regs[] = {
1387 REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(0),
1388 REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(1),
1389 REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),
1390 REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),
1391 REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),
1392 REG_A6XX_RBBM_PERFCTR_CNTL,
1393 REG_A6XX_TPL1_NC_MODE_CNTL,
1394 REG_A6XX_SP_NC_MODE_CNTL,
1395 REG_A6XX_CP_DBG_ECO_CNTL,
1396 REG_A6XX_CP_PROTECT_CNTL,
1397 REG_A6XX_CP_PROTECT(0),
1398 REG_A6XX_CP_PROTECT(1),
1399 REG_A6XX_CP_PROTECT(2),
1400 REG_A6XX_CP_PROTECT(3),
1401 REG_A6XX_CP_PROTECT(4),
1402 REG_A6XX_CP_PROTECT(5),
1403 REG_A6XX_CP_PROTECT(6),
1404 REG_A6XX_CP_PROTECT(7),
1405 REG_A6XX_CP_PROTECT(8),
1406 REG_A6XX_CP_PROTECT(9),
1407 REG_A6XX_CP_PROTECT(10),
1408 REG_A6XX_CP_PROTECT(11),
1409 REG_A6XX_CP_PROTECT(12),
1410 REG_A6XX_CP_PROTECT(13),
1411 REG_A6XX_CP_PROTECT(14),
1412 REG_A6XX_CP_PROTECT(15),
1413 REG_A6XX_CP_PROTECT(16),
1414 REG_A6XX_CP_PROTECT(17),
1415 REG_A6XX_CP_PROTECT(18),
1416 REG_A6XX_CP_PROTECT(19),
1417 REG_A6XX_CP_PROTECT(20),
1418 REG_A6XX_CP_PROTECT(21),
1419 REG_A6XX_CP_PROTECT(22),
1420 REG_A6XX_CP_PROTECT(23),
1421 REG_A6XX_CP_PROTECT(24),
1422 REG_A6XX_CP_PROTECT(25),
1423 REG_A6XX_CP_PROTECT(26),
1424 REG_A6XX_CP_PROTECT(27),
1425 REG_A6XX_CP_PROTECT(28),
1426 REG_A6XX_CP_PROTECT(29),
1427 REG_A6XX_CP_PROTECT(30),
1428 REG_A6XX_CP_PROTECT(31),
1429 REG_A6XX_CP_PROTECT(32),
1430 REG_A6XX_CP_PROTECT(33),
1431 REG_A6XX_CP_PROTECT(34),
1432 REG_A6XX_CP_PROTECT(35),
1433 REG_A6XX_CP_PROTECT(36),
1434 REG_A6XX_CP_PROTECT(37),
1435 REG_A6XX_CP_PROTECT(38),
1436 REG_A6XX_CP_PROTECT(39),
1437 REG_A6XX_CP_PROTECT(40),
1438 REG_A6XX_CP_PROTECT(41),
1439 REG_A6XX_CP_PROTECT(42),
1440 REG_A6XX_CP_PROTECT(43),
1441 REG_A6XX_CP_PROTECT(44),
1442 REG_A6XX_CP_PROTECT(45),
1443 REG_A6XX_CP_PROTECT(46),
1444 REG_A6XX_CP_PROTECT(47),
1445 };
1446
1447 DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist);
1448
1449 static const struct adreno_reglist_pipe a7xx_dyn_pwrup_reglist_regs[] = {
1450 { REG_A7XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
1451 };
1452
1453 DECLARE_ADRENO_REGLIST_PIPE_LIST(a7xx_dyn_pwrup_reglist);
1454
1455 static const struct adreno_info a7xx_gpus[] = {
1456 {
1457 .chip_ids = ADRENO_CHIP_IDS(0x07000200),
1458 .family = ADRENO_6XX_GEN1, /* NOT a mistake! */
1459 .fw = {
1460 [ADRENO_FW_SQE] = "a702_sqe.fw",
1461 },
1462 .gmem = SZ_128K,
1463 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1464 .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
1465 .funcs = &a6xx_gmuwrapper_funcs,
1466 .zapfw = "a702_zap.mbn",
1467 .a6xx = &(const struct a6xx_info) {
1468 .hwcg = a702_hwcg,
1469 .protect = &a650_protect,
1470 .gbif_cx = a640_gbif,
1471 .gmu_cgc_mode = 0x00020202,
1472 .prim_fifo_threshold = 0x0000c000,
1473 },
1474 .speedbins = ADRENO_SPEEDBINS(
1475 { 0, 0 },
1476 { 236, 1 },
1477 { 178, 2 },
1478 { 142, 3 },
1479 ),
1480 }, {
1481 .chip_ids = ADRENO_CHIP_IDS(0x07030001),
1482 .family = ADRENO_7XX_GEN1,
1483 .fw = {
1484 [ADRENO_FW_SQE] = "a730_sqe.fw",
1485 [ADRENO_FW_GMU] = "gmu_gen70000.bin",
1486 },
1487 .gmem = SZ_2M,
1488 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1489 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1490 ADRENO_QUIRK_HAS_HW_APRIV |
1491 ADRENO_QUIRK_PREEMPTION,
1492 .funcs = &a7xx_gpu_funcs,
1493 .zapfw = "a730_zap.mdt",
1494 .a6xx = &(const struct a6xx_info) {
1495 .hwcg = a730_hwcg,
1496 .protect = &a730_protect,
1497 .pwrup_reglist = &a7xx_pwrup_reglist,
1498 .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,
1499 .gbif_cx = a640_gbif,
1500 .gmu_cgc_mode = 0x00020000,
1501 },
1502 .preempt_record_size = 2860 * SZ_1K,
1503 }, {
1504 .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */
1505 .family = ADRENO_7XX_GEN2,
1506 .fw = {
1507 [ADRENO_FW_SQE] = "a740_sqe.fw",
1508 [ADRENO_FW_GMU] = "gmu_gen70200.bin",
1509 },
1510 .gmem = 3 * SZ_1M,
1511 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1512 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1513 ADRENO_QUIRK_HAS_HW_APRIV |
1514 ADRENO_QUIRK_PREEMPTION,
1515 .funcs = &a7xx_gpu_funcs,
1516 .zapfw = "a740_zap.mdt",
1517 .a6xx = &(const struct a6xx_info) {
1518 .hwcg = a740_hwcg,
1519 .protect = &a730_protect,
1520 .pwrup_reglist = &a7xx_pwrup_reglist,
1521 .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,
1522 .gbif_cx = a640_gbif,
1523 .gmu_chipid = 0x7020100,
1524 .gmu_cgc_mode = 0x00020202,
1525 .bcms = (const struct a6xx_bcm[]) {
1526 { .name = "SH0", .buswidth = 16 },
1527 { .name = "MC0", .buswidth = 4 },
1528 {
1529 .name = "ACV",
1530 .fixed = true,
1531 .perfmode = BIT(3),
1532 .perfmode_bw = 16500000,
1533 },
1534 { /* sentinel */ },
1535 },
1536 },
1537 .preempt_record_size = 4192 * SZ_1K,
1538 }, {
1539 .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */
1540 .family = ADRENO_7XX_GEN2,
1541 .fw = {
1542 [ADRENO_FW_SQE] = "gen70500_sqe.fw",
1543 [ADRENO_FW_GMU] = "gen70500_gmu.bin",
1544 },
1545 .gmem = 3 * SZ_1M,
1546 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1547 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1548 ADRENO_QUIRK_HAS_HW_APRIV |
1549 ADRENO_QUIRK_PREEMPTION |
1550 ADRENO_QUIRK_IFPC,
1551 .funcs = &a7xx_gpu_funcs,
1552 .a6xx = &(const struct a6xx_info) {
1553 .hwcg = a740_hwcg,
1554 .protect = &a730_protect,
1555 .pwrup_reglist = &a7xx_pwrup_reglist,
1556 .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,
1557 .ifpc_reglist = &a750_ifpc_reglist,
1558 .gbif_cx = a640_gbif,
1559 .gmu_chipid = 0x7050001,
1560 .gmu_cgc_mode = 0x00020202,
1561 .bcms = (const struct a6xx_bcm[]) {
1562 { .name = "SH0", .buswidth = 16 },
1563 { .name = "MC0", .buswidth = 4 },
1564 {
1565 .name = "ACV",
1566 .fixed = true,
1567 .perfmode = BIT(3),
1568 .perfmode_bw = 16500000,
1569 },
1570 { /* sentinel */ },
1571 },
1572 },
1573 .preempt_record_size = 4192 * SZ_1K,
1574 .speedbins = ADRENO_SPEEDBINS(
1575 { 0, 0 },
1576 { 59, 1 },
1577 { 7, 2 },
1578 { 232, 3 },
1579 { 146, 4 },
1580 ),
1581 }, {
1582 .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */
1583 .family = ADRENO_7XX_GEN3,
1584 .fw = {
1585 [ADRENO_FW_SQE] = "gen70900_sqe.fw",
1586 [ADRENO_FW_GMU] = "gmu_gen70900.bin",
1587 },
1588 .gmem = 3 * SZ_1M,
1589 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1590 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1591 ADRENO_QUIRK_HAS_HW_APRIV |
1592 ADRENO_QUIRK_PREEMPTION |
1593 ADRENO_QUIRK_IFPC,
1594 .funcs = &a7xx_gpu_funcs,
1595 .zapfw = "gen70900_zap.mbn",
1596 .a6xx = &(const struct a6xx_info) {
1597 .protect = &a730_protect,
1598 .pwrup_reglist = &a7xx_pwrup_reglist,
1599 .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,
1600 .ifpc_reglist = &a750_ifpc_reglist,
1601 .gbif_cx = a640_gbif,
1602 .gmu_chipid = 0x7090100,
1603 .gmu_cgc_mode = 0x00020202,
1604 .bcms = (const struct a6xx_bcm[]) {
1605 { .name = "SH0", .buswidth = 16 },
1606 { .name = "MC0", .buswidth = 4 },
1607 {
1608 .name = "ACV",
1609 .fixed = true,
1610 .perfmode = BIT(2),
1611 .perfmode_bw = 10687500,
1612 },
1613 { /* sentinel */ },
1614 },
1615 },
1616 .preempt_record_size = 3572 * SZ_1K,
1617 }, {
1618 .chip_ids = ADRENO_CHIP_IDS(0x43030c00),
1619 .family = ADRENO_7XX_GEN2,
1620 .fw = {
1621 [ADRENO_FW_SQE] = "gen71500_sqe.fw",
1622 [ADRENO_FW_GMU] = "gen71500_gmu.bin",
1623 },
1624 .gmem = SZ_1M + SZ_512K,
1625 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1626 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1627 ADRENO_QUIRK_HAS_HW_APRIV |
1628 ADRENO_QUIRK_PREEMPTION,
1629 .funcs = &a7xx_gpu_funcs,
1630 .a6xx = &(const struct a6xx_info) {
1631 .hwcg = a740_hwcg,
1632 .protect = &a730_protect,
1633 .pwrup_reglist = &a7xx_pwrup_reglist,
1634 .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,
1635 .gbif_cx = a640_gbif,
1636 .gmu_chipid = 0x70f0000,
1637 .gmu_cgc_mode = 0x00020222,
1638 .bcms = (const struct a6xx_bcm[]) {
1639 { .name = "SH0", .buswidth = 16 },
1640 { .name = "MC0", .buswidth = 4 },
1641 {
1642 .name = "ACV",
1643 .fixed = true,
1644 .perfmode = BIT(3),
1645 .perfmode_bw = 16500000,
1646 },
1647 { /* sentinel */ },
1648 },
1649 },
1650 .preempt_record_size = 4192 * SZ_1K,
1651 .speedbins = ADRENO_SPEEDBINS(
1652 { 0, 0 },
1653 { 294, 1 },
1654 { 263, 2 },
1655 { 233, 3 },
1656 { 141, 4 },
1657 ),
1658 }
1659 };
1660 DECLARE_ADRENO_GPULIST(a7xx);
1661
1662 static const struct adreno_reglist_pipe x285_nonctxt_regs[] = {
1663 { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
1664 { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
1665 { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1666 { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
1667 { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1668 { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) },
1669 { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) },
1670 { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) },
1671 { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1672 { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
1673 { REG_A8XX_RB_GC_GMEM_PROTECT, 0x15000000, BIT(PIPE_BR) },
1674 { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
1675 { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
1676 { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
1677 { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
1678 { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) },
1679 { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) },
1680 { REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, 0x0fffffff, BIT(PIPE_NONE) },
1681 { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) },
1682 { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) },
1683 { REG_A7XX_SP_CHICKEN_BITS_2, 0x00820800, BIT(PIPE_NONE) },
1684 { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) },
1685 { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) },
1686 /* Disable CS dead batch merge */
1687 { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, BIT(31), BIT(PIPE_NONE) },
1688 { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) },
1689 { REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },
1690 { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) },
1691 /* BIT(26): Disable final clamp for bicubic filtering */
1692 { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000720, BIT(PIPE_NONE) },
1693 { REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) },
1694 { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },
1695 { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) },
1696 { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) },
1697 { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) },
1698 { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1699 { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
1700 { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) },
1701 { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) },
1702 { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00000020, BIT(PIPE_BV) | BIT(PIPE_BR) },
1703 { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
1704 { },
1705 };
1706
1707 static const u32 x285_protect_regs[] = {
1708 A6XX_PROTECT_RDONLY(0x00008, 0x039b),
1709 A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
1710 A6XX_PROTECT_NORDWR(0x00440, 0x001f),
1711 A6XX_PROTECT_RDONLY(0x00580, 0x005f),
1712 A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
1713 A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
1714 A6XX_PROTECT_RDONLY(0x00759, 0x0026),
1715 A6XX_PROTECT_RDONLY(0x00789, 0x0000),
1716 A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
1717 A6XX_PROTECT_NORDWR(0x00800, 0x0029),
1718 A6XX_PROTECT_NORDWR(0x0082c, 0x0000),
1719 A6XX_PROTECT_NORDWR(0x00837, 0x00af),
1720 A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
1721 A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
1722 A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
1723 A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
1724 A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
1725 A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
1726 A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
1727 A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
1728 A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
1729 A6XX_PROTECT_RDONLY(0x03cc6, 0x0039),
1730 A6XX_PROTECT_NORDWR(0x03d00, 0x1fff),
1731 A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
1732 A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
1733 A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
1734 A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
1735 A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
1736 A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
1737 A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
1738 A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
1739 A6XX_PROTECT_NORDWR(0x0a82e, 0x0000),
1740 A6XX_PROTECT_NORDWR(0x0ae00, 0x0006),
1741 A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
1742 A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf),
1743 A6XX_PROTECT_RDONLY(0x0aed0, 0x002f),
1744 A6XX_PROTECT_NORDWR(0x0af00, 0x027f),
1745 A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
1746 A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
1747 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
1748 A6XX_PROTECT_NORDWR(0x18400, 0x003f),
1749 A6XX_PROTECT_RDONLY(0x18440, 0x013f),
1750 A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
1751 A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
1752 A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
1753 A6XX_PROTECT_RDONLY(0x1f878, 0x0507),
1754 A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
1755 A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff),
1756 A6XX_PROTECT_NORDWR(0x27800, 0x007f),
1757 A6XX_PROTECT_RDONLY(0x27880, 0x0385),
1758 A6XX_PROTECT_NORDWR(0x27882, 0x000a),
1759 A6XX_PROTECT_NORDWR(0x27c06, 0x0000),
1760 };
1761
1762 DECLARE_ADRENO_PROTECT(x285_protect, 15);
1763
1764 static const struct adreno_reglist_pipe x285_dyn_pwrup_reglist_regs[] = {
1765 { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
1766 { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
1767 { REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
1768 { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
1769 { REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
1770 { REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
1771 { REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
1772 { REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
1773 { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
1774 { REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
1775 { REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) },
1776 { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR)},
1777 { REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) },
1778 { REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) },
1779 { REG_A6XX_RB_RBP_CNTL, 0, BIT(PIPE_BR) },
1780 { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) },
1781 { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) },
1782 { REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
1783 { REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
1784 { REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
1785 { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
1786 { REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
1787 { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
1788 { REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) |
1789 BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) |
1790 BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) },
1791 { REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) |
1792 BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) |
1793 BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) },
1794 { REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC)},
1795 { REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC) },
1796 { REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) },
1797 { REG_A8XX_RB_LPAC_GMEM_PROTECT, 0, BIT(PIPE_BR) },
1798 { REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) },
1799 };
1800 DECLARE_ADRENO_REGLIST_PIPE_LIST(x285_dyn_pwrup_reglist);
1801
1802 static const struct adreno_reglist_pipe a840_nonctxt_regs[] = {
1803 { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
1804 { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
1805 { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1806 { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
1807 { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1808 { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) },
1809 { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) },
1810 { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) },
1811 { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1812 { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
1813 /* Disable Dead Draw Merge scheme on RB-HLSQ */
1814 { REG_A6XX_RB_RBP_CNTL, BIT(5), BIT(PIPE_BV) | BIT(PIPE_BR) },
1815 { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) },
1816 /* Partially enable perf clear, Disable DINT to c/z be data forwarding */
1817 { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) },
1818 { REG_A8XX_RB_GC_GMEM_PROTECT, 0x12000000, BIT(PIPE_BR) },
1819 { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
1820 { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
1821 { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
1822 { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
1823 { REG_A8XX_RBBM_POWER_UP_RESET_SW_OVERRIDE, 0x70809060, BIT(PIPE_NONE) },
1824 { REG_A8XX_RBBM_POWER_UP_RESET_SW_BV_OVERRIDE, 0x30000000, BIT(PIPE_NONE) },
1825 { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) },
1826 { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) },
1827 { REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, 0x0fffffff, BIT(PIPE_NONE) },
1828 { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) },
1829 { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) },
1830 /* Disable mode_switch optimization in UMAS */
1831 { REG_A6XX_SP_CHICKEN_BITS, BIT(24) | BIT(26), BIT(PIPE_NONE) },
1832 /* Disable LPAC large-LM mode */
1833 { REG_A8XX_SP_SS_CHICKEN_BITS_0, BIT(3), BIT(PIPE_NONE) },
1834 /* Disable PS out of order retire */
1835 { REG_A7XX_SP_CHICKEN_BITS_2, 0x00c21800, BIT(PIPE_NONE) },
1836 { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) },
1837 /* Disable SP2TP info attribute */
1838 { REG_A8XX_SP_CHICKEN_BITS_4, 0x00000002, BIT(PIPE_NONE) },
1839 { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) },
1840 { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, BIT(14), BIT(PIPE_NONE) },
1841 /* Ignore HLSQ shared constant feedback from SP */
1842 { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, BIT(17), BIT(PIPE_NONE) },
1843 /* Disable CS dead batch merge */
1844 { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, BIT(24), BIT(PIPE_NONE) },
1845 { REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3, BIT(7), BIT(PIPE_NONE) },
1846 { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) },
1847 { REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },
1848 { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10100000, BIT(PIPE_NONE) },
1849 /* BIT(26): Disable final clamp for bicubic filtering */
1850 { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000720, BIT(PIPE_NONE) },
1851 { REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) },
1852 { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },
1853 { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) },
1854 { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) },
1855 { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) },
1856 { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1857 { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
1858 { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) },
1859 { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) },
1860 { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00000020, BIT(PIPE_BV) | BIT(PIPE_BR) },
1861 { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
1862 { },
1863 };
1864
1865 static const u32 a840_protect_regs[] = {
1866 A6XX_PROTECT_RDONLY(0x00008, 0x039b),
1867 A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
1868 A6XX_PROTECT_NORDWR(0x00440, 0x001f),
1869 A6XX_PROTECT_RDONLY(0x00580, 0x005f),
1870 A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
1871 A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
1872 A6XX_PROTECT_RDONLY(0x00759, 0x001b),
1873 A6XX_PROTECT_NORDWR(0x00775, 0x000a),
1874 A6XX_PROTECT_RDONLY(0x00789, 0x0000),
1875 A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
1876 A6XX_PROTECT_NORDWR(0x00800, 0x0029),
1877 A6XX_PROTECT_NORDWR(0x00837, 0x00af),
1878 A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
1879 A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
1880 A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
1881 A6XX_PROTECT_NORDWR(0x00c07, 0x0008),
1882 A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
1883 A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
1884 A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
1885 A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
1886 A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
1887 A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
1888 A6XX_PROTECT_RDONLY(0x03cc6, 0x0039),
1889 A6XX_PROTECT_NORDWR(0x03d00, 0x1fff),
1890 A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
1891 A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
1892 A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
1893 A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
1894 A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
1895 A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
1896 A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
1897 A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
1898 A6XX_PROTECT_NORDWR(0x0a82e, 0x0000),
1899 A6XX_PROTECT_NORDWR(0x0ae00, 0x0000),
1900 A6XX_PROTECT_NORDWR(0x0ae02, 0x0004),
1901 A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
1902 A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf),
1903 A6XX_PROTECT_RDONLY(0x0aed0, 0x002f),
1904 A6XX_PROTECT_NORDWR(0x0af00, 0x027f),
1905 A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
1906 A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
1907 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
1908 A6XX_PROTECT_NORDWR(0x18400, 0x003f),
1909 A6XX_PROTECT_RDONLY(0x18440, 0x013f),
1910 A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
1911 A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
1912 A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
1913 A6XX_PROTECT_RDONLY(0x1f878, 0x0507),
1914 A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
1915 A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff),
1916 A6XX_PROTECT_NORDWR(0x27800, 0x007f),
1917 A6XX_PROTECT_RDONLY(0x27880, 0x0385),
1918 A6XX_PROTECT_NORDWR(0x27882, 0x0009),
1919 A6XX_PROTECT_NORDWR(0x27c06, 0x0000),
1920 };
1921 DECLARE_ADRENO_PROTECT(a840_protect, 15);
1922
1923 static const struct adreno_reglist a840_gbif[] = {
1924 { REG_A6XX_GBIF_QSB_SIDE0, 0x00071e20 },
1925 { REG_A6XX_GBIF_QSB_SIDE1, 0x00071e20 },
1926 { REG_A6XX_GBIF_QSB_SIDE2, 0x00071e20 },
1927 { REG_A6XX_GBIF_QSB_SIDE3, 0x00071e20 },
1928 { REG_A8XX_GBIF_CX_CONFIG, 0x20023000 },
1929 { },
1930 };
1931
1932 static const uint32_t a840_pwrup_reglist_regs[] = {
1933 REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP,
1934 REG_A7XX_SP_READ_SEL,
1935 REG_A6XX_UCHE_MODE_CNTL,
1936 REG_A8XX_UCHE_VARB_IDLE_TIMEOUT,
1937 REG_A8XX_UCHE_GBIF_GX_CONFIG,
1938 REG_A8XX_UCHE_CCHE_MODE_CNTL,
1939 REG_A8XX_UCHE_CCHE_CACHE_WAYS,
1940 REG_A8XX_UCHE_CACHE_WAYS,
1941 REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN,
1942 REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN + 1,
1943 REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN,
1944 REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN + 1,
1945 REG_A8XX_UCHE_CCHE_TRAP_BASE,
1946 REG_A8XX_UCHE_CCHE_TRAP_BASE + 1,
1947 REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE,
1948 REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE + 1,
1949 REG_A8XX_UCHE_HW_DBG_CNTL,
1950 REG_A8XX_UCHE_WRITE_THRU_BASE,
1951 REG_A8XX_UCHE_WRITE_THRU_BASE + 1,
1952 REG_A8XX_UCHE_TRAP_BASE,
1953 REG_A8XX_UCHE_TRAP_BASE + 1,
1954 REG_A8XX_UCHE_CLIENT_PF,
1955 REG_A8XX_RB_CMP_NC_MODE_CNTL,
1956 REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN,
1957 REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN + 1,
1958 REG_A6XX_TPL1_NC_MODE_CNTL,
1959 REG_A6XX_TPL1_DBG_ECO_CNTL,
1960 REG_A6XX_TPL1_DBG_ECO_CNTL1,
1961 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(0),
1962 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1),
1963 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),
1964 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),
1965 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),
1966 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5),
1967 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6),
1968 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7),
1969 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8),
1970 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9),
1971 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10),
1972 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11),
1973 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12),
1974 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13),
1975 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14),
1976 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15),
1977 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16),
1978 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17),
1979 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18),
1980 REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19),
1981 };
1982 DECLARE_ADRENO_REGLIST_LIST(a840_pwrup_reglist);
1983
1984 static const u32 a840_ifpc_reglist_regs[] = {
1985 REG_A8XX_RBBM_NC_MODE_CNTL,
1986 REG_A8XX_RBBM_SLICE_NC_MODE_CNTL,
1987 REG_A6XX_SP_NC_MODE_CNTL,
1988 REG_A6XX_SP_CHICKEN_BITS,
1989 REG_A8XX_SP_SS_CHICKEN_BITS_0,
1990 REG_A7XX_SP_CHICKEN_BITS_1,
1991 REG_A7XX_SP_CHICKEN_BITS_2,
1992 REG_A7XX_SP_CHICKEN_BITS_3,
1993 REG_A8XX_SP_CHICKEN_BITS_4,
1994 REG_A6XX_SP_PERFCTR_SHADER_MASK,
1995 REG_A8XX_RBBM_SLICE_PERFCTR_CNTL,
1996 REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL,
1997 REG_A7XX_SP_HLSQ_DBG_ECO_CNTL,
1998 REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1,
1999 REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2,
2000 REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3,
2001 REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN,
2002 REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN + 1,
2003 REG_A8XX_CP_INTERRUPT_STATUS_MASK_GLOBAL,
2004 REG_A8XX_RBBM_PERFCTR_CNTL,
2005 REG_A8XX_CP_PROTECT_GLOBAL(0),
2006 REG_A8XX_CP_PROTECT_GLOBAL(1),
2007 REG_A8XX_CP_PROTECT_GLOBAL(2),
2008 REG_A8XX_CP_PROTECT_GLOBAL(3),
2009 REG_A8XX_CP_PROTECT_GLOBAL(4),
2010 REG_A8XX_CP_PROTECT_GLOBAL(5),
2011 REG_A8XX_CP_PROTECT_GLOBAL(6),
2012 REG_A8XX_CP_PROTECT_GLOBAL(7),
2013 REG_A8XX_CP_PROTECT_GLOBAL(8),
2014 REG_A8XX_CP_PROTECT_GLOBAL(9),
2015 REG_A8XX_CP_PROTECT_GLOBAL(10),
2016 REG_A8XX_CP_PROTECT_GLOBAL(11),
2017 REG_A8XX_CP_PROTECT_GLOBAL(12),
2018 REG_A8XX_CP_PROTECT_GLOBAL(13),
2019 REG_A8XX_CP_PROTECT_GLOBAL(14),
2020 REG_A8XX_CP_PROTECT_GLOBAL(15),
2021 REG_A8XX_CP_PROTECT_GLOBAL(16),
2022 REG_A8XX_CP_PROTECT_GLOBAL(17),
2023 REG_A8XX_CP_PROTECT_GLOBAL(18),
2024 REG_A8XX_CP_PROTECT_GLOBAL(19),
2025 REG_A8XX_CP_PROTECT_GLOBAL(20),
2026 REG_A8XX_CP_PROTECT_GLOBAL(21),
2027 REG_A8XX_CP_PROTECT_GLOBAL(22),
2028 REG_A8XX_CP_PROTECT_GLOBAL(23),
2029 REG_A8XX_CP_PROTECT_GLOBAL(24),
2030 REG_A8XX_CP_PROTECT_GLOBAL(25),
2031 REG_A8XX_CP_PROTECT_GLOBAL(26),
2032 REG_A8XX_CP_PROTECT_GLOBAL(27),
2033 REG_A8XX_CP_PROTECT_GLOBAL(28),
2034 REG_A8XX_CP_PROTECT_GLOBAL(29),
2035 REG_A8XX_CP_PROTECT_GLOBAL(30),
2036 REG_A8XX_CP_PROTECT_GLOBAL(31),
2037 REG_A8XX_CP_PROTECT_GLOBAL(32),
2038 REG_A8XX_CP_PROTECT_GLOBAL(33),
2039 REG_A8XX_CP_PROTECT_GLOBAL(34),
2040 REG_A8XX_CP_PROTECT_GLOBAL(35),
2041 REG_A8XX_CP_PROTECT_GLOBAL(36),
2042 REG_A8XX_CP_PROTECT_GLOBAL(37),
2043 REG_A8XX_CP_PROTECT_GLOBAL(38),
2044 REG_A8XX_CP_PROTECT_GLOBAL(39),
2045 REG_A8XX_CP_PROTECT_GLOBAL(40),
2046 REG_A8XX_CP_PROTECT_GLOBAL(41),
2047 REG_A8XX_CP_PROTECT_GLOBAL(42),
2048 REG_A8XX_CP_PROTECT_GLOBAL(43),
2049 REG_A8XX_CP_PROTECT_GLOBAL(44),
2050 REG_A8XX_CP_PROTECT_GLOBAL(45),
2051 REG_A8XX_CP_PROTECT_GLOBAL(46),
2052 REG_A8XX_CP_PROTECT_GLOBAL(47),
2053 REG_A8XX_CP_PROTECT_GLOBAL(48),
2054 REG_A8XX_CP_PROTECT_GLOBAL(49),
2055 REG_A8XX_CP_PROTECT_GLOBAL(50),
2056 REG_A8XX_CP_PROTECT_GLOBAL(51),
2057 REG_A8XX_CP_PROTECT_GLOBAL(52),
2058 REG_A8XX_CP_PROTECT_GLOBAL(53),
2059 REG_A8XX_CP_PROTECT_GLOBAL(54),
2060 REG_A8XX_CP_PROTECT_GLOBAL(55),
2061 REG_A8XX_CP_PROTECT_GLOBAL(56),
2062 REG_A8XX_CP_PROTECT_GLOBAL(57),
2063 REG_A8XX_CP_PROTECT_GLOBAL(58),
2064 REG_A8XX_CP_PROTECT_GLOBAL(59),
2065 REG_A8XX_CP_PROTECT_GLOBAL(60),
2066 REG_A8XX_CP_PROTECT_GLOBAL(61),
2067 REG_A8XX_CP_PROTECT_GLOBAL(62),
2068 REG_A8XX_CP_PROTECT_GLOBAL(63),
2069 };
2070 DECLARE_ADRENO_REGLIST_LIST(a840_ifpc_reglist);
2071
2072 static const struct adreno_reglist_pipe a840_dyn_pwrup_reglist_regs[] = {
2073 { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
2074 { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
2075 { REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
2076 { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
2077 { REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
2078 { REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
2079 { REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
2080 { REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
2081 { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
2082 { REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
2083 { REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) },
2084 { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR)},
2085 { REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) },
2086 { REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) },
2087 { REG_A6XX_RB_RBP_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
2088 { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) },
2089 { REG_A6XX_RB_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
2090 { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) },
2091 { REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
2092 { REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
2093 { REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
2094 { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
2095 { REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
2096 { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
2097 { REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) |
2098 BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) |
2099 BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) },
2100 { REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) |
2101 BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) |
2102 BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) },
2103 { REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC)},
2104 { REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC) },
2105 { REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) },
2106 { REG_A8XX_RB_LPAC_GMEM_PROTECT, 0, BIT(PIPE_BR) },
2107 { REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) },
2108 };
2109 DECLARE_ADRENO_REGLIST_PIPE_LIST(a840_dyn_pwrup_reglist);
2110
2111 static const struct adreno_info a8xx_gpus[] = {
2112 {
2113 .chip_ids = ADRENO_CHIP_IDS(0x44070001),
2114 .family = ADRENO_8XX_GEN2,
2115 .fw = {
2116 [ADRENO_FW_SQE] = "gen80100_sqe.fw",
2117 [ADRENO_FW_GMU] = "gen80100_gmu.bin",
2118 },
2119 .gmem = 21 * SZ_1M,
2120 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
2121 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
2122 ADRENO_QUIRK_HAS_HW_APRIV |
2123 ADRENO_QUIRK_PREEMPTION |
2124 ADRENO_QUIRK_SOFTFUSE,
2125 .funcs = &a8xx_gpu_funcs,
2126 .a6xx = &(const struct a6xx_info) {
2127 .protect = &x285_protect,
2128 .nonctxt_reglist = x285_nonctxt_regs,
2129 .pwrup_reglist = &a840_pwrup_reglist,
2130 .dyn_pwrup_reglist = &x285_dyn_pwrup_reglist,
2131 .ifpc_reglist = &a840_ifpc_reglist,
2132 .gbif_cx = a840_gbif,
2133 .max_slices = 4,
2134 .gmu_chipid = 0x8010100,
2135 .bcms = (const struct a6xx_bcm[]) {
2136 { .name = "SH0", .buswidth = 16 },
2137 { .name = "MC0", .buswidth = 4 },
2138 {
2139 .name = "ACV",
2140 .fixed = true,
2141 .perfmode = BIT(2),
2142 .perfmode_bw = 16500000,
2143 },
2144 { /* sentinel */ },
2145 },
2146 },
2147 .speedbins = ADRENO_SPEEDBINS(
2148 { 0, 0 },
2149 { 388, 1 },
2150 { 357, 2 },
2151 { 284, 3 },
2152 ),
2153 }, {
2154 .chip_ids = ADRENO_CHIP_IDS(0x44050a01),
2155 .family = ADRENO_8XX_GEN2,
2156 .fw = {
2157 [ADRENO_FW_SQE] = "gen80200_sqe.fw",
2158 [ADRENO_FW_GMU] = "gen80200_gmu.bin",
2159 [ADRENO_FW_AQE] = "gen80200_aqe.fw",
2160 },
2161 .gmem = 18 * SZ_1M,
2162 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
2163 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
2164 ADRENO_QUIRK_HAS_HW_APRIV |
2165 ADRENO_QUIRK_PREEMPTION |
2166 ADRENO_QUIRK_IFPC,
2167 .funcs = &a8xx_gpu_funcs,
2168 .a6xx = &(const struct a6xx_info) {
2169 .protect = &a840_protect,
2170 .nonctxt_reglist = a840_nonctxt_regs,
2171 .pwrup_reglist = &a840_pwrup_reglist,
2172 .dyn_pwrup_reglist = &a840_dyn_pwrup_reglist,
2173 .ifpc_reglist = &a840_ifpc_reglist,
2174 .gbif_cx = a840_gbif,
2175 .max_slices = 3,
2176 .gmu_chipid = 0x8020100,
2177 .bcms = (const struct a6xx_bcm[]) {
2178 { .name = "SH0", .buswidth = 16 },
2179 { .name = "MC0", .buswidth = 4 },
2180 {
2181 .name = "ACV",
2182 .fixed = true,
2183 .perfmode = BIT(2),
2184 .perfmode_bw = 10687500,
2185 },
2186 { /* sentinel */ },
2187 },
2188 },
2189 .preempt_record_size = 19708 * SZ_1K,
2190 .speedbins = ADRENO_SPEEDBINS(
2191 { 0, 0 },
2192 { 273, 1 },
2193 { 252, 2 },
2194 { 221, 3 },
2195 ),
2196 }
2197 };
2198
2199 DECLARE_ADRENO_GPULIST(a8xx);
2200
__build_asserts(void)2201 static inline __always_unused void __build_asserts(void)
2202 {
2203 BUILD_BUG_ON(a630_protect.count > a630_protect.count_max);
2204 BUILD_BUG_ON(a650_protect.count > a650_protect.count_max);
2205 BUILD_BUG_ON(a660_protect.count > a660_protect.count_max);
2206 BUILD_BUG_ON(a690_protect.count > a690_protect.count_max);
2207 BUILD_BUG_ON(a730_protect.count > a730_protect.count_max);
2208 }
2209