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Searched refs:_REG (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/meson/
H A Dmeson_venc.c1046 priv->io_base + _REG(VENC_VDAC_SETTING)); in meson_venc_hdmi_mode_set()
1048 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in meson_venc_hdmi_mode_set()
1049 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in meson_venc_hdmi_mode_set()
1057 priv->io_base + _REG(ENCI_CFILT_CTRL)); in meson_venc_hdmi_mode_set()
1060 priv->io_base + _REG(ENCI_CFILT_CTRL2)); in meson_venc_hdmi_mode_set()
1063 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); in meson_venc_hdmi_mode_set()
1066 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE)); in meson_venc_hdmi_mode_set()
1067 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); in meson_venc_hdmi_mode_set()
1071 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN)); in meson_venc_hdmi_mode_set()
1073 priv->io_base + _REG(ENCI_SYNC_HSO_END)); in meson_venc_hdmi_mode_set()
[all …]
H A Dmeson_viu.c86 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
88 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
90 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF00_01)); in meson_viu_set_g12a_osd1_matrix()
92 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF02_10)); in meson_viu_set_g12a_osd1_matrix()
94 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12)); in meson_viu_set_g12a_osd1_matrix()
96 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21)); in meson_viu_set_g12a_osd1_matrix()
98 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22)); in meson_viu_set_g12a_osd1_matrix()
101 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
103 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
106 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL)); in meson_viu_set_g12a_osd1_matrix()
[all …]
H A Dmeson_crtc.c100 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END)); in meson_g12a_crtc_atomic_enable()
105 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); in meson_g12a_crtc_atomic_enable()
109 priv->io_base + _REG(VPP_OSD1_BLD_H_SCOPE)); in meson_g12a_crtc_atomic_enable()
112 priv->io_base + _REG(VPP_OSD1_BLD_V_SCOPE)); in meson_g12a_crtc_atomic_enable()
115 priv->io_base + _REG(VPP_OUT_H_V_SIZE)); in meson_g12a_crtc_atomic_enable()
136 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); in meson_crtc_atomic_enable()
140 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END)); in meson_crtc_atomic_enable()
143 priv->io_base + _REG(VPP_MISC)); in meson_crtc_atomic_enable()
192 priv->io_base + _REG(VPP_MISC)); in meson_crtc_atomic_disable()
246 priv->io_base + _REG(VPP_MISC)); in meson_crtc_enable_osd1()
[all …]
H A Dmeson_vpp.c38 writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL)); in meson_vpp_setup_mux()
60 priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX)); in meson_vpp_write_scaling_filter_coefs()
63 priv->io_base + _REG(VPP_OSD_SCALE_COEF)); in meson_vpp_write_scaling_filter_coefs()
85 priv->io_base + _REG(VPP_SCALE_COEF_IDX)); in meson_vpp_write_vd_scaling_filter_coefs()
88 priv->io_base + _REG(VPP_SCALE_COEF)); in meson_vpp_write_vd_scaling_filter_coefs()
95 writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
98 priv->io_base + _REG(VIU_MISC_CTRL1)); in meson_vpp_init()
100 priv->io_base + _REG(VPP_DOLBY_CTRL)); in meson_vpp_init()
102 priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
104 priv->io_base + _REG(VPP_DUMMY_DATA)); in meson_vpp_init()
[all …]
H A Dmeson_rdma.c39 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_init()
43 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_init()
68 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_setup()
75 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_stop()
81 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_stop()
113 writel_relaxed(val, priv->io_base + _REG(reg)); in meson_rdma_writel_sync()
122 priv->io_base + _REG(RDMA_AHB_START_ADDR_1)); in meson_rdma_flush()
126 priv->io_base + _REG(RDMA_AHB_END_ADDR_1)); in meson_rdma_flush()
132 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_flush()
H A Dmeson_osd_afbcd.c85 priv->io_base + _REG(VIU_SW_RESET)); in meson_gxm_afbcd_reset()
86 writel_relaxed(0, priv->io_base + _REG(VIU_SW_RESET)); in meson_gxm_afbcd_reset()
105 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); in meson_gxm_afbcd_enable()
113 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); in meson_gxm_afbcd_disable()
133 writel_relaxed(mode, priv->io_base + _REG(OSD1_AFBCD_MODE)); in meson_gxm_afbcd_setup()
139 priv->io_base + _REG(OSD1_AFBCD_SIZE_IN)); in meson_gxm_afbcd_setup()
142 priv->io_base + _REG(OSD1_AFBCD_HDR_PTR)); in meson_gxm_afbcd_setup()
144 priv->io_base + _REG(OSD1_AFBCD_FRAME_PTR)); in meson_gxm_afbcd_setup()
147 priv->io_base + _REG(OSD1_AFBCD_CHROMA_PTR)); in meson_gxm_afbcd_setup()
163 priv->io_base + _REG(OSD1_AFBCD_CONV_CTRL)); in meson_gxm_afbcd_setup()
[all …]
H A Dmeson_encoder_hdmi.c238 priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); in meson_encoder_hdmi_atomic_enable()
242 priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); in meson_encoder_hdmi_atomic_enable()
245 writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); in meson_encoder_hdmi_atomic_enable()
250 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); in meson_encoder_hdmi_atomic_enable()
252 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); in meson_encoder_hdmi_atomic_enable()
262 priv->io_base + _REG(VPU_HDMI_SETTING)); in meson_encoder_hdmi_atomic_disable()
264 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in meson_encoder_hdmi_atomic_disable()
265 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in meson_encoder_hdmi_atomic_disable()
H A Dmeson_dw_hdmi.c366 readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
412 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in dw_hdmi_phy_init()
414 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in dw_hdmi_phy_init()
418 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
420 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
424 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); in dw_hdmi_phy_init()
426 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); in dw_hdmi_phy_init()
430 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
435 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
438 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
H A Dmeson_drv.c76 (void)readl_relaxed(priv->io_base + _REG(VENC_INTFLAG)); in meson_irq()
147 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1)); in meson_vpu_init()
151 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2)); in meson_vpu_init()
156 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1)); in meson_vpu_init()
160 writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); in meson_vpu_init()
H A Dmeson_registers.h12 #define _REG(reg) ((reg) << 2) macro
/linux/sound/soc/qcom/
H A Dlpass-lpaif-reg.h149 LPAIF_HDMI_RDMA##reg##_REG(v, chan) : \
150 LPAIF_RDMA##reg##_REG(v, chan))
155 LPAIF_WRDMA##reg##_REG(v, chan))
242 (is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_RDMA##reg##_REG(v, chan, dai_id) : \
243 LPAIF_CDC_VA_RDMA##reg##_REG(v, chan, dai_id))
246 (is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_WRDMA##reg##_REG(v, chan, dai_id) : \
247 LPAIF_CDC_VA_WRDMA##reg##_REG(v, chan, dai_id))