1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _ZL3073X_REGS_H 4 #define _ZL3073X_REGS_H 5 6 #include <linux/bitfield.h> 7 #include <linux/bits.h> 8 #include <linux/limits.h> 9 10 /* 11 * Hardware limits for ZL3073x chip family 12 */ 13 #define ZL3073X_MAX_CHANNELS 5 14 #define ZL3073X_NUM_REFS 10 15 #define ZL3073X_NUM_OUTS 10 16 #define ZL3073X_NUM_SYNTHS 5 17 #define ZL3073X_NUM_INPUT_PINS ZL3073X_NUM_REFS 18 #define ZL3073X_NUM_OUTPUT_PINS (ZL3073X_NUM_OUTS * 2) 19 #define ZL3073X_NUM_PINS (ZL3073X_NUM_INPUT_PINS + \ 20 ZL3073X_NUM_OUTPUT_PINS) 21 #define ZL3073X_NCO_PIN_ID ZL3073X_NUM_PINS 22 23 /* 24 * Register address structure: 25 * =========================== 26 * 25 19 18 16 15 7 6 0 27 * +------------------------------------------+ 28 * | max_offset | size | page | page_offset | 29 * +------------------------------------------+ 30 * 31 * page_offset ... <0x00..0x7F> 32 * page .......... HW page number 33 * size .......... register byte size (1, 2, 4 or 6) 34 * max_offset .... maximal offset for indexed registers 35 * (for non-indexed regs max_offset == page_offset) 36 */ 37 38 #define ZL_REG_OFFSET_MASK GENMASK(6, 0) 39 #define ZL_REG_PAGE_MASK GENMASK(15, 7) 40 #define ZL_REG_SIZE_MASK GENMASK(18, 16) 41 #define ZL_REG_MAX_OFFSET_MASK GENMASK(25, 19) 42 #define ZL_REG_ADDR_MASK GENMASK(15, 0) 43 44 #define ZL_REG_OFFSET(_reg) FIELD_GET(ZL_REG_OFFSET_MASK, _reg) 45 #define ZL_REG_PAGE(_reg) FIELD_GET(ZL_REG_PAGE_MASK, _reg) 46 #define ZL_REG_MAX_OFFSET(_reg) FIELD_GET(ZL_REG_MAX_OFFSET_MASK, _reg) 47 #define ZL_REG_SIZE(_reg) FIELD_GET(ZL_REG_SIZE_MASK, _reg) 48 #define ZL_REG_ADDR(_reg) FIELD_GET(ZL_REG_ADDR_MASK, _reg) 49 50 /** 51 * ZL_REG_IDX - define indexed register 52 * @_idx: index of register to access 53 * @_page: register page 54 * @_offset: register offset in page 55 * @_size: register byte size (1, 2, 4 or 6) 56 * @_items: number of register indices 57 * @_stride: stride between items in bytes 58 * 59 * All parameters except @_idx should be constant. 60 */ 61 #define ZL_REG_IDX(_idx, _page, _offset, _size, _items, _stride) \ 62 (FIELD_PREP(ZL_REG_OFFSET_MASK, \ 63 (_offset) + (_idx) * (_stride)) | \ 64 FIELD_PREP_CONST(ZL_REG_PAGE_MASK, _page) | \ 65 FIELD_PREP_CONST(ZL_REG_SIZE_MASK, _size) | \ 66 FIELD_PREP_CONST(ZL_REG_MAX_OFFSET_MASK, \ 67 (_offset) + ((_items) - 1) * (_stride))) 68 69 /** 70 * ZL_REG - define simple (non-indexed) register 71 * @_page: register page 72 * @_offset: register offset in page 73 * @_size: register byte size (1, 2, 4 or 6) 74 * 75 * All parameters should be constant. 76 */ 77 #define ZL_REG(_page, _offset, _size) \ 78 ZL_REG_IDX(0, _page, _offset, _size, 1, 0) 79 80 /************************** 81 * Register Page 0, General 82 **************************/ 83 84 #define ZL_REG_INFO ZL_REG(0, 0x00, 1) 85 #define ZL_INFO_READY BIT(7) 86 87 #define ZL_REG_ID ZL_REG(0, 0x01, 2) 88 #define ZL_REG_REVISION ZL_REG(0, 0x03, 2) 89 #define ZL_REG_FW_VER ZL_REG(0, 0x05, 2) 90 #define ZL_REG_CUSTOM_CONFIG_VER ZL_REG(0, 0x07, 4) 91 92 #define ZL_REG_RESET_STATUS ZL_REG(0, 0x18, 1) 93 #define ZL_REG_RESET_STATUS_RESET BIT(0) 94 95 #define ZL_REG_DIE_TEMP_STATUS ZL_REG(0, 0x44, 2) 96 97 /************************* 98 * Register Page 2, Status 99 *************************/ 100 101 #define ZL_REG_REF_MON_STATUS(_idx) \ 102 ZL_REG_IDX(_idx, 2, 0x02, 1, ZL3073X_NUM_REFS, 1) 103 #define ZL_REF_MON_STATUS_OK 0 104 #define ZL_REF_MON_STATUS_LOS BIT(0) 105 #define ZL_REF_MON_STATUS_SCM BIT(1) 106 #define ZL_REF_MON_STATUS_CFM BIT(2) 107 #define ZL_REF_MON_STATUS_GST BIT(3) 108 #define ZL_REF_MON_STATUS_PFM BIT(4) 109 #define ZL_REF_MON_STATUS_ESYNC BIT(6) 110 #define ZL_REF_MON_STATUS_SPLIT_XO BIT(7) 111 112 #define ZL_REG_DPLL_MON_STATUS(_idx) \ 113 ZL_REG_IDX(_idx, 2, 0x10, 1, ZL3073X_MAX_CHANNELS, 1) 114 #define ZL_DPLL_MON_STATUS_STATE GENMASK(1, 0) 115 #define ZL_DPLL_MON_STATUS_STATE_ACQUIRING 0 116 #define ZL_DPLL_MON_STATUS_STATE_LOCK 1 117 #define ZL_DPLL_MON_STATUS_STATE_HOLDOVER 2 118 #define ZL_DPLL_MON_STATUS_HO_READY BIT(2) 119 120 #define ZL_REG_DPLL_REFSEL_STATUS(_idx) \ 121 ZL_REG_IDX(_idx, 2, 0x30, 1, ZL3073X_MAX_CHANNELS, 1) 122 #define ZL_DPLL_REFSEL_STATUS_REFSEL GENMASK(3, 0) 123 #define ZL_DPLL_REFSEL_STATUS_STATE GENMASK(6, 4) 124 #define ZL_DPLL_REFSEL_STATUS_STATE_LOCK 4 125 126 #define ZL_REG_REF_FREQ(_idx) \ 127 ZL_REG_IDX(_idx, 2, 0x44, 4, ZL3073X_NUM_REFS, 4) 128 129 /********************** 130 * Register Page 4, Ref 131 **********************/ 132 133 #define ZL_REG_REF_PHASE_ERR_READ_RQST ZL_REG(4, 0x0f, 1) 134 #define ZL_REF_PHASE_ERR_READ_RQST_RD BIT(0) 135 136 #define ZL_REG_REF_FREQ_MEAS_CTRL ZL_REG(4, 0x1c, 1) 137 #define ZL_REF_FREQ_MEAS_CTRL GENMASK(1, 0) 138 #define ZL_REF_FREQ_MEAS_CTRL_REF_FREQ 1 139 #define ZL_REF_FREQ_MEAS_CTRL_REF_FREQ_OFF 2 140 #define ZL_REF_FREQ_MEAS_CTRL_DPLL_FREQ_OFF 3 141 142 #define ZL_REG_REF_FREQ_MEAS_MASK_3_0 ZL_REG(4, 0x1d, 1) 143 #define ZL_REF_FREQ_MEAS_MASK_3_0(_ref) BIT(_ref) 144 145 #define ZL_REG_REF_FREQ_MEAS_MASK_4 ZL_REG(4, 0x1e, 1) 146 #define ZL_REF_FREQ_MEAS_MASK_4(_ref) BIT((_ref) - 8) 147 148 #define ZL_REG_DPLL_MEAS_REF_FREQ_CTRL ZL_REG(4, 0x1f, 1) 149 #define ZL_DPLL_MEAS_REF_FREQ_CTRL_EN BIT(0) 150 #define ZL_DPLL_MEAS_REF_FREQ_CTRL_IDX GENMASK(6, 4) 151 152 #define ZL_REG_REF_PHASE(_idx) \ 153 ZL_REG_IDX(_idx, 4, 0x20, 6, ZL3073X_NUM_REFS, 6) 154 155 /*********************** 156 * Register Page 5, DPLL 157 ***********************/ 158 159 #define ZL_REG_DPLL_MODE_REFSEL(_idx) \ 160 ZL_REG_IDX(_idx, 5, 0x04, 1, ZL3073X_MAX_CHANNELS, 4) 161 #define ZL_DPLL_MODE_REFSEL_MODE GENMASK(2, 0) 162 #define ZL_DPLL_MODE_REFSEL_MODE_FREERUN 0 163 #define ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER 1 164 #define ZL_DPLL_MODE_REFSEL_MODE_REFLOCK 2 165 #define ZL_DPLL_MODE_REFSEL_MODE_AUTO 3 166 #define ZL_DPLL_MODE_REFSEL_MODE_NCO 4 167 #define ZL_DPLL_MODE_REFSEL_REF GENMASK(7, 4) 168 169 #define ZL_REG_DPLL_CTRL(_idx) \ 170 ZL_REG_IDX(_idx, 5, 0x05, 1, ZL3073X_MAX_CHANNELS, 4) 171 #define ZL_DPLL_CTRL_TIE_CLEAR BIT(0) 172 #define ZL_DPLL_CTRL_TOD_STEP_RST BIT(2) 173 #define ZL_DPLL_CTRL_NCO_AUTO_READ BIT(7) 174 175 #define ZL_REG_DPLL_DF_READ(_idx) \ 176 ZL_REG_IDX(_idx, 5, 0x28, 1, ZL3073X_MAX_CHANNELS, 1) 177 #define ZL_DPLL_DF_READ_SEM BIT(4) 178 #define ZL_DPLL_DF_READ_REF_OFST BIT(3) 179 #define ZL_DPLL_DF_READ_CMD GENMASK(2, 0) 180 #define ZL_DPLL_DF_READ_CMD_ACC_I 4 181 182 #define ZL_REG_DPLL_TIE_CTRL ZL_REG(5, 0x30, 1) 183 #define ZL_DPLL_TIE_CTRL_OP GENMASK(2, 0) 184 #define ZL_DPLL_TIE_CTRL_OP_WR 4 185 186 #define ZL_REG_DPLL_TIE_CTRL_MASK ZL_REG(5, 0x31, 1) 187 188 #define ZL_REG_DPLL_TOD_CTRL(_idx) \ 189 ZL_REG_IDX(_idx, 5, 0x38, 1, ZL3073X_MAX_CHANNELS, 1) 190 #define ZL_DPLL_TOD_CTRL_SEM BIT(4) 191 #define ZL_DPLL_TOD_CTRL_CMD GENMASK(3, 0) 192 #define ZL_DPLL_TOD_CTRL_CMD_WR_NEXT_1HZ 1 193 #define ZL_DPLL_TOD_CTRL_CMD_RD_CURRENT 8 194 #define ZL_DPLL_TOD_CTRL_CMD_RD_NEXT_1HZ 9 195 196 #define ZL_REG_DPLL_MEAS_CTRL ZL_REG(5, 0x50, 1) 197 #define ZL_DPLL_MEAS_CTRL_EN BIT(0) 198 #define ZL_DPLL_MEAS_CTRL_AVG_FACTOR GENMASK(7, 4) 199 200 #define ZL_REG_DPLL_MEAS_IDX ZL_REG(5, 0x51, 1) 201 #define ZL_DPLL_MEAS_IDX GENMASK(2, 0) 202 203 #define ZL_REG_DPLL_PHASE_ERR_READ_MASK ZL_REG(5, 0x54, 1) 204 205 #define ZL_REG_DPLL_PHASE_ERR_DATA(_idx) \ 206 ZL_REG_IDX(_idx, 5, 0x55, 6, ZL3073X_MAX_CHANNELS, 6) 207 208 /******************************* 209 * Register Pages 6-7, DPLL Data 210 * 211 * Per-channel registers with stride 0x20. Channels 0-3 reside on page 6, 212 * channel 4 on page 7. 213 *******************************/ 214 215 #define ZL_REG_DPLL_DF_OFFSET_03(_idx) \ 216 ZL_REG_IDX(_idx, 6, 0x00, 6, 4, 0x20) 217 #define ZL_REG_DPLL_DF_OFFSET_4 ZL_REG(7, 0x00, 6) 218 #define ZL_REG_DPLL_DF_OFFSET(_idx) \ 219 ((_idx) < 4 ? ZL_REG_DPLL_DF_OFFSET_03(_idx) : ZL_REG_DPLL_DF_OFFSET_4) 220 #define ZL_DPLL_DF_OFFSET_UNKNOWN S64_MIN 221 222 #define ZL_REG_DPLL_TIE_DATA_03(_idx) \ 223 ZL_REG_IDX(_idx, 6, 0x0C, 6, 4, 0x20) 224 #define ZL_REG_DPLL_TIE_DATA_4 ZL_REG(7, 0x0C, 6) 225 #define ZL_REG_DPLL_TIE_DATA(_idx) \ 226 ((_idx) < 4 ? ZL_REG_DPLL_TIE_DATA_03(_idx) : ZL_REG_DPLL_TIE_DATA_4) 227 228 #define ZL_REG_DPLL_TOD_SEC_03(_idx) \ 229 ZL_REG_IDX(_idx, 6, 0x12, 6, 4, 0x20) 230 #define ZL_REG_DPLL_TOD_SEC_4 ZL_REG(7, 0x12, 6) 231 #define ZL_REG_DPLL_TOD_SEC(_idx) \ 232 ((_idx) < 4 ? ZL_REG_DPLL_TOD_SEC_03(_idx) : ZL_REG_DPLL_TOD_SEC_4) 233 234 #define ZL_REG_DPLL_TOD_NS_03(_idx) \ 235 ZL_REG_IDX(_idx, 6, 0x18, 4, 4, 0x20) 236 #define ZL_REG_DPLL_TOD_NS_4 ZL_REG(7, 0x18, 4) 237 #define ZL_REG_DPLL_TOD_NS(_idx) \ 238 ((_idx) < 4 ? ZL_REG_DPLL_TOD_NS_03(_idx) : ZL_REG_DPLL_TOD_NS_4) 239 240 /*********************************** 241 * Register Page 9, Synth and Output 242 ***********************************/ 243 244 #define ZL_REG_SYNTH_CTRL(_idx) \ 245 ZL_REG_IDX(_idx, 9, 0x00, 1, ZL3073X_NUM_SYNTHS, 1) 246 #define ZL_SYNTH_CTRL_EN BIT(0) 247 #define ZL_SYNTH_CTRL_DPLL_SEL GENMASK(6, 4) 248 249 #define ZL_REG_SYNTH_PHASE_SHIFT_CTRL ZL_REG(9, 0x1e, 1) 250 #define ZL_REG_SYNTH_PHASE_SHIFT_MASK ZL_REG(9, 0x1f, 1) 251 #define ZL_REG_SYNTH_PHASE_SHIFT_INTVL ZL_REG(9, 0x20, 1) 252 #define ZL_REG_SYNTH_PHASE_SHIFT_DATA ZL_REG(9, 0x21, 2) 253 254 #define ZL_REG_OUTPUT_CTRL(_idx) \ 255 ZL_REG_IDX(_idx, 9, 0x28, 1, ZL3073X_NUM_OUTS, 1) 256 #define ZL_OUTPUT_CTRL_EN BIT(0) 257 #define ZL_OUTPUT_CTRL_SYNTH_SEL GENMASK(6, 4) 258 259 #define ZL_REG_OUTPUT_STEP_TIME_MASK ZL_REG(9, 0x36, 2) 260 261 #define ZL_REG_OUTPUT_PHASE_STEP_CTRL ZL_REG(9, 0x38, 1) 262 #define ZL_OUTPUT_PHASE_STEP_CTRL_DPLL GENMASK(6, 4) 263 #define ZL_OUTPUT_PHASE_STEP_CTRL_TOD_STEP BIT(3) 264 #define ZL_OUTPUT_PHASE_STEP_CTRL_OP GENMASK(1, 0) 265 #define ZL_OUTPUT_PHASE_STEP_CTRL_OP_NONE 0 266 #define ZL_OUTPUT_PHASE_STEP_CTRL_OP_RESET 1 267 #define ZL_OUTPUT_PHASE_STEP_CTRL_OP_READ 2 268 #define ZL_OUTPUT_PHASE_STEP_CTRL_OP_WRITE 3 269 270 #define ZL_REG_OUTPUT_PHASE_STEP_NUMBER ZL_REG(9, 0x39, 1) 271 272 #define ZL_REG_OUTPUT_PHASE_STEP_MASK ZL_REG(9, 0x3a, 2) 273 274 #define ZL_REG_OUTPUT_PHASE_STEP_DATA ZL_REG(9, 0x3c, 4) 275 276 /******************************* 277 * Register Page 10, Ref Mailbox 278 *******************************/ 279 280 #define ZL_REG_REF_MB_MASK ZL_REG(10, 0x02, 2) 281 282 #define ZL_REG_REF_MB_SEM ZL_REG(10, 0x04, 1) 283 #define ZL_REF_MB_SEM_WR BIT(0) 284 #define ZL_REF_MB_SEM_RD BIT(1) 285 286 #define ZL_REG_REF_FREQ_BASE ZL_REG(10, 0x05, 2) 287 #define ZL_REG_REF_FREQ_MULT ZL_REG(10, 0x07, 2) 288 #define ZL_REG_REF_RATIO_M ZL_REG(10, 0x09, 2) 289 #define ZL_REG_REF_RATIO_N ZL_REG(10, 0x0b, 2) 290 291 #define ZL_REG_REF_CONFIG ZL_REG(10, 0x0d, 1) 292 #define ZL_REF_CONFIG_ENABLE BIT(0) 293 #define ZL_REF_CONFIG_DIFF_EN BIT(2) 294 295 #define ZL_REG_REF_PHASE_OFFSET_COMP ZL_REG(10, 0x28, 6) 296 #define ZL_REG_REF_PHASE_OFFSET_COMP_32 ZL_REG(10, 0x28, 4) 297 298 #define ZL_REG_REF_SYNC_CTRL ZL_REG(10, 0x2e, 1) 299 #define ZL_REF_SYNC_CTRL_MODE GENMASK(2, 0) 300 #define ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF 0 301 #define ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR 1 302 #define ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75 2 303 #define ZL_REF_SYNC_CTRL_PAIR GENMASK(7, 4) 304 305 #define ZL_REG_REF_ESYNC_DIV ZL_REG(10, 0x30, 4) 306 #define ZL_REF_ESYNC_DIV_1HZ 0 307 308 /******************************** 309 * Register Page 12, DPLL Mailbox 310 ********************************/ 311 312 #define ZL_REG_DPLL_MB_MASK ZL_REG(12, 0x02, 2) 313 314 #define ZL_REG_DPLL_MB_SEM ZL_REG(12, 0x04, 1) 315 #define ZL_DPLL_MB_SEM_WR BIT(0) 316 #define ZL_DPLL_MB_SEM_RD BIT(1) 317 318 #define ZL_REG_DPLL_REF_PRIO(_idx) \ 319 ZL_REG_IDX(_idx, 12, 0x52, 1, ZL3073X_NUM_REFS / 2, 1) 320 #define ZL_DPLL_REF_PRIO_REF_P GENMASK(3, 0) 321 #define ZL_DPLL_REF_PRIO_REF_N GENMASK(7, 4) 322 #define ZL_DPLL_REF_PRIO_MAX 14 323 #define ZL_DPLL_REF_PRIO_NONE 15 324 325 /********************************* 326 * Register Page 13, Synth Mailbox 327 *********************************/ 328 329 #define ZL_REG_SYNTH_MB_MASK ZL_REG(13, 0x02, 2) 330 331 #define ZL_REG_SYNTH_MB_SEM ZL_REG(13, 0x04, 1) 332 #define ZL_SYNTH_MB_SEM_WR BIT(0) 333 #define ZL_SYNTH_MB_SEM_RD BIT(1) 334 335 #define ZL_REG_SYNTH_FREQ_BASE ZL_REG(13, 0x06, 2) 336 #define ZL_REG_SYNTH_FREQ_MULT ZL_REG(13, 0x08, 4) 337 #define ZL_REG_SYNTH_FREQ_M ZL_REG(13, 0x0c, 2) 338 #define ZL_REG_SYNTH_FREQ_N ZL_REG(13, 0x0e, 2) 339 340 /********************************** 341 * Register Page 14, Output Mailbox 342 **********************************/ 343 #define ZL_REG_OUTPUT_MB_MASK ZL_REG(14, 0x02, 2) 344 345 #define ZL_REG_OUTPUT_MB_SEM ZL_REG(14, 0x04, 1) 346 #define ZL_OUTPUT_MB_SEM_WR BIT(0) 347 #define ZL_OUTPUT_MB_SEM_RD BIT(1) 348 349 #define ZL_REG_OUTPUT_MODE ZL_REG(14, 0x05, 1) 350 #define ZL_OUTPUT_MODE_CLOCK_TYPE GENMASK(2, 0) 351 #define ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL 0 352 #define ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC 1 353 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT GENMASK(7, 4) 354 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_DISABLED 0 355 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_LVDS 1 356 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_DIFF 2 357 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_LOWVCM 3 358 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2 4 359 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_1P 5 360 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_1N 6 361 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_INV 7 362 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV 12 363 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV 15 364 365 #define ZL_REG_OUTPUT_DIV ZL_REG(14, 0x0c, 4) 366 #define ZL_REG_OUTPUT_WIDTH ZL_REG(14, 0x10, 4) 367 #define ZL_REG_OUTPUT_ESYNC_PERIOD ZL_REG(14, 0x14, 4) 368 #define ZL_REG_OUTPUT_ESYNC_WIDTH ZL_REG(14, 0x18, 4) 369 #define ZL_REG_OUTPUT_PHASE_COMP ZL_REG(14, 0x20, 4) 370 371 /* 372 * Register Page 255 - HW registers access 373 */ 374 #define ZL_REG_HWREG_OP ZL_REG(0xff, 0x00, 1) 375 #define ZL_HWREG_OP_WRITE 0x28 376 #define ZL_HWREG_OP_READ 0x29 377 #define ZL_HWREG_OP_PENDING BIT(1) 378 379 #define ZL_REG_HWREG_ADDR ZL_REG(0xff, 0x04, 4) 380 #define ZL_REG_HWREG_WRITE_DATA ZL_REG(0xff, 0x08, 4) 381 #define ZL_REG_HWREG_READ_DATA ZL_REG(0xff, 0x0c, 4) 382 383 /* 384 * Registers available in flash mode 385 */ 386 #define ZL_REG_FLASH_HASH ZL_REG(0, 0x78, 4) 387 #define ZL_REG_FLASH_FAMILY ZL_REG(0, 0x7c, 1) 388 #define ZL_REG_FLASH_RELEASE ZL_REG(0, 0x7d, 1) 389 390 #define ZL_REG_HOST_CONTROL ZL_REG(1, 0x02, 1) 391 #define ZL_HOST_CONTROL_ENABLE BIT(0) 392 393 #define ZL_REG_IMAGE_START_ADDR ZL_REG(1, 0x04, 4) 394 #define ZL_REG_IMAGE_SIZE ZL_REG(1, 0x08, 4) 395 #define ZL_REG_FLASH_INDEX_READ ZL_REG(1, 0x0c, 4) 396 #define ZL_REG_FLASH_INDEX_WRITE ZL_REG(1, 0x10, 4) 397 #define ZL_REG_FILL_PATTERN ZL_REG(1, 0x14, 4) 398 399 #define ZL_REG_WRITE_FLASH ZL_REG(1, 0x18, 1) 400 #define ZL_WRITE_FLASH_OP GENMASK(2, 0) 401 #define ZL_WRITE_FLASH_OP_DONE 0x0 402 #define ZL_WRITE_FLASH_OP_SECTORS 0x2 403 #define ZL_WRITE_FLASH_OP_PAGE 0x3 404 #define ZL_WRITE_FLASH_OP_COPY_PAGE 0x4 405 406 #define ZL_REG_FLASH_INFO ZL_REG(2, 0x00, 1) 407 #define ZL_FLASH_INFO_SECTOR_SIZE GENMASK(3, 0) 408 #define ZL_FLASH_INFO_SECTOR_4K 0 409 #define ZL_FLASH_INFO_SECTOR_64K 1 410 411 #define ZL_REG_ERROR_COUNT ZL_REG(2, 0x04, 4) 412 #define ZL_REG_ERROR_CAUSE ZL_REG(2, 0x08, 4) 413 414 #define ZL_REG_OP_STATE ZL_REG(2, 0x14, 1) 415 #define ZL_OP_STATE_NO_COMMAND 0 416 #define ZL_OP_STATE_PENDING 1 417 #define ZL_OP_STATE_DONE 2 418 419 #endif /* _ZL3073X_REGS_H */ 420