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Searched refs:XEHP_L3SQCREG5 (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/xe/
H A Dxe_tuning.c32 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
112 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
131 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
/linux/drivers/gpu/drm/xe/regs/
H A Dxe_gt_regs.h397 #define XEHP_L3SQCREG5 XE_REG_MCR(0xb158) macro
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_regs.h1007 #define XEHP_L3SQCREG5 MCR_REG(0xb158) macro
H A Dintel_workarounds.c682 wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, in dg2_ctx_gt_tuning_init()