1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */
3
4 #ifndef _WX_TYPE_H_
5 #define _WX_TYPE_H_
6
7 #include <linux/ptp_clock_kernel.h>
8 #include <linux/timecounter.h>
9 #include <linux/bitfield.h>
10 #include <linux/netdevice.h>
11 #include <linux/if_vlan.h>
12 #include <linux/phylink.h>
13 #include <linux/dim.h>
14 #include <net/ip.h>
15
16 #define WX_NCSI_SUP 0x8000
17 #define WX_NCSI_MASK 0x8000
18 #define WX_WOL_SUP 0x4000
19 #define WX_WOL_MASK 0x4000
20
21 /* MSI-X capability fields masks */
22 #define WX_PCIE_MSIX_TBL_SZ_MASK 0x7FF
23 #define WX_PCI_LINK_STATUS 0xB2
24 #define WX_MAX_PF_MACVLANS 15
25 #define WX_MAX_VF_MC_ENTRIES 30
26
27 /**************** Global Registers ****************************/
28 #define WX_VF_REG_OFFSET(_v) FIELD_GET(GENMASK(15, 5), (_v))
29 #define WX_VF_IND_SHIFT(_v) FIELD_GET(GENMASK(4, 0), (_v))
30
31 /* chip control Registers */
32 #define WX_MIS_PWR 0x10000
33 #define WX_MIS_RST 0x1000C
34 #define WX_MIS_RST_LAN_RST(_i) BIT((_i) + 1)
35 #define WX_MIS_RST_SW_RST BIT(0)
36 #define WX_MIS_ST 0x10028
37 #define WX_MIS_ST_MNG_INIT_DN BIT(0)
38 #define WX_MIS_SWSM 0x1002C
39 #define WX_MIS_SWSM_SMBI BIT(0)
40 #define WX_MIS_RST_ST 0x10030
41 #define WX_MIS_RST_ST_RST_INI_SHIFT 8
42 #define WX_MIS_RST_ST_RST_INIT (0xFF << WX_MIS_RST_ST_RST_INI_SHIFT)
43
44 /* FMGR Registers */
45 #define WX_SPI_CMD 0x10104
46 #define WX_SPI_CMD_READ_DWORD 0x1
47 #define WX_SPI_CLK_DIV 0x3
48 #define WX_SPI_CMD_CMD(_v) FIELD_PREP(GENMASK(30, 28), _v)
49 #define WX_SPI_CMD_CLK(_v) FIELD_PREP(GENMASK(27, 25), _v)
50 #define WX_SPI_CMD_ADDR(_v) FIELD_PREP(GENMASK(23, 0), _v)
51 #define WX_SPI_DATA 0x10108
52 #define WX_SPI_DATA_BYPASS BIT(31)
53 #define WX_SPI_DATA_OP_DONE BIT(0)
54 #define WX_SPI_STATUS 0x1010C
55 #define WX_SPI_STATUS_OPDONE BIT(0)
56 #define WX_SPI_STATUS_FLASH_BYPASS BIT(31)
57 #define WX_SPI_ILDR_STATUS 0x10120
58
59 /* Sensors for PVT(Process Voltage Temperature) */
60 #define WX_TS_EN 0x10304
61 #define WX_TS_EN_ENA BIT(0)
62 #define WX_TS_ALARM_THRE 0x1030C
63 #define WX_TS_DALARM_THRE 0x10310
64 #define WX_TS_INT_EN 0x10314
65 #define WX_TS_INT_EN_DALARM_INT_EN BIT(1)
66 #define WX_TS_INT_EN_ALARM_INT_EN BIT(0)
67 #define WX_TS_ALARM_ST 0x10318
68 #define WX_TS_ALARM_ST_DALARM BIT(1)
69 #define WX_TS_ALARM_ST_ALARM BIT(0)
70
71 /* statistic */
72 #define WX_TX_FRAME_CNT_GOOD_BAD_L 0x1181C
73 #define WX_TX_BC_FRAMES_GOOD_L 0x11824
74 #define WX_TX_MC_FRAMES_GOOD_L 0x1182C
75 #define WX_RX_FRAME_CNT_GOOD_BAD_L 0x11900
76 #define WX_RX_BC_FRAMES_GOOD_L 0x11918
77 #define WX_RX_MC_FRAMES_GOOD_L 0x11920
78 #define WX_RX_CRC_ERROR_FRAMES_L 0x11928
79 #define WX_RX_LEN_ERROR_FRAMES_L 0x11978
80 #define WX_RX_UNDERSIZE_FRAMES_GOOD 0x11938
81 #define WX_RX_OVERSIZE_FRAMES_GOOD 0x1193C
82 #define WX_MAC_LXOFFRXC 0x11988
83 #define WX_MAC_LXONRXC 0x11E0C
84 #define WX_MAC_LXOFFRXC_AML 0x11F80
85 #define WX_MAC_LXONRXC_AML 0x11F84
86
87 /*********************** Receive DMA registers **************************/
88 #define WX_RDM_VF_RE(_i) (0x12004 + ((_i) * 4))
89 #define WX_RDM_RSC_CTL 0x1200C
90 #define WX_RDM_RSC_CTL_FREE_CNT_DIS BIT(8)
91 #define WX_RDM_RSC_CTL_FREE_CTL BIT(7)
92 #define WX_RDM_PF_QDE(_i) (0x12080 + ((_i) * 4))
93 #define WX_RDM_VFRE_CLR(_i) (0x120A0 + ((_i) * 4))
94 #define WX_RDM_DCACHE_CTL 0x120A8
95 #define WX_RDM_DCACHE_CTL_EN BIT(0)
96 #define WX_RDM_DRP_PKT 0x12500
97 #define WX_RDM_PKT_CNT 0x12504
98 #define WX_RDM_BYTE_CNT_LSB 0x12508
99 #define WX_RDM_BMC2OS_CNT 0x12510
100
101 /************************* Port Registers ************************************/
102 /* port cfg Registers */
103 #define WX_CFG_PORT_CTL 0x14400
104 #define WX_CFG_PORT_CTL_PFRSTD BIT(14)
105 #define WX_CFG_PORT_CTL_DRV_LOAD BIT(3)
106 #define WX_CFG_PORT_CTL_QINQ BIT(2)
107 #define WX_CFG_PORT_CTL_D_VLAN BIT(0) /* double vlan*/
108 #define WX_CFG_PORT_ST 0x14404
109 #define WX_CFG_PORT_ST_LANID GENMASK(9, 8)
110 #define WX_CFG_TAG_TPID(_i) (0x14430 + ((_i) * 4))
111 #define WX_CFG_PORT_CTL_NUM_VT_MASK GENMASK(13, 12) /* number of TVs */
112
113 #define WX_CFG_PORT_CTL_NUM_VT_NONE 0
114 #define WX_CFG_PORT_CTL_NUM_VT_8 FIELD_PREP(GENMASK(13, 12), 1)
115 #define WX_CFG_PORT_CTL_NUM_VT_32 FIELD_PREP(GENMASK(13, 12), 2)
116 #define WX_CFG_PORT_CTL_NUM_VT_64 FIELD_PREP(GENMASK(13, 12), 3)
117
118 /* GPIO Registers */
119 #define WX_GPIO_DR 0x14800
120 #define WX_GPIO_DR_0 BIT(0) /* SDP0 Data Value */
121 #define WX_GPIO_DR_1 BIT(1) /* SDP1 Data Value */
122 #define WX_GPIO_DDR 0x14804
123 #define WX_GPIO_DDR_0 BIT(0) /* SDP0 IO direction */
124 #define WX_GPIO_DDR_1 BIT(1) /* SDP1 IO direction */
125 #define WX_GPIO_CTL 0x14808
126 #define WX_GPIO_INTEN 0x14830
127 #define WX_GPIO_INTEN_0 BIT(0)
128 #define WX_GPIO_INTEN_1 BIT(1)
129 #define WX_GPIO_INTMASK 0x14834
130 #define WX_GPIO_INTTYPE_LEVEL 0x14838
131 #define WX_GPIO_POLARITY 0x1483C
132 #define WX_GPIO_INTSTATUS 0x14844
133 #define WX_GPIO_EOI 0x1484C
134 #define WX_GPIO_EXT 0x14850
135
136 /*********************** Transmit DMA registers **************************/
137 /* transmit global control */
138 #define WX_TDM_CTL 0x18000
139 #define WX_TDM_VF_TE(_i) (0x18004 + ((_i) * 4))
140 #define WX_TDM_MAC_AS(_i) (0x18060 + ((_i) * 4))
141 #define WX_TDM_VLAN_AS(_i) (0x18070 + ((_i) * 4))
142 #define WX_TDM_VFTE_CLR(_i) (0x180A0 + ((_i) * 4))
143
144 /* TDM CTL BIT */
145 #define WX_TDM_CTL_TE BIT(0) /* Transmit Enable */
146 #define WX_TDM_PB_THRE(_i) (0x18020 + ((_i) * 4))
147 #define WX_TDM_RP_IDX 0x1820C
148 #define WX_TDM_PKT_CNT 0x18308
149 #define WX_TDM_BYTE_CNT_LSB 0x1830C
150 #define WX_TDM_OS2BMC_CNT 0x18314
151 #define WX_TDM_RP_RATE 0x18404
152
153 /***************************** RDB registers *********************************/
154 /* receive packet buffer */
155 #define WX_RDB_PB_CTL 0x19000
156 #define WX_RDB_PB_CTL_RXEN BIT(31) /* Enable Receiver */
157 #define WX_RDB_PB_CTL_DISABLED BIT(0)
158 #define WX_RDB_PB_SZ(_i) (0x19020 + ((_i) * 4))
159 #define WX_RDB_PB_SZ_SHIFT 10
160 /* statistic */
161 #define WX_RDB_PFCMACDAL 0x19210
162 #define WX_RDB_PFCMACDAH 0x19214
163 #define WX_RDB_LXOFFTXC 0x19218
164 #define WX_RDB_LXONTXC 0x1921C
165 /* Flow Control Registers */
166 #define WX_RDB_RFCV 0x19200
167 #define WX_RDB_RFCL 0x19220
168 #define WX_RDB_RFCL_XONE BIT(31)
169 #define WX_RDB_RFCH 0x19260
170 #define WX_RDB_RFCH_XOFFE BIT(31)
171 #define WX_RDB_RFCRT 0x192A0
172 #define WX_RDB_RFCC 0x192A4
173 #define WX_RDB_RFCC_RFCE_802_3X BIT(3)
174 /* ring assignment */
175 #define WX_RDB_PL_CFG(_i) (0x19300 + ((_i) * 4))
176 #define WX_RDB_PL_CFG_L4HDR BIT(1)
177 #define WX_RDB_PL_CFG_L3HDR BIT(2)
178 #define WX_RDB_PL_CFG_L2HDR BIT(3)
179 #define WX_RDB_PL_CFG_TUN_TUNHDR BIT(4)
180 #define WX_RDB_PL_CFG_TUN_OUTL2HDR BIT(5)
181 #define WX_RDB_PL_CFG_RSS_EN BIT(24)
182 #define WX_RDB_PL_CFG_RSS_MASK GENMASK(23, 16)
183 #define WX_RDB_RSSTBL(_i) (0x19400 + ((_i) * 4))
184 #define WX_RDB_RSSRK(_i) (0x19480 + ((_i) * 4))
185 #define WX_RDB_RA_CTL 0x194F4
186 #define WX_RDB_RA_CTL_MULTI_RSS BIT(0)
187 #define WX_RDB_RA_CTL_RSS_EN BIT(2) /* RSS Enable */
188 #define WX_RDB_RA_CTL_RSS_IPV4_TCP BIT(16)
189 #define WX_RDB_RA_CTL_RSS_IPV4 BIT(17)
190 #define WX_RDB_RA_CTL_RSS_IPV6 BIT(20)
191 #define WX_RDB_RA_CTL_RSS_IPV6_TCP BIT(21)
192 #define WX_RDB_RA_CTL_RSS_IPV4_UDP BIT(22)
193 #define WX_RDB_RA_CTL_RSS_IPV6_UDP BIT(23)
194 #define WX_RDB_RA_CTL_RSS_MASK GENMASK(23, 16)
195 #define WX_RDB_FDIR_MATCH 0x19558
196 #define WX_RDB_FDIR_MISS 0x1955C
197 /* VM RSS */
198 #define WX_RDB_VMRSSRK(_i, _p) (0x1A000 + ((_i) * 4) + ((_p) * 0x40))
199 #define WX_RDB_VMRSSTBL(_i, _p) (0x1B000 + ((_i) * 4) + ((_p) * 0x40))
200
201 /******************************* PSR Registers *******************************/
202 /* psr control */
203 #define WX_PSR_CTL 0x15000
204 #define WX_PSR_VM_CTL 0x151B0
205 /* Header split receive */
206 #define WX_PSR_CTL_SW_EN BIT(18)
207 #define WX_PSR_CTL_RSC_ACK BIT(17)
208 #define WX_PSR_CTL_RSC_DIS BIT(16)
209 #define WX_PSR_CTL_PCSD BIT(13)
210 #define WX_PSR_CTL_IPPCSE BIT(12)
211 #define WX_PSR_CTL_BAM BIT(10)
212 #define WX_PSR_CTL_UPE BIT(9)
213 #define WX_PSR_CTL_MPE BIT(8)
214 #define WX_PSR_CTL_MFE BIT(7)
215 #define WX_PSR_CTL_MO_SHIFT 5
216 #define WX_PSR_CTL_MO (0x3 << WX_PSR_CTL_MO_SHIFT)
217 #define WX_PSR_CTL_TPE BIT(4)
218 #define WX_PSR_MAX_SZ 0x15020
219 #define WX_PSR_VLAN_CTL 0x15088
220 #define WX_PSR_VLAN_CTL_CFIEN BIT(29) /* bit 29 */
221 #define WX_PSR_VLAN_CTL_VFE BIT(30) /* bit 30 */
222 /* EType Queue Filter */
223 #define WX_PSR_ETYPE_SWC(_i) (0x15128 + ((_i) * 4))
224 #define WX_PSR_ETYPE_SWC_FILTER_1588 3
225 #define WX_PSR_ETYPE_SWC_FILTER_EN BIT(31)
226 #define WX_PSR_ETYPE_SWC_1588 BIT(30)
227 /* 1588 */
228 #define WX_PSR_1588_MSG 0x15120
229 #define WX_PSR_1588_MSG_V1_SYNC FIELD_PREP(GENMASK(7, 0), 0)
230 #define WX_PSR_1588_MSG_V1_DELAY_REQ FIELD_PREP(GENMASK(7, 0), 1)
231 #define WX_PSR_1588_STMPL 0x151E8
232 #define WX_PSR_1588_STMPH 0x151A4
233 #define WX_PSR_1588_CTL 0x15188
234 #define WX_PSR_1588_CTL_ENABLED BIT(4)
235 #define WX_PSR_1588_CTL_TYPE_MASK GENMASK(3, 1)
236 #define WX_PSR_1588_CTL_TYPE_L4_V1 FIELD_PREP(GENMASK(3, 1), 1)
237 #define WX_PSR_1588_CTL_TYPE_EVENT_V2 FIELD_PREP(GENMASK(3, 1), 5)
238 #define WX_PSR_1588_CTL_VALID BIT(0)
239 /* mcasst/ucast overflow tbl */
240 #define WX_PSR_MC_TBL(_i) (0x15200 + ((_i) * 4))
241 #define WX_PSR_MC_TBL_REG(_i) FIELD_GET(GENMASK(11, 5), (_i))
242 #define WX_PSR_MC_TBL_BIT(_i) FIELD_GET(GENMASK(4, 0), (_i))
243 #define WX_PSR_UC_TBL(_i) (0x15400 + ((_i) * 4))
244 #define WX_PSR_VM_CTL_REPLEN BIT(30) /* replication enabled */
245 #define WX_PSR_VM_CTL_POOL_MASK GENMASK(12, 7)
246
247 /* VM L2 contorl */
248 #define WX_PSR_VM_L2CTL(_i) (0x15600 + ((_i) * 4))
249 #define WX_PSR_VM_L2CTL_UPE BIT(4) /* unicast promiscuous */
250 #define WX_PSR_VM_L2CTL_VACC BIT(6) /* accept nomatched vlan */
251 #define WX_PSR_VM_L2CTL_VPE BIT(7) /* vlan promiscuous mode */
252 #define WX_PSR_VM_L2CTL_AUPE BIT(8) /* accept untagged packets */
253 #define WX_PSR_VM_L2CTL_ROMPE BIT(9) /* accept packets in MTA tbl */
254 #define WX_PSR_VM_L2CTL_ROPE BIT(10) /* accept packets in UC tbl */
255 #define WX_PSR_VM_L2CTL_BAM BIT(11) /* accept broadcast packets */
256 #define WX_PSR_VM_L2CTL_MPE BIT(12) /* multicast promiscuous */
257
258 /* Management */
259 #define WX_PSR_MNG_FLEX_SEL 0x1582C
260 #define WX_PSR_MNG_FLEX_DW_L(_i) (0x15A00 + ((_i) * 16))
261 #define WX_PSR_MNG_FLEX_DW_H(_i) (0x15A04 + ((_i) * 16))
262 #define WX_PSR_MNG_FLEX_MSK(_i) (0x15A08 + ((_i) * 16))
263 #define WX_PSR_LAN_FLEX_SEL 0x15B8C
264 #define WX_PSR_LAN_FLEX_DW_L(_i) (0x15C00 + ((_i) * 16))
265 #define WX_PSR_LAN_FLEX_DW_H(_i) (0x15C04 + ((_i) * 16))
266 #define WX_PSR_LAN_FLEX_MSK(_i) (0x15C08 + ((_i) * 16))
267
268 #define WX_PSR_WKUP_CTL 0x15B80
269 /* Wake Up Filter Control Bit */
270 #define WX_PSR_WKUP_CTL_MAG BIT(1) /* Magic Packet Wakeup Enable */
271
272 /* vlan tbl */
273 #define WX_PSR_VLAN_TBL(_i) (0x16000 + ((_i) * 4))
274
275 /* mac switcher */
276 #define WX_PSR_MAC_SWC_AD_L 0x16200
277 #define WX_PSR_MAC_SWC_AD_H 0x16204
278 #define WX_PSR_MAC_SWC_AD_H_AD(v) FIELD_PREP(U16_MAX, v)
279 #define WX_PSR_MAC_SWC_AD_H_ADTYPE(v) FIELD_PREP(BIT(30), v)
280 #define WX_PSR_MAC_SWC_AD_H_AV BIT(31)
281 #define WX_PSR_MAC_SWC_VM_L 0x16208
282 #define WX_PSR_MAC_SWC_VM_H 0x1620C
283 #define WX_PSR_MAC_SWC_IDX 0x16210
284 #define WX_CLEAR_VMDQ_ALL 0xFFFFFFFFU
285
286 /* vlan switch */
287 #define WX_PSR_VLAN_SWC 0x16220
288 #define WX_PSR_VLAN_SWC_VM_L 0x16224
289 #define WX_PSR_VLAN_SWC_VM_H 0x16228
290 #define WX_PSR_VLAN_SWC_VM(_i) (0x16224 + ((_i) * 4))
291 #define WX_PSR_VLAN_SWC_IDX 0x16230 /* 64 vlan entries */
292 /* VLAN pool filtering masks */
293 #define WX_PSR_VLAN_SWC_VIEN BIT(31) /* filter is valid */
294 #define WX_PSR_VLAN_SWC_ENTRIES 64
295 #define WX_PSR_VLAN_SWC_VLANID_MASK GENMASK(11, 0)
296
297 /********************************* RSEC **************************************/
298 /* general rsec */
299 #define WX_RSC_CTL 0x17000
300 #define WX_RSC_CTL_SAVE_MAC_ERR BIT(6)
301 #define WX_RSC_CTL_CRC_STRIP BIT(2)
302 #define WX_RSC_CTL_RX_DIS BIT(1)
303 #define WX_RSC_ST 0x17004
304 #define WX_RSC_ST_RSEC_RDY BIT(0)
305
306 /*********************** Transmit DMA registers **************************/
307 /* transmit global control */
308 #define WX_TDM_ETYPE_AS(_i) (0x18058 + ((_i) * 4))
309 #define WX_TDM_VLAN_INS(_i) (0x18100 + ((_i) * 4))
310 /* Per VF Port VLAN insertion rules */
311 #define WX_TDM_VLAN_INS_VLANA_DEFAULT BIT(30) /* Always use default VLAN*/
312
313 /****************************** TDB ******************************************/
314 #define WX_TDB_PB_SZ(_i) (0x1CC00 + ((_i) * 4))
315 #define WX_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
316
317 /****************************** TSEC *****************************************/
318 /* Security Control Registers */
319 #define WX_TSC_CTL 0x1D000
320 #define WX_TSC_CTL_TX_DIS BIT(1)
321 #define WX_TSC_CTL_TSEC_DIS BIT(0)
322 #define WX_TSC_ST 0x1D004
323 #define WX_TSC_ST_SECTX_RDY BIT(0)
324 #define WX_TSC_BUF_AE 0x1D00C
325 #define WX_TSC_BUF_AE_THR GENMASK(9, 0)
326 /* 1588 */
327 #define WX_TSC_1588_CTL 0x11F00
328 #define WX_TSC_1588_CTL_ENABLED BIT(4)
329 #define WX_TSC_1588_CTL_VALID BIT(0)
330 #define WX_TSC_1588_STMPL 0x11F04
331 #define WX_TSC_1588_STMPH 0x11F08
332 #define WX_TSC_1588_SYSTIML 0x11F0C
333 #define WX_TSC_1588_SYSTIMH 0x11F10
334 #define WX_TSC_1588_INC 0x11F14
335 #define WX_TSC_1588_INT_ST 0x11F20
336 #define WX_TSC_1588_INT_ST_TT1 BIT(5)
337 #define WX_TSC_1588_INT_EN 0x11F24
338 #define WX_TSC_1588_INT_EN_TT1 BIT(5)
339 #define WX_TSC_1588_AUX_CTL 0x11F28
340 #define WX_TSC_1588_AUX_CTL_EN_TS0 BIT(8)
341 #define WX_TSC_1588_AUX_CTL_EN_TT1 BIT(2)
342 #define WX_TSC_1588_AUX_CTL_PLSG BIT(1)
343 #define WX_TSC_1588_AUX_CTL_EN_TT0 BIT(0)
344 #define WX_TSC_1588_TRGT_L(i) (0x11F2C + ((i) * 8)) /* [0,1] */
345 #define WX_TSC_1588_TRGT_H(i) (0x11F30 + ((i) * 8)) /* [0,1] */
346 #define WX_TSC_1588_SDP(i) (0x11F5C + ((i) * 4)) /* [0,3] */
347 #define WX_TSC_1588_SDP_OUT_LEVEL_H FIELD_PREP(BIT(4), 0)
348 #define WX_TSC_1588_SDP_OUT_LEVEL_L FIELD_PREP(BIT(4), 1)
349 #define WX_TSC_1588_SDP_FUN_SEL_MASK GENMASK(2, 0)
350 #define WX_TSC_1588_SDP_FUN_SEL_TT0 FIELD_PREP(WX_TSC_1588_SDP_FUN_SEL_MASK, 1)
351 #define WX_TSC_1588_SDP_FUN_SEL_TS0 FIELD_PREP(WX_TSC_1588_SDP_FUN_SEL_MASK, 5)
352
353 /************************************** MNG ********************************/
354 #define WX_MNG_SWFW_SYNC 0x1E008
355 #define WX_MNG_SWFW_SYNC_SW_MB BIT(2)
356 #define WX_MNG_SWFW_SYNC_SW_FLASH BIT(3)
357 #define WX_MNG_MBOX 0x1E100
358 #define WX_MNG_MBOX_CTL 0x1E044
359 #define WX_MNG_MBOX_CTL_SWRDY BIT(0)
360 #define WX_MNG_MBOX_CTL_FWRDY BIT(2)
361 #define WX_MNG_BMC2OS_CNT 0x1E090
362 #define WX_MNG_OS2BMC_CNT 0x1E094
363 #define WX_SW2FW_MBOX_CMD 0x1E0A0
364 #define WX_SW2FW_MBOX_CMD_VLD BIT(31)
365 #define WX_SW2FW_MBOX 0x1E200
366 #define WX_FW2SW_MBOX 0x1E300
367
368 /************************************* ETH MAC *****************************/
369 #define WX_MAC_TX_CFG 0x11000
370 #define WX_MAC_TX_CFG_TE BIT(0)
371 #define WX_MAC_TX_CFG_SPEED_MASK GENMASK(30, 29)
372 #define WX_MAC_TX_CFG_SPEED_10G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 0)
373 #define WX_MAC_TX_CFG_SPEED_1G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 3)
374 #define WX_MAC_RX_CFG 0x11004
375 #define WX_MAC_RX_CFG_RE BIT(0)
376 #define WX_MAC_RX_CFG_JE BIT(8)
377 #define WX_MAC_PKT_FLT 0x11008
378 #define WX_MAC_PKT_FLT_PR BIT(0) /* promiscuous mode */
379 #define WX_MAC_WDG_TIMEOUT 0x1100C
380 #define WX_MAC_RX_FLOW_CTRL 0x11090
381 #define WX_MAC_RX_FLOW_CTRL_RFE BIT(0) /* receive fc enable */
382
383 #define WX_MAC_WDG_TIMEOUT_WTO_MASK GENMASK(3, 0)
384 #define WX_MAC_WDG_TIMEOUT_WTO_DELTA 2
385 /* MDIO Registers */
386 #define WX_MSCA 0x11200
387 #define WX_MSCA_RA(v) FIELD_PREP(U16_MAX, v)
388 #define WX_MSCA_PA(v) FIELD_PREP(GENMASK(20, 16), v)
389 #define WX_MSCA_DA(v) FIELD_PREP(GENMASK(25, 21), v)
390 #define WX_MSCC 0x11204
391 #define WX_MSCC_CMD(v) FIELD_PREP(GENMASK(17, 16), v)
392
393 enum WX_MSCA_CMD_value {
394 WX_MSCA_CMD_RSV = 0,
395 WX_MSCA_CMD_WRITE,
396 WX_MSCA_CMD_POST_READ,
397 WX_MSCA_CMD_READ,
398 };
399
400 #define WX_MSCC_SADDR BIT(18)
401 #define WX_MSCC_BUSY BIT(22)
402 #define WX_MDIO_CLK(v) FIELD_PREP(GENMASK(21, 19), v)
403 #define WX_MDIO_CLAUSE_SELECT 0x11220
404 #define WX_MMC_CONTROL 0x11800
405 #define WX_MMC_CONTROL_RSTONRD BIT(2) /* reset on read */
406
407 /********************************* BAR registers ***************************/
408 /* Interrupt Registers */
409 #define WX_BME_CTL 0x12020
410 #define WX_PX_MISC_IC 0x100
411 #define WX_PX_MISC_ICS 0x104
412 #define WX_PX_MISC_IEN 0x108
413 #define WX_PX_INTA 0x110
414 #define WX_PX_GPIE 0x118
415 #define WX_PX_GPIE_MODEL BIT(0)
416 #define WX_PX_IC(_i) (0x120 + (_i) * 4)
417 #define WX_PX_IMS(_i) (0x140 + (_i) * 4)
418 #define WX_PX_IMC(_i) (0x150 + (_i) * 4)
419 #define WX_PX_ISB_ADDR_L 0x160
420 #define WX_PX_ISB_ADDR_H 0x164
421 #define WX_PX_TRANSACTION_PENDING 0x168
422 #define WX_PX_ITRSEL 0x180
423 #define WX_PX_ITR(_i) (0x200 + (_i) * 4)
424 #define WX_PX_ITR_CNT_WDIS BIT(31)
425 #define WX_PX_MISC_IVAR 0x4FC
426 #define WX_PX_IVAR(_i) (0x500 + (_i) * 4)
427
428 #define WX_PX_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
429 #define WX_7K_ITR 595
430 #define WX_12K_ITR 336
431 #define WX_20K_ITR 200
432 #define WX_MIN_RSC_ITR 24
433 #define WX_SP_MAX_EITR 0x00000FF8U
434 #define WX_AML_MAX_EITR 0x00000FFFU
435 #define WX_EM_MAX_EITR 0x00007FFCU
436
437 /* transmit DMA Registers */
438 #define WX_PX_TR_BAL(_i) (0x03000 + ((_i) * 0x40))
439 #define WX_PX_TR_BAH(_i) (0x03004 + ((_i) * 0x40))
440 #define WX_PX_TR_WP(_i) (0x03008 + ((_i) * 0x40))
441 #define WX_PX_TR_RP(_i) (0x0300C + ((_i) * 0x40))
442 #define WX_PX_TR_CFG(_i) (0x03010 + ((_i) * 0x40))
443 #define WX_PX_TR_HEAD_ADDRL(_i) (0x03028 + ((_i) * 0x40))
444 #define WX_PX_TR_HEAD_ADDRH(_i) (0x0302C + ((_i) * 0x40))
445 /* Transmit Config masks */
446 #define WX_PX_TR_CFG_ENABLE BIT(0) /* Ena specific Tx Queue */
447 #define WX_PX_TR_CFG_TR_SIZE_SHIFT 1 /* tx desc number per ring */
448 #define WX_PX_TR_CFG_SWFLSH BIT(26) /* Tx Desc. wr-bk flushing */
449 #define WX_PX_TR_CFG_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
450 #define WX_PX_TR_CFG_THRE_SHIFT 8
451 #define WX_PX_TR_CFG_HEAD_WB BIT(27)
452
453 /* Receive DMA Registers */
454 #define WX_PX_RR_BAL(_i) (0x01000 + ((_i) * 0x40))
455 #define WX_PX_RR_BAH(_i) (0x01004 + ((_i) * 0x40))
456 #define WX_PX_RR_WP(_i) (0x01008 + ((_i) * 0x40))
457 #define WX_PX_RR_RP(_i) (0x0100C + ((_i) * 0x40))
458 #define WX_PX_RR_CFG(_i) (0x01010 + ((_i) * 0x40))
459 #define WX_PX_MPRC(_i) (0x01020 + ((_i) * 0x40))
460 /* PX_RR_CFG bit definitions */
461 #define WX_PX_RR_CFG_VLAN BIT(31)
462 #define WX_PX_RR_CFG_DROP_EN BIT(30)
463 #define WX_PX_RR_CFG_RSC BIT(29)
464 #define WX_PX_RR_CFG_SPLIT_MODE BIT(26)
465 #define WX_PX_RR_CFG_MAX_RSCBUF_16 FIELD_PREP(GENMASK(24, 23), 3)
466 #define WX_PX_RR_CFG_DESC_MERGE BIT(19)
467 #define WX_PX_RR_CFG_RR_THER_SHIFT 16
468 #define WX_PX_RR_CFG_RR_HDR_SZ GENMASK(15, 12)
469 #define WX_PX_RR_CFG_RR_BUF_SZ GENMASK(11, 8)
470 #define WX_PX_RR_CFG_BHDRSIZE_SHIFT 6 /* 64byte resolution (>> 6)
471 * + at bit 8 offset (<< 12)
472 * = (<< 6)
473 */
474 #define WX_PX_RR_CFG_BSIZEPKT_SHIFT 2 /* so many KBs */
475 #define WX_PX_RR_CFG_RR_SIZE_SHIFT 1
476 #define WX_PX_RR_CFG_RR_EN BIT(0)
477
478 /* Number of 80 microseconds we wait for PCI Express master disable */
479 #define WX_PCI_MASTER_DISABLE_TIMEOUT 80000
480
481 #define WX_RSS_64Q_MASK 0x3F
482 #define WX_RSS_8Q_MASK 0x7
483 #define WX_RSS_4Q_MASK 0x3
484 #define WX_RSS_2Q_MASK 0x1
485 #define WX_RSS_DISABLED_MASK 0x0
486
487 #define WX_VMDQ_4Q_MASK 0x7C
488 #define WX_VMDQ_2Q_MASK 0x7E
489 #define WX_VMDQ_1Q_MASK 0x7F
490
491 /****************** Manageablility Host Interface defines ********************/
492 #define WX_HI_MAX_BLOCK_BYTE_LENGTH 256 /* Num of bytes in range */
493 #define WX_HI_COMMAND_TIMEOUT 1000 /* Process HI command limit */
494 #define WX_HIC_HDR_INDEX_MAX 255
495
496 #define FW_READ_SHADOW_RAM_CMD 0x31
497 #define FW_READ_SHADOW_RAM_LEN 0x6
498 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */
499 #define FW_NVM_DATA_OFFSET 3
500 #define FW_MAX_READ_BUFFER_SIZE 244
501 #define FW_RESET_CMD 0xDF
502 #define FW_RESET_LEN 0x2
503 #define FW_CEM_HDR_LEN 0x4
504 #define FW_CEM_CMD_RESERVED 0X0
505 #define FW_CEM_MAX_RETRIES 3
506 #define FW_CEM_RESP_STATUS_SUCCESS 0x1
507 #define FW_PPS_SET_CMD 0xF6
508 #define FW_PPS_SET_LEN 0x14
509
510 #define WX_SW_REGION_PTR 0x1C
511
512 #define WX_MAC_STATE_DEFAULT 0x1
513 #define WX_MAC_STATE_MODIFIED 0x2
514 #define WX_MAC_STATE_IN_USE 0x4
515
516 /* BitTimes (BT) conversion */
517 #define WX_BT2KB(BT) (((BT) + (8 * 1024 - 1)) / (8 * 1024))
518 #define WX_B2BT(BT) ((BT) * 8)
519
520 /* Calculate Delay to respond to PFC */
521 #define WX_PFC_D 672
522 /* Calculate Cable Delay */
523 #define WX_CABLE_DC 5556 /* Delay Copper */
524 /* Calculate Delay incurred from higher layer */
525 #define WX_HD 6144
526
527 /* Calculate Interface Delay */
528 #define WX_PHY_D 12800
529 #define WX_MAC_D 4096
530 #define WX_XAUI_D (2 * 1024)
531 #define WX_ID (WX_MAC_D + WX_XAUI_D + WX_PHY_D)
532 /* Calculate PCI Bus delay for low thresholds */
533 #define WX_PCI_DELAY 10000
534
535 /* Calculate delay value in bit times */
536 #define WX_DV(_max_frame_link, _max_frame_tc) \
537 ((36 * (WX_B2BT(_max_frame_link) + WX_PFC_D + \
538 (2 * WX_CABLE_DC) + (2 * WX_ID) + WX_HD) / 25 + 1) + \
539 2 * WX_B2BT(_max_frame_tc))
540
541 /* Calculate low threshold delay values */
542 #define WX_LOW_DV(_max_frame_tc) \
543 (2 * (2 * WX_B2BT(_max_frame_tc) + (36 * WX_PCI_DELAY / 25) + 1))
544
545 /* flow control */
546 #define WX_DEFAULT_FCPAUSE 0xFFFF
547
548 #define WX_MAX_RXD 8192
549 #define WX_MAX_TXD 8192
550 #define WX_MIN_RXD 128
551 #define WX_MIN_TXD 128
552
553 /* Number of Transmit and Receive Descriptors must be a multiple of 128 */
554 #define WX_REQ_RX_DESCRIPTOR_MULTIPLE 128
555 #define WX_REQ_TX_DESCRIPTOR_MULTIPLE 128
556
557 #define WX_MAX_JUMBO_FRAME_SIZE 9432 /* max payload 9414 */
558 #define VMDQ_P(p) ((p) + wx->ring_feature[RING_F_VMDQ].offset)
559
560 /* Supported Rx Buffer Sizes */
561 #define WX_RXBUFFER_256 256 /* Used for skb receive header */
562 #define WX_RXBUFFER_2K 2048
563 #define WX_RXBUFFER_3K 3072
564 #define WX_MAX_RXBUFFER 16384 /* largest size for single descriptor */
565
566 #define WX_RX_BUFFER_WRITE 16 /* Must be power of 2 */
567
568 #define WX_MAX_DATA_PER_TXD BIT(14)
569 /* Tx Descriptors needed, worst case */
570 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), WX_MAX_DATA_PER_TXD)
571 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
572
573 /******************* Receive Descriptor bit definitions **********************/
574 #define WX_RXD_STAT_DD BIT(0) /* Done */
575 #define WX_RXD_STAT_EOP BIT(1) /* End of Packet */
576 #define WX_RXD_STAT_VP BIT(5) /* IEEE VLAN Pkt */
577 #define WX_RXD_STAT_L4CS BIT(7) /* L4 xsum calculated */
578 #define WX_RXD_STAT_IPCS BIT(8) /* IP xsum calculated */
579 #define WX_RXD_STAT_OUTERIPCS BIT(10) /* Cloud IP xsum calculated*/
580 #define WX_RXD_STAT_IPV6EX BIT(12) /* IPv6 Dest Header */
581 #define WX_RXD_STAT_TS BIT(14) /* IEEE1588 Time Stamp */
582
583 #define WX_RXD_ERR_OUTERIPER BIT(26) /* CRC IP Header error */
584 #define WX_RXD_ERR_RXE BIT(29) /* Any MAC Error */
585 #define WX_RXD_ERR_TCPE BIT(30) /* TCP/UDP Checksum Error */
586 #define WX_RXD_ERR_IPE BIT(31) /* IP Checksum Error */
587
588 /* RSS Hash results */
589 #define WX_RXD_RSSTYPE_MASK GENMASK(3, 0)
590 #define WX_RXD_RSSTYPE_IPV4_TCP 0x00000001U
591 #define WX_RXD_RSSTYPE_IPV6_TCP 0x00000003U
592 #define WX_RXD_RSSTYPE_IPV4_SCTP 0x00000004U
593 #define WX_RXD_RSSTYPE_IPV6_SCTP 0x00000006U
594 #define WX_RXD_RSSTYPE_IPV4_UDP 0x00000007U
595 #define WX_RXD_RSSTYPE_IPV6_UDP 0x00000008U
596
597 #define WX_RSS_L4_TYPES_MASK \
598 ((1ul << WX_RXD_RSSTYPE_IPV4_TCP) | \
599 (1ul << WX_RXD_RSSTYPE_IPV4_UDP) | \
600 (1ul << WX_RXD_RSSTYPE_IPV4_SCTP) | \
601 (1ul << WX_RXD_RSSTYPE_IPV6_TCP) | \
602 (1ul << WX_RXD_RSSTYPE_IPV6_UDP) | \
603 (1ul << WX_RXD_RSSTYPE_IPV6_SCTP))
604 /* TUN */
605 #define WX_PTYPE_TUN_IPV4 0x80
606 #define WX_PTYPE_TUN_IPV6 0xC0
607
608 /* PKT for TUN */
609 #define WX_PTYPE_PKT_IPIP 0x00 /* IP+IP */
610 #define WX_PTYPE_PKT_IG 0x10 /* IP+GRE */
611 #define WX_PTYPE_PKT_IGM 0x20 /* IP+GRE+MAC */
612 #define WX_PTYPE_PKT_IGMV 0x30 /* IP+GRE+MAC+VLAN */
613 /* PKT for !TUN */
614 #define WX_PTYPE_PKT_MAC 0x10
615 #define WX_PTYPE_PKT_IP 0x20
616
617 /* TYP for PKT=mac */
618 #define WX_PTYPE_TYP_MAC 0x01
619 /* TYP for PKT=ip */
620 #define WX_PTYPE_PKT_IPV6 0x08
621 #define WX_PTYPE_TYP_IPFRAG 0x01
622 #define WX_PTYPE_TYP_IP 0x02
623 #define WX_PTYPE_TYP_UDP 0x03
624 #define WX_PTYPE_TYP_TCP 0x04
625 #define WX_PTYPE_TYP_SCTP 0x05
626
627 /* Packet type non-ip values */
628 enum wx_l2_ptypes {
629 WX_PTYPE_L2_ABORTED = (WX_PTYPE_PKT_MAC),
630 WX_PTYPE_L2_MAC = (WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC),
631
632 WX_PTYPE_L2_IPV4_FRAG = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_IPFRAG),
633 WX_PTYPE_L2_IPV4 = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_IP),
634 WX_PTYPE_L2_IPV4_UDP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_UDP),
635 WX_PTYPE_L2_IPV4_TCP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_TCP),
636 WX_PTYPE_L2_IPV4_SCTP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_SCTP),
637 WX_PTYPE_L2_IPV6_FRAG = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
638 WX_PTYPE_TYP_IPFRAG),
639 WX_PTYPE_L2_IPV6 = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
640 WX_PTYPE_TYP_IP),
641 WX_PTYPE_L2_IPV6_UDP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
642 WX_PTYPE_TYP_UDP),
643 WX_PTYPE_L2_IPV6_TCP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
644 WX_PTYPE_TYP_TCP),
645 WX_PTYPE_L2_IPV6_SCTP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
646 WX_PTYPE_TYP_SCTP),
647
648 WX_PTYPE_L2_TUN4_MAC = (WX_PTYPE_TUN_IPV4 | WX_PTYPE_PKT_IGM),
649 WX_PTYPE_L2_TUN6_MAC = (WX_PTYPE_TUN_IPV6 | WX_PTYPE_PKT_IGM),
650 };
651
652 #define WX_PTYPE_PKT(_pt) ((_pt) & 0x30)
653 #define WX_PTYPE_TYPL4(_pt) ((_pt) & 0x07)
654
655 #define WX_RXD_PKTTYPE(_rxd) \
656 ((le32_to_cpu((_rxd)->wb.lower.lo_dword.data) >> 9) & 0xFF)
657
658 #define WX_RXD_RSCCNT_MASK GENMASK(20, 17)
659 #define WX_RXD_RSCCNT_SHIFT 17
660 #define WX_RXD_NEXTP_MASK GENMASK(19, 4)
661 #define WX_RXD_NEXTP_SHIFT 4
662
663 /*********************** Transmit Descriptor Config Masks ****************/
664 #define WX_TXD_STAT_DD BIT(0) /* Descriptor Done */
665 #define WX_TXD_DTYP_DATA 0 /* Adv Data Descriptor */
666 #define WX_TXD_PAYLEN_SHIFT 13 /* Desc PAYLEN shift */
667 #define WX_TXD_EOP BIT(24) /* End of Packet */
668 #define WX_TXD_IFCS BIT(25) /* Insert FCS */
669 #define WX_TXD_RS BIT(27) /* Report Status */
670
671 /*********************** Adv Transmit Descriptor Config Masks ****************/
672 #define WX_TXD_MAC_TSTAMP BIT(19) /* IEEE1588 time stamp */
673 #define WX_TXD_DTYP_CTXT BIT(20) /* Adv Context Desc */
674 #define WX_TXD_LINKSEC BIT(26) /* enable linksec */
675 #define WX_TXD_VLE BIT(30) /* VLAN pkt enable */
676 #define WX_TXD_TSE BIT(31) /* TCP Seg enable */
677 #define WX_TXD_CC BIT(7) /* Check Context */
678 #define WX_TXD_IPSEC BIT(8) /* enable ipsec esp */
679 #define WX_TXD_L4CS BIT(9)
680 #define WX_TXD_IIPCS BIT(10)
681 #define WX_TXD_EIPCS BIT(11)
682 #define WX_TXD_PAYLEN_SHIFT 13 /* Adv desc PAYLEN shift */
683 #define WX_TXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
684 #define WX_TXD_TAG_TPID_SEL_SHIFT 11
685
686 #define WX_TXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
687 #define WX_TXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
688
689 #define WX_TXD_OUTER_IPLEN_SHIFT 12 /* Adv ctxt OUTERIPLEN shift */
690 #define WX_TXD_TUNNEL_LEN_SHIFT 21 /* Adv ctxt TUNNELLEN shift */
691 #define WX_TXD_TUNNEL_TYPE_SHIFT 11 /* Adv Tx Desc Tunnel Type shift */
692 #define WX_TXD_TUNNEL_UDP FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 0)
693 #define WX_TXD_TUNNEL_GRE FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 1)
694
695 enum wx_tx_flags {
696 /* cmd_type flags */
697 WX_TX_FLAGS_HW_VLAN = 0x01,
698 WX_TX_FLAGS_TSO = 0x02,
699 WX_TX_FLAGS_TSTAMP = 0x04,
700
701 /* olinfo flags */
702 WX_TX_FLAGS_CC = 0x08,
703 WX_TX_FLAGS_IPV4 = 0x10,
704 WX_TX_FLAGS_CSUM = 0x20,
705 WX_TX_FLAGS_OUTER_IPV4 = 0x100,
706 WX_TX_FLAGS_LINKSEC = 0x200,
707 WX_TX_FLAGS_IPSEC = 0x400,
708
709 /* software defined flags */
710 WX_TX_FLAGS_SW_VLAN = 0x40,
711 };
712
713 /* VLAN info */
714 #define WX_TX_FLAGS_VLAN_MASK GENMASK(31, 16)
715 #define WX_TX_FLAGS_VLAN_SHIFT 16
716
717 /* wx_dec_ptype.mac: outer mac */
718 enum wx_dec_ptype_mac {
719 WX_DEC_PTYPE_MAC_IP = 0,
720 WX_DEC_PTYPE_MAC_L2 = 2,
721 WX_DEC_PTYPE_MAC_FCOE = 3,
722 };
723
724 /* wx_dec_ptype.[e]ip: outer&encaped ip */
725 #define WX_DEC_PTYPE_IP_FRAG 0x4
726 enum wx_dec_ptype_ip {
727 WX_DEC_PTYPE_IP_NONE = 0,
728 WX_DEC_PTYPE_IP_IPV4 = 1,
729 WX_DEC_PTYPE_IP_IPV6 = 2,
730 WX_DEC_PTYPE_IP_FGV4 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV4,
731 WX_DEC_PTYPE_IP_FGV6 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV6,
732 };
733
734 /* wx_dec_ptype.etype: encaped type */
735 enum wx_dec_ptype_etype {
736 WX_DEC_PTYPE_ETYPE_NONE = 0,
737 WX_DEC_PTYPE_ETYPE_IPIP = 1, /* IP+IP */
738 WX_DEC_PTYPE_ETYPE_IG = 2, /* IP+GRE */
739 WX_DEC_PTYPE_ETYPE_IGM = 3, /* IP+GRE+MAC */
740 WX_DEC_PTYPE_ETYPE_IGMV = 4, /* IP+GRE+MAC+VLAN */
741 };
742
743 /* wx_dec_ptype.proto: payload proto */
744 enum wx_dec_ptype_prot {
745 WX_DEC_PTYPE_PROT_NONE = 0,
746 WX_DEC_PTYPE_PROT_UDP = 1,
747 WX_DEC_PTYPE_PROT_TCP = 2,
748 WX_DEC_PTYPE_PROT_SCTP = 3,
749 WX_DEC_PTYPE_PROT_ICMP = 4,
750 WX_DEC_PTYPE_PROT_TS = 5, /* time sync */
751 };
752
753 /* wx_dec_ptype.layer: payload layer */
754 enum wx_dec_ptype_layer {
755 WX_DEC_PTYPE_LAYER_NONE = 0,
756 WX_DEC_PTYPE_LAYER_PAY2 = 1,
757 WX_DEC_PTYPE_LAYER_PAY3 = 2,
758 WX_DEC_PTYPE_LAYER_PAY4 = 3,
759 };
760
761 struct wx_dec_ptype {
762 u32 known:1;
763 u32 mac:2; /* outer mac */
764 u32 ip:3; /* outer ip*/
765 u32 etype:3; /* encaped type */
766 u32 eip:3; /* encaped ip */
767 u32 prot:4; /* payload proto */
768 u32 layer:3; /* payload layer */
769 };
770
771 /* macro to make the table lines short */
772 #define WX_PTT(mac, ip, etype, eip, proto, layer)\
773 {1, \
774 WX_DEC_PTYPE_MAC_##mac, /* mac */\
775 WX_DEC_PTYPE_IP_##ip, /* ip */ \
776 WX_DEC_PTYPE_ETYPE_##etype, /* etype */\
777 WX_DEC_PTYPE_IP_##eip, /* eip */\
778 WX_DEC_PTYPE_PROT_##proto, /* proto */\
779 WX_DEC_PTYPE_LAYER_##layer /* layer */}
780
781 /* Host Interface Command Structures */
782 struct wx_hic_hdr {
783 u8 cmd;
784 u8 buf_len;
785 union {
786 u8 cmd_resv;
787 u8 ret_status;
788 } cmd_or_resp;
789 union {
790 u8 checksum;
791 u8 index;
792 };
793 };
794
795 struct wx_hic_hdr2_req {
796 u8 cmd;
797 u8 buf_lenh;
798 u8 buf_lenl;
799 union {
800 u8 checksum;
801 u8 index;
802 };
803 };
804
805 struct wx_hic_hdr2_rsp {
806 u8 cmd;
807 u8 buf_lenl;
808 u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */
809 union {
810 u8 checksum;
811 u8 index;
812 };
813 };
814
815 union wx_hic_hdr2 {
816 struct wx_hic_hdr2_req req;
817 struct wx_hic_hdr2_rsp rsp;
818 };
819
820 /* These need to be dword aligned */
821 struct wx_hic_read_shadow_ram {
822 union wx_hic_hdr2 hdr;
823 u32 address;
824 u16 length;
825 u16 pad2;
826 u16 data;
827 u16 pad3;
828 };
829
830 struct wx_hic_reset {
831 struct wx_hic_hdr hdr;
832 u16 lan_id;
833 u16 reset_type;
834 };
835
836 struct wx_hic_set_pps {
837 struct wx_hic_hdr hdr;
838 u8 lan_id;
839 u8 enable;
840 u16 pad2;
841 u64 nsec;
842 u64 cycles;
843 };
844
845 /* Bus parameters */
846 struct wx_bus_info {
847 u8 func;
848 u16 device;
849 };
850
851 struct wx_mbx_info {
852 u16 size;
853 u32 mailbox;
854 u32 udelay;
855 u32 timeout;
856 /* lock mbx access */
857 spinlock_t mbx_lock;
858 };
859
860 struct wx_thermal_sensor_data {
861 s16 temp;
862 s16 alarm_thresh;
863 s16 dalarm_thresh;
864 };
865
866 enum wx_mac_type {
867 wx_mac_unknown = 0,
868 wx_mac_sp,
869 wx_mac_em,
870 wx_mac_aml,
871 wx_mac_aml40,
872 };
873
874 enum wx_media_type {
875 wx_media_unknown = 0,
876 wx_media_fiber,
877 wx_media_copper,
878 wx_media_backplane
879 };
880
881 enum em_mac_type {
882 em_mac_type_unknown = 0,
883 em_mac_type_mdi,
884 em_mac_type_rgmii
885 };
886
887 struct wx_mac_info {
888 enum wx_mac_type type;
889 bool set_lben;
890 u8 addr[ETH_ALEN];
891 u8 perm_addr[ETH_ALEN];
892 u32 mta_shadow[128];
893 s32 mc_filter_type;
894 u32 mcft_size;
895 u32 vft_shadow[128];
896 u32 vft_size;
897 u32 num_rar_entries;
898 u32 rx_pb_size;
899 u32 tx_pb_size;
900 u32 max_tx_queues;
901 u32 max_rx_queues;
902
903 u16 max_msix_vectors;
904 struct wx_thermal_sensor_data sensor;
905 };
906
907 enum wx_eeprom_type {
908 wx_eeprom_uninitialized = 0,
909 wx_eeprom_spi,
910 wx_flash,
911 wx_eeprom_none /* No NVM support */
912 };
913
914 struct wx_eeprom_info {
915 enum wx_eeprom_type type;
916 u32 semaphore_delay;
917 u16 word_size;
918 u16 sw_region_offset;
919 };
920
921 struct wx_addr_filter_info {
922 u32 num_mc_addrs;
923 u32 mta_in_use;
924 bool user_set_promisc;
925 };
926
927 struct wx_mac_addr {
928 u8 addr[ETH_ALEN];
929 u16 state; /* bitmask */
930 u64 pools;
931 };
932
933 enum wx_reset_type {
934 WX_LAN_RESET = 0,
935 WX_SW_RESET,
936 WX_GLOBAL_RESET
937 };
938
939 struct wx_cb {
940 dma_addr_t dma;
941 u16 append_cnt; /* number of skb's appended */
942 bool dma_released;
943 };
944
945 #define WX_CB(skb) ((struct wx_cb *)(skb)->cb)
946
947 /* Transmit Descriptor */
948 union wx_tx_desc {
949 struct {
950 __le64 buffer_addr; /* Address of descriptor's data buf */
951 __le32 cmd_type_len;
952 __le32 olinfo_status;
953 } read;
954 struct {
955 __le64 rsvd; /* Reserved */
956 __le32 nxtseq_seed;
957 __le32 status;
958 } wb;
959 };
960
961 /* Receive Descriptor */
962 union wx_rx_desc {
963 struct {
964 __le64 pkt_addr; /* Packet buffer address */
965 __le64 hdr_addr; /* Header buffer address */
966 } read;
967 struct {
968 struct {
969 union {
970 __le32 data;
971 struct {
972 __le16 pkt_info; /* RSS, Pkt type */
973 __le16 hdr_info; /* Splithdr, hdrlen */
974 } hs_rss;
975 } lo_dword;
976 union {
977 __le32 rss; /* RSS Hash */
978 struct {
979 __le16 ip_id; /* IP id */
980 __le16 csum; /* Packet Checksum */
981 } csum_ip;
982 } hi_dword;
983 } lower;
984 struct {
985 __le32 status_error; /* ext status/error */
986 __le16 length; /* Packet length */
987 __le16 vlan; /* VLAN tag */
988 } upper;
989 } wb; /* writeback */
990 };
991
992 struct wx_tx_context_desc {
993 __le32 vlan_macip_lens;
994 __le32 seqnum_seed;
995 __le32 type_tucmd_mlhl;
996 __le32 mss_l4len_idx;
997 };
998
999 /* if _flag is in _input, return _result */
1000 #define WX_SET_FLAG(_input, _flag, _result) \
1001 (((_flag) <= (_result)) ? \
1002 ((u32)((_input) & (_flag)) * ((_result) / (_flag))) : \
1003 ((u32)((_input) & (_flag)) / ((_flag) / (_result))))
1004
1005 #define WX_RX_DESC(R, i) \
1006 (&(((union wx_rx_desc *)((R)->desc))[i]))
1007 #define WX_TX_DESC(R, i) \
1008 (&(((union wx_tx_desc *)((R)->desc))[i]))
1009 #define WX_TX_CTXTDESC(R, i) \
1010 (&(((struct wx_tx_context_desc *)((R)->desc))[i]))
1011
1012 /* wrapper around a pointer to a socket buffer,
1013 * so a DMA handle can be stored along with the buffer
1014 */
1015 struct wx_tx_buffer {
1016 union wx_tx_desc *next_to_watch;
1017 unsigned long time_stamp;
1018 struct sk_buff *skb;
1019 unsigned int bytecount;
1020 unsigned short gso_segs;
1021 DEFINE_DMA_UNMAP_ADDR(dma);
1022 DEFINE_DMA_UNMAP_LEN(len);
1023 __be16 protocol;
1024 u32 tx_flags;
1025 u32 next_eop;
1026 };
1027
1028 struct wx_rx_buffer {
1029 struct sk_buff *skb;
1030 dma_addr_t dma;
1031 struct page *page;
1032 unsigned int page_offset;
1033 };
1034
1035 struct wx_queue_stats {
1036 u64 packets;
1037 u64 bytes;
1038 };
1039
1040 struct wx_tx_queue_stats {
1041 u64 restart_queue;
1042 u64 tx_busy;
1043 };
1044
1045 struct wx_rx_queue_stats {
1046 u64 non_eop_descs;
1047 u64 csum_good_cnt;
1048 u64 csum_err;
1049 u64 alloc_rx_buff_failed;
1050 u64 rsc_count;
1051 u64 rsc_flush;
1052 };
1053
1054 /* iterator for handling rings in ring container */
1055 #define wx_for_each_ring(posm, headm) \
1056 for (posm = (headm).ring; posm; posm = posm->next)
1057
1058 struct wx_ring_container {
1059 struct wx_ring *ring; /* pointer to linked list of rings */
1060 unsigned int total_bytes; /* total bytes processed this int */
1061 unsigned int total_packets; /* total packets processed this int */
1062 u8 count; /* total number of rings in vector */
1063 u8 itr; /* current ITR setting for ring */
1064 struct dim dim; /* data for net_dim algorithm */
1065 };
1066 struct wx_ring {
1067 struct wx_ring *next; /* pointer to next ring in q_vector */
1068 struct wx_q_vector *q_vector; /* backpointer to host q_vector */
1069 struct net_device *netdev; /* netdev ring belongs to */
1070 struct device *dev; /* device for DMA mapping */
1071 struct page_pool *page_pool;
1072 void *desc; /* descriptor ring memory */
1073 union {
1074 struct wx_tx_buffer *tx_buffer_info;
1075 struct wx_rx_buffer *rx_buffer_info;
1076 };
1077 u8 __iomem *tail;
1078 dma_addr_t dma; /* phys. address of descriptor ring */
1079 dma_addr_t headwb_dma;
1080 u32 *headwb_mem;
1081 unsigned int size; /* length in bytes */
1082
1083 u16 count; /* amount of descriptors */
1084 unsigned long last_rx_timestamp;
1085
1086 u8 queue_index; /* needed for multiqueue queue management */
1087 u8 reg_idx; /* holds the special value that gets
1088 * the hardware register offset
1089 * associated with this ring, which is
1090 * different for DCB and RSS modes
1091 */
1092 u16 next_to_use;
1093 u16 next_to_clean;
1094 u16 rx_buf_len;
1095 union {
1096 u16 next_to_alloc;
1097 struct {
1098 u8 atr_sample_rate;
1099 u8 atr_count;
1100 };
1101 };
1102
1103 struct wx_queue_stats stats;
1104 struct u64_stats_sync syncp;
1105 union {
1106 struct wx_tx_queue_stats tx_stats;
1107 struct wx_rx_queue_stats rx_stats;
1108 };
1109 } ____cacheline_internodealigned_in_smp;
1110
1111 struct wx_q_vector {
1112 struct wx *wx;
1113 int cpu; /* CPU for DCA */
1114 int numa_node;
1115 u16 v_idx; /* index of q_vector within array, also used for
1116 * finding the bit in EICR and friends that
1117 * represents the vector for this ring
1118 */
1119 u16 itr; /* Interrupt throttle rate written to EITR */
1120 struct wx_ring_container rx, tx;
1121 struct napi_struct napi;
1122 struct rcu_head rcu; /* to avoid race with update stats on free */
1123
1124 u16 total_events; /* number of interrupts processed */
1125
1126 char name[IFNAMSIZ + 17];
1127
1128 /* for dynamic allocation of rings associated with this q_vector */
1129 struct wx_ring ring[] ____cacheline_internodealigned_in_smp;
1130 };
1131
1132 struct wx_ring_feature {
1133 u16 limit; /* upper limit on feature indices */
1134 u16 indices; /* current value of indices */
1135 u16 mask; /* Mask used for feature to ring mapping */
1136 u16 offset; /* offset to start of feature */
1137 };
1138
1139 enum wx_ring_f_enum {
1140 RING_F_NONE = 0,
1141 RING_F_VMDQ,
1142 RING_F_RSS,
1143 RING_F_FDIR,
1144 RING_F_ARRAY_SIZE /* must be last in enum set */
1145 };
1146
1147 enum wx_isb_idx {
1148 WX_ISB_HEADER,
1149 WX_ISB_MISC,
1150 WX_ISB_VEC0,
1151 WX_ISB_VEC1,
1152 WX_ISB_MAX
1153 };
1154
1155 /* Flow Control Settings */
1156 enum wx_fc_mode {
1157 wx_fc_none = 0,
1158 wx_fc_rx_pause,
1159 wx_fc_tx_pause,
1160 wx_fc_full
1161 };
1162
1163 struct wx_fc_info {
1164 u32 high_water; /* Flow Ctrl High-water */
1165 u32 low_water; /* Flow Ctrl Low-water */
1166 enum wx_fc_mode mode; /* Flow Control Mode */
1167 };
1168
1169 /* Statistics counters collected by the MAC */
1170 struct wx_hw_stats {
1171 u64 gprc;
1172 u64 gptc;
1173 u64 gorc;
1174 u64 gotc;
1175 u64 tpr;
1176 u64 tpt;
1177 u64 bprc;
1178 u64 bptc;
1179 u64 mprc;
1180 u64 mptc;
1181 u64 roc;
1182 u64 ruc;
1183 u64 lxonrxc;
1184 u64 lxoffrxc;
1185 u64 lxontxc;
1186 u64 lxofftxc;
1187 u64 o2bgptc;
1188 u64 b2ospc;
1189 u64 o2bspc;
1190 u64 b2ogprc;
1191 u64 rdmdrop;
1192 u64 crcerrs;
1193 u64 rlec;
1194 u64 qmprc;
1195 u64 fdirmatch;
1196 u64 fdirmiss;
1197 };
1198
1199 struct wx_last_stats {
1200 u32 qmprc[128];
1201 u32 lxoffrxc;
1202 u32 lxonrxc;
1203 };
1204
1205 enum wx_state {
1206 WX_STATE_DOWN,
1207 WX_STATE_RESETTING,
1208 WX_STATE_SWFW_BUSY,
1209 WX_STATE_PTP_RUNNING,
1210 WX_STATE_PTP_TX_IN_PROGRESS,
1211 WX_STATE_SERVICE_SCHED,
1212 WX_STATE_NBITS /* must be last */
1213 };
1214
1215 struct vf_data_storage {
1216 struct pci_dev *vfdev;
1217 unsigned char vf_mac_addr[ETH_ALEN];
1218 bool spoofchk_enabled;
1219 bool link_enable;
1220 bool trusted;
1221 int xcast_mode;
1222 unsigned int vf_api;
1223 bool clear_to_send;
1224 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
1225 u16 pf_qos;
1226 bool pf_set_mac;
1227
1228 u16 vf_mc_hashes[WX_MAX_VF_MC_ENTRIES];
1229 u16 num_vf_mc_hashes;
1230 u16 vlan_count;
1231 int link_state;
1232 };
1233
1234 struct vf_macvlans {
1235 struct list_head mvlist;
1236 int vf;
1237 bool free;
1238 bool is_macvlan;
1239 u8 vf_macvlan[ETH_ALEN];
1240 };
1241
1242 #define WX_RSS_FIELD_IPV4_TCP BIT(0)
1243 #define WX_RSS_FIELD_IPV4 BIT(1)
1244 #define WX_RSS_FIELD_IPV4_SCTP BIT(2)
1245 #define WX_RSS_FIELD_IPV6_SCTP BIT(3)
1246 #define WX_RSS_FIELD_IPV6_TCP BIT(4)
1247 #define WX_RSS_FIELD_IPV6 BIT(5)
1248 #define WX_RSS_FIELD_IPV4_UDP BIT(6)
1249 #define WX_RSS_FIELD_IPV6_UDP BIT(7)
1250
1251 struct wx_rss_flow_map {
1252 u8 flow_type;
1253 u32 data;
1254 u8 flag;
1255 };
1256
1257 enum wx_pf_flags {
1258 WX_FLAG_MULTI_64_FUNC,
1259 WX_FLAG_SWFW_RING,
1260 WX_FLAG_VMDQ_ENABLED,
1261 WX_FLAG_VLAN_PROMISC,
1262 WX_FLAG_SRIOV_ENABLED,
1263 WX_FLAG_IRQ_VECTOR_SHARED,
1264 WX_FLAG_FDIR_CAPABLE,
1265 WX_FLAG_FDIR_HASH,
1266 WX_FLAG_FDIR_PERFECT,
1267 WX_FLAG_RSC_CAPABLE,
1268 WX_FLAG_RSC_ENABLED,
1269 WX_FLAG_RX_HWTSTAMP_ENABLED,
1270 WX_FLAG_RX_HWTSTAMP_IN_REGISTER,
1271 WX_FLAG_PTP_PPS_ENABLED,
1272 WX_FLAG_NEED_LINK_CONFIG,
1273 WX_FLAG_NEED_MODULE_RESET,
1274 WX_FLAG_NEED_UPDATE_LINK,
1275 WX_FLAG_NEED_DO_RESET,
1276 WX_FLAG_RX_MERGE_ENABLED,
1277 WX_FLAG_TXHEAD_WB_ENABLED,
1278 WX_PF_FLAGS_NBITS /* must be last */
1279 };
1280
1281 struct wx {
1282 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
1283 DECLARE_BITMAP(state, WX_STATE_NBITS);
1284 DECLARE_BITMAP(flags, WX_PF_FLAGS_NBITS);
1285
1286 void *priv;
1287 u8 __iomem *hw_addr;
1288 u8 __iomem *b4_addr; /* vf only */
1289 struct pci_dev *pdev;
1290 struct net_device *netdev;
1291 struct wx_bus_info bus;
1292 struct wx_mbx_info mbx;
1293 struct wx_mac_info mac;
1294 enum em_mac_type mac_type;
1295 enum wx_media_type media_type;
1296 struct wx_eeprom_info eeprom;
1297 struct wx_addr_filter_info addr_ctrl;
1298 struct wx_fc_info fc;
1299 struct wx_mac_addr *mac_table;
1300 u16 device_id;
1301 u16 vendor_id;
1302 u16 subsystem_device_id;
1303 u16 subsystem_vendor_id;
1304 u8 revision_id;
1305 u16 oem_ssid;
1306 u16 oem_svid;
1307 u16 msg_enable;
1308 bool adapter_stopped;
1309 u16 tpid[8];
1310 char eeprom_id[32];
1311 char *driver_name;
1312 enum wx_reset_type reset_type;
1313 u8 swfw_index;
1314
1315 /* PHY stuff */
1316 bool notify_down;
1317 unsigned int link;
1318 int speed;
1319 int duplex;
1320 struct phy_device *phydev;
1321 struct phylink *phylink;
1322 struct phylink_config phylink_config;
1323
1324 bool wol_hw_supported;
1325 bool ncsi_enabled;
1326 bool gpio_ctrl;
1327 raw_spinlock_t gpio_lock;
1328
1329 /* Tx fast path data */
1330 int num_tx_queues;
1331 u16 tx_itr_setting;
1332 u16 tx_work_limit;
1333
1334 /* Rx fast path data */
1335 int num_rx_queues;
1336 u16 rx_itr_setting;
1337 u16 rx_work_limit;
1338 bool adaptive_itr;
1339
1340 int num_q_vectors; /* current number of q_vectors for device */
1341 int max_q_vectors; /* upper limit of q_vectors for device */
1342
1343 u32 tx_ring_count;
1344 u32 rx_ring_count;
1345
1346 struct wx_ring *tx_ring[64] ____cacheline_aligned_in_smp;
1347 struct wx_ring *rx_ring[64];
1348 struct wx_q_vector *q_vector[64];
1349 int num_rx_pools;
1350 int num_rx_queues_per_pool;
1351
1352 unsigned int queues_per_pool;
1353 struct msix_entry *msix_q_entries;
1354 struct msix_entry *msix_entry;
1355 struct wx_ring_feature ring_feature[RING_F_ARRAY_SIZE];
1356
1357 /* misc interrupt status block */
1358 dma_addr_t isb_dma;
1359 u32 *isb_mem;
1360 u32 isb_tag[WX_ISB_MAX];
1361 bool misc_irq_domain;
1362 u32 eims_other;
1363 u32 eims_enable_mask;
1364
1365 #define WX_MAX_RETA_ENTRIES 128
1366 #define WX_RSS_INDIR_TBL_MAX 64
1367 u8 rss_indir_tbl[WX_MAX_RETA_ENTRIES];
1368 u8 rss_flags;
1369 bool rss_enabled;
1370 #define WX_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */
1371 u32 *rss_key;
1372 u32 wol;
1373
1374 u16 bd_number;
1375 bool default_up;
1376
1377 struct wx_hw_stats stats;
1378 struct wx_last_stats last_stats;
1379 spinlock_t hw_stats_lock; /* spinlock for accessing to hw stats */
1380 u64 tx_busy;
1381 u64 non_eop_descs;
1382 u64 restart_queue;
1383 u64 hw_csum_rx_good;
1384 u64 hw_csum_rx_error;
1385 u64 alloc_rx_buff_failed;
1386 u64 rsc_count;
1387 u64 rsc_flush;
1388 unsigned int num_vfs;
1389 struct vf_data_storage *vfinfo;
1390 struct vf_macvlans vf_mvs;
1391 struct vf_macvlans *mv_list;
1392 unsigned long fwd_bitmask;
1393
1394 u32 atr_sample_rate;
1395 void (*atr)(struct wx_ring *ring, struct wx_tx_buffer *first, u8 ptype);
1396 void (*configure_fdir)(struct wx *wx);
1397 int (*setup_tc)(struct net_device *netdev, u8 tc);
1398 void (*do_reset)(struct net_device *netdev);
1399 int (*ptp_setup_sdp)(struct wx *wx);
1400 void (*set_num_queues)(struct wx *wx);
1401
1402 bool pps_enabled;
1403 u64 pps_width;
1404 u64 pps_edge_start;
1405 u64 pps_edge_end;
1406 u64 sec_to_cc;
1407 u32 base_incval;
1408 u32 tx_hwtstamp_pkts;
1409 u32 tx_hwtstamp_timeouts;
1410 u32 tx_hwtstamp_skipped;
1411 u32 tx_hwtstamp_errors;
1412 u32 rx_hwtstamp_cleared;
1413 unsigned long last_overflow_check;
1414 unsigned long last_rx_ptp_check;
1415 unsigned long ptp_tx_start;
1416 seqlock_t hw_tc_lock; /* seqlock for ptp */
1417 struct cyclecounter hw_cc;
1418 struct timecounter hw_tc;
1419 struct ptp_clock *ptp_clock;
1420 struct ptp_clock_info ptp_caps;
1421 struct kernel_hwtstamp_config tstamp_config;
1422 struct sk_buff *ptp_tx_skb;
1423
1424 struct timer_list service_timer;
1425 struct work_struct service_task;
1426 struct mutex reset_lock; /* mutex for reset */
1427 };
1428
1429 #define WX_INTR_ALL (~0ULL)
1430 #define WX_INTR_Q(i) BIT((i))
1431
1432 /* register operations */
1433 #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
1434 #define rd32(a, reg) readl((a)->hw_addr + (reg))
1435 #define rd32a(a, reg, offset) ( \
1436 rd32((a), (reg) + ((offset) << 2)))
1437 #define wr32a(a, reg, off, val) \
1438 wr32((a), (reg) + ((off) << 2), (val))
1439
1440 static inline u32
rd32m(struct wx * wx,u32 reg,u32 mask)1441 rd32m(struct wx *wx, u32 reg, u32 mask)
1442 {
1443 u32 val;
1444
1445 val = rd32(wx, reg);
1446 return val & mask;
1447 }
1448
1449 static inline void
wr32m(struct wx * wx,u32 reg,u32 mask,u32 field)1450 wr32m(struct wx *wx, u32 reg, u32 mask, u32 field)
1451 {
1452 u32 val;
1453
1454 val = rd32(wx, reg);
1455 val = ((val & ~mask) | (field & mask));
1456
1457 wr32(wx, reg, val);
1458 }
1459
1460 static inline u64
rd64(struct wx * wx,u32 reg)1461 rd64(struct wx *wx, u32 reg)
1462 {
1463 u64 lsb, msb;
1464
1465 lsb = rd32(wx, reg);
1466 msb = rd32(wx, reg + 4);
1467
1468 return (lsb | msb << 32);
1469 }
1470
1471 static inline u32
rd32ptp(struct wx * wx,u32 reg)1472 rd32ptp(struct wx *wx, u32 reg)
1473 {
1474 if (wx->mac.type == wx_mac_em)
1475 return rd32(wx, reg);
1476
1477 return rd32(wx, reg + 0xB500);
1478 }
1479
1480 static inline void
wr32ptp(struct wx * wx,u32 reg,u32 value)1481 wr32ptp(struct wx *wx, u32 reg, u32 value)
1482 {
1483 if (wx->mac.type == wx_mac_em)
1484 return wr32(wx, reg, value);
1485
1486 return wr32(wx, reg + 0xB500, value);
1487 }
1488
1489 static inline u32
rd32_wrap(struct wx * wx,u32 reg,u32 * last)1490 rd32_wrap(struct wx *wx, u32 reg, u32 *last)
1491 {
1492 u32 val, delta;
1493
1494 val = rd32(wx, reg);
1495 delta = val - *last;
1496 *last = val;
1497
1498 return delta;
1499 }
1500
1501 /* On some domestic CPU platforms, sometimes IO is not synchronized with
1502 * flushing memory, here use readl() to flush PCI read and write.
1503 */
1504 #define WX_WRITE_FLUSH(H) rd32(H, WX_MIS_PWR)
1505
1506 #define wx_err(wx, fmt, arg...) \
1507 dev_err(&(wx)->pdev->dev, fmt, ##arg)
1508
1509 #define wx_dbg(wx, fmt, arg...) \
1510 dev_dbg(&(wx)->pdev->dev, fmt, ##arg)
1511
phylink_to_wx(struct phylink_config * config)1512 static inline struct wx *phylink_to_wx(struct phylink_config *config)
1513 {
1514 return container_of(config, struct wx, phylink_config);
1515 }
1516
wx_rx_pg_order(struct wx_ring * ring)1517 static inline unsigned int wx_rx_pg_order(struct wx_ring *ring)
1518 {
1519 #if (PAGE_SIZE < 8192)
1520 if (ring->rx_buf_len == WX_RXBUFFER_3K)
1521 return 1;
1522 #endif
1523 return 0;
1524 }
1525
1526 #define wx_rx_pg_size(_ring) (PAGE_SIZE << wx_rx_pg_order(_ring))
1527
1528 #endif /* _WX_TYPE_H_ */
1529