Searched refs:WR_CONFIRM (Results 1 – 6 of 6) sorted by relevance
151 #define WR_CONFIRM (1 << 20) macro
1166 (wc ? WR_CONFIRM : 0)); in gfx_v9_0_write_data_to_reg() 1248 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib() 5674 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq() 5683 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_ring_emit_sb() 5713 WR_CONFIRM) | in gfx_v9_0_ring_emit_ce_meta() 5811 WR_CONFIRM) | in gfx_v9_0_ring_emit_de_meta() 5906 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v9_0_ring_emit_wreg() 5912 cmd = WR_CONFIRM; in gfx_v9_0_ring_emit_wreg() 7193 cmd = WR_CONFIRM; in gfx_v9_0_ring_emit_wreg_me()
529 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v11_0_write_data_to_reg() 645 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v11_0_ring_test_ib() 6130 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v11_0_ring_emit_init_cond_exec() 6139 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v11_0_ring_emit_gfx_shadow() 6235 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); in gfx_v11_0_ring_preempt_ib() 6297 WR_CONFIRM) | in gfx_v11_0_ring_emit_de_meta() 6343 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v11_0_ring_emit_wreg() 6349 cmd = WR_CONFIRM; in gfx_v11_0_ring_emit_wreg()
525 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v12_0_ring_test_ib() 4602 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v12_0_ring_emit_cntxcntl() 4611 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v12_0_ring_emit_init_cond_exec() 4680 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v12_0_ring_emit_rreg() 4686 cmd = WR_CONFIRM; in gfx_v12_0_ring_emit_rreg()
1737 #define WR_CONFIRM (1 << 20) macro