Searched refs:WR_CONFIRM (Results 1 – 6 of 6) sorted by relevance
151 #define WR_CONFIRM (1 << 20) macro
1166 (wc ? WR_CONFIRM : 0)); in gfx_v9_0_write_data_to_reg()1248 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()5666 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5675 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5705 WR_CONFIRM) | in gfx_v9_0_ring_emit_ce_meta()5803 WR_CONFIRM) | in gfx_v9_0_ring_emit_de_meta()5898 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v9_0_ring_emit_wreg()5904 cmd = WR_CONFIRM; in gfx_v9_0_ring_emit_wreg()7185 cmd = WR_CONFIRM; in gfx_v9_0_ring_emit_wreg_me()
525 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v11_0_write_data_to_reg()641 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v11_0_ring_test_ib()6086 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()6095 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()6191 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); in gfx_v11_0_ring_emit_gfx_shadow()6303 WR_CONFIRM) | in gfx_v11_0_ring_emit_de_meta()6349 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v11_0_ring_emit_wreg()6355 cmd = WR_CONFIRM; in gfx_v11_0_ring_emit_wreg()
338 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v12_1_ring_test_ib()3463 amdgpu_ring_write(ring, (WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v12_1_ring_emit_fence_kiq()3471 amdgpu_ring_write(ring, (WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v12_1_ring_emit_fence_kiq()3510 cmd = WR_CONFIRM; in gfx_v12_1_ring_emit_wreg()
525 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v12_0_ring_test_ib()4561 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v12_0_ring_emit_fence_kiq()4570 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v12_0_ring_emit_fence_kiq()4689 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v12_0_ring_emit_wreg()4695 cmd = WR_CONFIRM; in gfx_v12_0_ring_emit_wreg()
1737 #define WR_CONFIRM (1 << 20) macro