Searched refs:WRITE_DATA_DST_SEL (Results 1 – 17 of 17) sorted by relevance
152 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
89 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
116 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
142 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
260 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
892 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v8_0_ring_test_ib()5167 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5175 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5183 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5191 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()6281 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()6290 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()7257 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_ce_meta()7290 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_de_meta()
3177 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_wreg()4007 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4015 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4023 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4031 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
463 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v11_0_write_data_to_reg()594 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v11_0_ring_test_ib()5833 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()5842 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()5938 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); in gfx_v11_0_ring_emit_gfx_shadow()6064 WRITE_DATA_DST_SEL(8) | in gfx_v11_0_ring_emit_de_meta()
1138 WRITE_DATA_DST_SEL(0) | in gfx_v9_0_write_data_to_reg()1221 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()5672 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5681 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5720 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_ce_meta()5833 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_de_meta()
385 WRITE_DATA_DST_SEL(0) | in gfx_v9_4_3_write_data_to_reg()479 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_4_3_ring_test_ib()2991 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_4_3_ring_emit_fence_kiq()3000 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_4_3_ring_emit_fence_kiq()
1700 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
3923 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v10_0_write_data_to_reg()4016 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v10_0_ring_test_ib()8709 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()8718 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()8845 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_ce_meta()8881 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_de_meta()
492 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v12_0_ring_test_ib()4469 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v12_0_ring_emit_fence_kiq()4478 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v12_0_ring_emit_fence_kiq()
1637 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
3742 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()5684 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5698 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5705 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5716 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5727 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
1728 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
5062 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5077 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5085 WRITE_DATA_DST_SEL(0))); in si_vm_flush()