Searched refs:WRITE_DATA_DST_SEL (Results 1 – 7 of 7) sorted by relevance
142 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
525 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v11_0_write_data_to_reg()641 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v11_0_ring_test_ib()6086 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()6095 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()6191 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); in gfx_v11_0_ring_emit_gfx_shadow()6302 WRITE_DATA_DST_SEL(8) | in gfx_v11_0_ring_emit_de_meta()
1165 WRITE_DATA_DST_SEL(0) | in gfx_v9_0_write_data_to_reg()1248 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()5666 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5675 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5704 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_ce_meta()5802 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_de_meta()
338 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v12_1_ring_test_ib()3463 amdgpu_ring_write(ring, (WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v12_1_ring_emit_fence_kiq()3471 amdgpu_ring_write(ring, (WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v12_1_ring_emit_fence_kiq()
525 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v12_0_ring_test_ib()4568 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v12_0_ring_emit_fence_kiq()4577 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v12_0_ring_emit_fence_kiq()
2414 WRITE_DATA_DST_SEL(0))); in gfx_v6_0_ring_emit_wreg()
1728 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro