1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * wm8580.c -- WM8580 and WM8581 ALSA Soc Audio driver
4 *
5 * Copyright 2008-12 Wolfson Microelectronics PLC.
6 *
7 * Notes:
8 * The WM8580 is a multichannel codec with S/PDIF support, featuring six
9 * DAC channels and two ADC channels.
10 *
11 * The WM8581 is a multichannel codec with S/PDIF support, featuring eight
12 * DAC channels and two ADC channels.
13 *
14 * Currently only the primary audio interface is supported - S/PDIF and
15 * the secondary audio interfaces are not.
16 */
17
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/pm.h>
24 #include <linux/i2c.h>
25 #include <linux/regmap.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/slab.h>
28
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/soc.h>
33 #include <sound/tlv.h>
34 #include <sound/initval.h>
35 #include <asm/div64.h>
36
37 #include "wm8580.h"
38
39 /* WM8580 register space */
40 #define WM8580_PLLA1 0x00
41 #define WM8580_PLLA2 0x01
42 #define WM8580_PLLA3 0x02
43 #define WM8580_PLLA4 0x03
44 #define WM8580_PLLB1 0x04
45 #define WM8580_PLLB2 0x05
46 #define WM8580_PLLB3 0x06
47 #define WM8580_PLLB4 0x07
48 #define WM8580_CLKSEL 0x08
49 #define WM8580_PAIF1 0x09
50 #define WM8580_PAIF2 0x0A
51 #define WM8580_SAIF1 0x0B
52 #define WM8580_PAIF3 0x0C
53 #define WM8580_PAIF4 0x0D
54 #define WM8580_SAIF2 0x0E
55 #define WM8580_DAC_CONTROL1 0x0F
56 #define WM8580_DAC_CONTROL2 0x10
57 #define WM8580_DAC_CONTROL3 0x11
58 #define WM8580_DAC_CONTROL4 0x12
59 #define WM8580_DAC_CONTROL5 0x13
60 #define WM8580_DIGITAL_ATTENUATION_DACL1 0x14
61 #define WM8580_DIGITAL_ATTENUATION_DACR1 0x15
62 #define WM8580_DIGITAL_ATTENUATION_DACL2 0x16
63 #define WM8580_DIGITAL_ATTENUATION_DACR2 0x17
64 #define WM8580_DIGITAL_ATTENUATION_DACL3 0x18
65 #define WM8580_DIGITAL_ATTENUATION_DACR3 0x19
66 #define WM8581_DIGITAL_ATTENUATION_DACL4 0x1A
67 #define WM8581_DIGITAL_ATTENUATION_DACR4 0x1B
68 #define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C
69 #define WM8580_ADC_CONTROL1 0x1D
70 #define WM8580_SPDTXCHAN0 0x1E
71 #define WM8580_SPDTXCHAN1 0x1F
72 #define WM8580_SPDTXCHAN2 0x20
73 #define WM8580_SPDTXCHAN3 0x21
74 #define WM8580_SPDTXCHAN4 0x22
75 #define WM8580_SPDTXCHAN5 0x23
76 #define WM8580_SPDMODE 0x24
77 #define WM8580_INTMASK 0x25
78 #define WM8580_GPO1 0x26
79 #define WM8580_GPO2 0x27
80 #define WM8580_GPO3 0x28
81 #define WM8580_GPO4 0x29
82 #define WM8580_GPO5 0x2A
83 #define WM8580_INTSTAT 0x2B
84 #define WM8580_SPDRXCHAN1 0x2C
85 #define WM8580_SPDRXCHAN2 0x2D
86 #define WM8580_SPDRXCHAN3 0x2E
87 #define WM8580_SPDRXCHAN4 0x2F
88 #define WM8580_SPDRXCHAN5 0x30
89 #define WM8580_SPDSTAT 0x31
90 #define WM8580_PWRDN1 0x32
91 #define WM8580_PWRDN2 0x33
92 #define WM8580_READBACK 0x34
93 #define WM8580_RESET 0x35
94
95 #define WM8580_MAX_REGISTER 0x35
96
97 #define WM8580_DACOSR 0x40
98
99 /* PLLB4 (register 7h) */
100 #define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60
101 #define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20
102 #define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40
103 #define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60
104
105 #define WM8580_PLLB4_CLKOUTSRC_MASK 0x180
106 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
107 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
108 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK 0x180
109
110 /* CLKSEL (register 8h) */
111 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
112 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
113 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
114
115 /* AIF control 1 (registers 9h-bh) */
116 #define WM8580_AIF_RATE_MASK 0x7
117 #define WM8580_AIF_BCLKSEL_MASK 0x18
118
119 #define WM8580_AIF_MS 0x20
120
121 #define WM8580_AIF_CLKSRC_MASK 0xc0
122 #define WM8580_AIF_CLKSRC_PLLA 0x40
123 #define WM8580_AIF_CLKSRC_PLLB 0x40
124 #define WM8580_AIF_CLKSRC_MCLK 0xc0
125
126 /* AIF control 2 (registers ch-eh) */
127 #define WM8580_AIF_FMT_MASK 0x03
128 #define WM8580_AIF_FMT_RIGHTJ 0x00
129 #define WM8580_AIF_FMT_LEFTJ 0x01
130 #define WM8580_AIF_FMT_I2S 0x02
131 #define WM8580_AIF_FMT_DSP 0x03
132
133 #define WM8580_AIF_LENGTH_MASK 0x0c
134 #define WM8580_AIF_LENGTH_16 0x00
135 #define WM8580_AIF_LENGTH_20 0x04
136 #define WM8580_AIF_LENGTH_24 0x08
137 #define WM8580_AIF_LENGTH_32 0x0c
138
139 #define WM8580_AIF_LRP 0x10
140 #define WM8580_AIF_BCP 0x20
141
142 /* Powerdown Register 1 (register 32h) */
143 #define WM8580_PWRDN1_PWDN 0x001
144 #define WM8580_PWRDN1_ALLDACPD 0x040
145
146 /* Powerdown Register 2 (register 33h) */
147 #define WM8580_PWRDN2_OSSCPD 0x001
148 #define WM8580_PWRDN2_PLLAPD 0x002
149 #define WM8580_PWRDN2_PLLBPD 0x004
150 #define WM8580_PWRDN2_SPDIFPD 0x008
151 #define WM8580_PWRDN2_SPDIFTXD 0x010
152 #define WM8580_PWRDN2_SPDIFRXD 0x020
153
154 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
155
156 /*
157 * wm8580 register cache
158 * We can't read the WM8580 register space when we
159 * are using 2 wire for device control, so we cache them instead.
160 */
161 static const struct reg_default wm8580_reg_defaults[] = {
162 { 0, 0x0121 },
163 { 1, 0x017e },
164 { 2, 0x007d },
165 { 3, 0x0014 },
166 { 4, 0x0121 },
167 { 5, 0x017e },
168 { 6, 0x007d },
169 { 7, 0x0194 },
170 { 8, 0x0010 },
171 { 9, 0x0002 },
172 { 10, 0x0002 },
173 { 11, 0x00c2 },
174 { 12, 0x0182 },
175 { 13, 0x0082 },
176 { 14, 0x000a },
177 { 15, 0x0024 },
178 { 16, 0x0009 },
179 { 17, 0x0000 },
180 { 18, 0x00ff },
181 { 19, 0x0000 },
182 { 20, 0x00ff },
183 { 21, 0x00ff },
184 { 22, 0x00ff },
185 { 23, 0x00ff },
186 { 24, 0x00ff },
187 { 25, 0x00ff },
188 { 26, 0x00ff },
189 { 27, 0x00ff },
190 { 28, 0x01f0 },
191 { 29, 0x0040 },
192 { 30, 0x0000 },
193 { 31, 0x0000 },
194 { 32, 0x0000 },
195 { 33, 0x0000 },
196 { 34, 0x0031 },
197 { 35, 0x000b },
198 { 36, 0x0039 },
199 { 37, 0x0000 },
200 { 38, 0x0010 },
201 { 39, 0x0032 },
202 { 40, 0x0054 },
203 { 41, 0x0076 },
204 { 42, 0x0098 },
205 { 43, 0x0000 },
206 { 44, 0x0000 },
207 { 45, 0x0000 },
208 { 46, 0x0000 },
209 { 47, 0x0000 },
210 { 48, 0x0000 },
211 { 49, 0x0000 },
212 { 50, 0x005e },
213 { 51, 0x003e },
214 { 52, 0x0000 },
215 };
216
wm8580_volatile(struct device * dev,unsigned int reg)217 static bool wm8580_volatile(struct device *dev, unsigned int reg)
218 {
219 switch (reg) {
220 case WM8580_RESET:
221 return true;
222 default:
223 return false;
224 }
225 }
226
227 struct pll_state {
228 unsigned int in;
229 unsigned int out;
230 };
231
232 #define WM8580_NUM_SUPPLIES 3
233 static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
234 "AVDD",
235 "DVDD",
236 "PVDD",
237 };
238
239 struct wm8580_driver_data {
240 int num_dacs;
241 };
242
243 /* codec private data */
244 struct wm8580_priv {
245 struct regmap *regmap;
246 struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
247 struct pll_state a;
248 struct pll_state b;
249 const struct wm8580_driver_data *drvdata;
250 int sysclk[2];
251 };
252
253 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
254
wm8580_out_vu(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)255 static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
256 struct snd_ctl_elem_value *ucontrol)
257 {
258 struct soc_mixer_control *mc =
259 (struct soc_mixer_control *)kcontrol->private_value;
260 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
261 struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
262 unsigned int reg = mc->reg;
263 unsigned int reg2 = mc->rreg;
264 int ret;
265
266 /* Clear the register cache VU so we write without VU set */
267 regcache_cache_only(wm8580->regmap, true);
268 regmap_update_bits(wm8580->regmap, reg, 0x100, 0x000);
269 regmap_update_bits(wm8580->regmap, reg2, 0x100, 0x000);
270 regcache_cache_only(wm8580->regmap, false);
271
272 ret = snd_soc_put_volsw(kcontrol, ucontrol);
273 if (ret < 0)
274 return ret;
275
276 /* Now write again with the volume update bit set */
277 snd_soc_component_update_bits(component, reg, 0x100, 0x100);
278 snd_soc_component_update_bits(component, reg2, 0x100, 0x100);
279
280 return 0;
281 }
282
283 static const struct snd_kcontrol_new wm8580_snd_controls[] = {
284 SOC_DOUBLE_R_EXT_TLV("DAC1 Playback Volume",
285 WM8580_DIGITAL_ATTENUATION_DACL1,
286 WM8580_DIGITAL_ATTENUATION_DACR1,
287 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
288 SOC_DOUBLE_R_EXT_TLV("DAC2 Playback Volume",
289 WM8580_DIGITAL_ATTENUATION_DACL2,
290 WM8580_DIGITAL_ATTENUATION_DACR2,
291 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
292 SOC_DOUBLE_R_EXT_TLV("DAC3 Playback Volume",
293 WM8580_DIGITAL_ATTENUATION_DACL3,
294 WM8580_DIGITAL_ATTENUATION_DACR3,
295 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
296
297 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
298 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
299 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
300
301 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4, 0, 1, 1, 0),
302 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4, 2, 3, 1, 0),
303 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4, 4, 5, 1, 0),
304
305 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
306 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 1),
307 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 1),
308 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 1),
309
310 SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 1),
311 SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
312 };
313
314 static const struct snd_kcontrol_new wm8581_snd_controls[] = {
315 SOC_DOUBLE_R_EXT_TLV("DAC4 Playback Volume",
316 WM8581_DIGITAL_ATTENUATION_DACL4,
317 WM8581_DIGITAL_ATTENUATION_DACR4,
318 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
319
320 SOC_SINGLE("DAC4 Deemphasis Switch", WM8580_DAC_CONTROL3, 3, 1, 0),
321
322 SOC_DOUBLE("DAC4 Invert Switch", WM8580_DAC_CONTROL4, 8, 7, 1, 0),
323
324 SOC_SINGLE("DAC4 Switch", WM8580_DAC_CONTROL5, 3, 1, 1),
325 };
326
327 static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
328 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
329 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
330 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
331
332 SND_SOC_DAPM_OUTPUT("VOUT1L"),
333 SND_SOC_DAPM_OUTPUT("VOUT1R"),
334 SND_SOC_DAPM_OUTPUT("VOUT2L"),
335 SND_SOC_DAPM_OUTPUT("VOUT2R"),
336 SND_SOC_DAPM_OUTPUT("VOUT3L"),
337 SND_SOC_DAPM_OUTPUT("VOUT3R"),
338
339 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
340
341 SND_SOC_DAPM_INPUT("AINL"),
342 SND_SOC_DAPM_INPUT("AINR"),
343 };
344
345 static const struct snd_soc_dapm_widget wm8581_dapm_widgets[] = {
346 SND_SOC_DAPM_DAC("DAC4", "Playback", WM8580_PWRDN1, 5, 1),
347
348 SND_SOC_DAPM_OUTPUT("VOUT4L"),
349 SND_SOC_DAPM_OUTPUT("VOUT4R"),
350 };
351
352 static const struct snd_soc_dapm_route wm8580_dapm_routes[] = {
353 { "VOUT1L", NULL, "DAC1" },
354 { "VOUT1R", NULL, "DAC1" },
355
356 { "VOUT2L", NULL, "DAC2" },
357 { "VOUT2R", NULL, "DAC2" },
358
359 { "VOUT3L", NULL, "DAC3" },
360 { "VOUT3R", NULL, "DAC3" },
361
362 { "ADC", NULL, "AINL" },
363 { "ADC", NULL, "AINR" },
364 };
365
366 static const struct snd_soc_dapm_route wm8581_dapm_routes[] = {
367 { "VOUT4L", NULL, "DAC4" },
368 { "VOUT4R", NULL, "DAC4" },
369 };
370
371 /* PLL divisors */
372 struct _pll_div {
373 u32 prescale:1;
374 u32 postscale:1;
375 u32 freqmode:2;
376 u32 n:4;
377 u32 k:24;
378 };
379
380 /* The size in bits of the pll divide */
381 #define FIXED_PLL_SIZE (1 << 22)
382
383 /* PLL rate to output rate divisions */
384 static struct {
385 unsigned int div;
386 unsigned int freqmode;
387 unsigned int postscale;
388 } post_table[] = {
389 { 2, 0, 0 },
390 { 4, 0, 1 },
391 { 4, 1, 0 },
392 { 8, 1, 1 },
393 { 8, 2, 0 },
394 { 16, 2, 1 },
395 { 12, 3, 0 },
396 { 24, 3, 1 }
397 };
398
pll_factors(struct _pll_div * pll_div,unsigned int target,unsigned int source)399 static int pll_factors(struct _pll_div *pll_div, unsigned int target,
400 unsigned int source)
401 {
402 u64 Kpart;
403 unsigned int K, Ndiv, Nmod;
404 int i;
405
406 pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
407
408 /* Scale the output frequency up; the PLL should run in the
409 * region of 90-100MHz.
410 */
411 for (i = 0; i < ARRAY_SIZE(post_table); i++) {
412 if (target * post_table[i].div >= 90000000 &&
413 target * post_table[i].div <= 100000000) {
414 pll_div->freqmode = post_table[i].freqmode;
415 pll_div->postscale = post_table[i].postscale;
416 target *= post_table[i].div;
417 break;
418 }
419 }
420
421 if (i == ARRAY_SIZE(post_table)) {
422 printk(KERN_ERR "wm8580: Unable to scale output frequency "
423 "%u\n", target);
424 return -EINVAL;
425 }
426
427 Ndiv = target / source;
428
429 if (Ndiv < 5) {
430 source /= 2;
431 pll_div->prescale = 1;
432 Ndiv = target / source;
433 } else
434 pll_div->prescale = 0;
435
436 if ((Ndiv < 5) || (Ndiv > 13)) {
437 printk(KERN_ERR
438 "WM8580 N=%u outside supported range\n", Ndiv);
439 return -EINVAL;
440 }
441
442 pll_div->n = Ndiv;
443 Nmod = target % source;
444 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
445
446 do_div(Kpart, source);
447
448 K = Kpart & 0xFFFFFFFF;
449
450 pll_div->k = K;
451
452 pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
453 pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
454 pll_div->postscale);
455
456 return 0;
457 }
458
wm8580_set_dai_pll(struct snd_soc_dai * codec_dai,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)459 static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
460 int source, unsigned int freq_in, unsigned int freq_out)
461 {
462 int offset;
463 struct snd_soc_component *component = codec_dai->component;
464 struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
465 struct pll_state *state;
466 struct _pll_div pll_div;
467 unsigned int reg;
468 unsigned int pwr_mask;
469 int ret;
470
471 /* GCC isn't able to work out the ifs below for initialising/using
472 * pll_div so suppress warnings.
473 */
474 memset(&pll_div, 0, sizeof(pll_div));
475
476 switch (pll_id) {
477 case WM8580_PLLA:
478 state = &wm8580->a;
479 offset = 0;
480 pwr_mask = WM8580_PWRDN2_PLLAPD;
481 break;
482 case WM8580_PLLB:
483 state = &wm8580->b;
484 offset = 4;
485 pwr_mask = WM8580_PWRDN2_PLLBPD;
486 break;
487 default:
488 return -ENODEV;
489 }
490
491 if (freq_in && freq_out) {
492 ret = pll_factors(&pll_div, freq_out, freq_in);
493 if (ret != 0)
494 return ret;
495 }
496
497 state->in = freq_in;
498 state->out = freq_out;
499
500 /* Always disable the PLL - it is not safe to leave it running
501 * while reprogramming it.
502 */
503 snd_soc_component_update_bits(component, WM8580_PWRDN2, pwr_mask, pwr_mask);
504
505 if (!freq_in || !freq_out)
506 return 0;
507
508 snd_soc_component_write(component, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
509 snd_soc_component_write(component, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
510 snd_soc_component_write(component, WM8580_PLLA3 + offset,
511 (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
512
513 reg = snd_soc_component_read(component, WM8580_PLLA4 + offset);
514 reg &= ~0x1b;
515 reg |= pll_div.prescale | pll_div.postscale << 1 |
516 pll_div.freqmode << 3;
517
518 snd_soc_component_write(component, WM8580_PLLA4 + offset, reg);
519
520 /* All done, turn it on */
521 snd_soc_component_update_bits(component, WM8580_PWRDN2, pwr_mask, 0);
522
523 return 0;
524 }
525
526 static const int wm8580_sysclk_ratios[] = {
527 128, 192, 256, 384, 512, 768, 1152,
528 };
529
530 /*
531 * Set PCM DAI bit size and sample rate.
532 */
wm8580_paif_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)533 static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
534 struct snd_pcm_hw_params *params,
535 struct snd_soc_dai *dai)
536 {
537 struct snd_soc_component *component = dai->component;
538 struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
539 u16 paifa = 0;
540 u16 paifb = 0;
541 int i, ratio, osr;
542
543 /* bit size */
544 switch (params_width(params)) {
545 case 16:
546 paifa |= 0x8;
547 break;
548 case 20:
549 paifa |= 0x0;
550 paifb |= WM8580_AIF_LENGTH_20;
551 break;
552 case 24:
553 paifa |= 0x0;
554 paifb |= WM8580_AIF_LENGTH_24;
555 break;
556 case 32:
557 paifa |= 0x0;
558 paifb |= WM8580_AIF_LENGTH_32;
559 break;
560 default:
561 return -EINVAL;
562 }
563
564 /* Look up the SYSCLK ratio; accept only exact matches */
565 ratio = wm8580->sysclk[dai->driver->id] / params_rate(params);
566 for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++)
567 if (ratio == wm8580_sysclk_ratios[i])
568 break;
569 if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) {
570 dev_err(component->dev, "Invalid clock ratio %d/%d\n",
571 wm8580->sysclk[dai->driver->id], params_rate(params));
572 return -EINVAL;
573 }
574 paifa |= i;
575 dev_dbg(component->dev, "Running at %dfs with %dHz clock\n",
576 wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]);
577
578 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
579 switch (ratio) {
580 case 128:
581 case 192:
582 osr = WM8580_DACOSR;
583 dev_dbg(component->dev, "Selecting 64x OSR\n");
584 break;
585 default:
586 osr = 0;
587 dev_dbg(component->dev, "Selecting 128x OSR\n");
588 break;
589 }
590
591 snd_soc_component_update_bits(component, WM8580_PAIF3, WM8580_DACOSR, osr);
592 }
593
594 snd_soc_component_update_bits(component, WM8580_PAIF1 + dai->driver->id,
595 WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK,
596 paifa);
597 snd_soc_component_update_bits(component, WM8580_PAIF3 + dai->driver->id,
598 WM8580_AIF_LENGTH_MASK, paifb);
599 return 0;
600 }
601
wm8580_set_paif_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)602 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
603 unsigned int fmt)
604 {
605 struct snd_soc_component *component = codec_dai->component;
606 unsigned int aifa;
607 unsigned int aifb;
608 int can_invert_lrclk;
609
610 aifa = snd_soc_component_read(component, WM8580_PAIF1 + codec_dai->driver->id);
611 aifb = snd_soc_component_read(component, WM8580_PAIF3 + codec_dai->driver->id);
612
613 aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
614
615 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
616 case SND_SOC_DAIFMT_CBC_CFC:
617 aifa &= ~WM8580_AIF_MS;
618 break;
619 case SND_SOC_DAIFMT_CBP_CFP:
620 aifa |= WM8580_AIF_MS;
621 break;
622 default:
623 return -EINVAL;
624 }
625
626 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
627 case SND_SOC_DAIFMT_I2S:
628 can_invert_lrclk = 1;
629 aifb |= WM8580_AIF_FMT_I2S;
630 break;
631 case SND_SOC_DAIFMT_RIGHT_J:
632 can_invert_lrclk = 1;
633 aifb |= WM8580_AIF_FMT_RIGHTJ;
634 break;
635 case SND_SOC_DAIFMT_LEFT_J:
636 can_invert_lrclk = 1;
637 aifb |= WM8580_AIF_FMT_LEFTJ;
638 break;
639 case SND_SOC_DAIFMT_DSP_A:
640 can_invert_lrclk = 0;
641 aifb |= WM8580_AIF_FMT_DSP;
642 break;
643 case SND_SOC_DAIFMT_DSP_B:
644 can_invert_lrclk = 0;
645 aifb |= WM8580_AIF_FMT_DSP;
646 aifb |= WM8580_AIF_LRP;
647 break;
648 default:
649 return -EINVAL;
650 }
651
652 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
653 case SND_SOC_DAIFMT_NB_NF:
654 break;
655
656 case SND_SOC_DAIFMT_IB_IF:
657 if (!can_invert_lrclk)
658 return -EINVAL;
659 aifb |= WM8580_AIF_BCP;
660 aifb |= WM8580_AIF_LRP;
661 break;
662
663 case SND_SOC_DAIFMT_IB_NF:
664 aifb |= WM8580_AIF_BCP;
665 break;
666
667 case SND_SOC_DAIFMT_NB_IF:
668 if (!can_invert_lrclk)
669 return -EINVAL;
670 aifb |= WM8580_AIF_LRP;
671 break;
672
673 default:
674 return -EINVAL;
675 }
676
677 snd_soc_component_write(component, WM8580_PAIF1 + codec_dai->driver->id, aifa);
678 snd_soc_component_write(component, WM8580_PAIF3 + codec_dai->driver->id, aifb);
679
680 return 0;
681 }
682
wm8580_set_dai_clkdiv(struct snd_soc_dai * codec_dai,int div_id,int div)683 static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
684 int div_id, int div)
685 {
686 struct snd_soc_component *component = codec_dai->component;
687 unsigned int reg;
688
689 switch (div_id) {
690 case WM8580_MCLK:
691 reg = snd_soc_component_read(component, WM8580_PLLB4);
692 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
693
694 switch (div) {
695 case WM8580_CLKSRC_MCLK:
696 /* Input */
697 break;
698
699 case WM8580_CLKSRC_PLLA:
700 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
701 break;
702 case WM8580_CLKSRC_PLLB:
703 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
704 break;
705
706 case WM8580_CLKSRC_OSC:
707 reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
708 break;
709
710 default:
711 return -EINVAL;
712 }
713 snd_soc_component_write(component, WM8580_PLLB4, reg);
714 break;
715
716 case WM8580_CLKOUTSRC:
717 reg = snd_soc_component_read(component, WM8580_PLLB4);
718 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
719
720 switch (div) {
721 case WM8580_CLKSRC_NONE:
722 break;
723
724 case WM8580_CLKSRC_PLLA:
725 reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
726 break;
727
728 case WM8580_CLKSRC_PLLB:
729 reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
730 break;
731
732 case WM8580_CLKSRC_OSC:
733 reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
734 break;
735
736 default:
737 return -EINVAL;
738 }
739 snd_soc_component_write(component, WM8580_PLLB4, reg);
740 break;
741
742 default:
743 return -EINVAL;
744 }
745
746 return 0;
747 }
748
wm8580_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)749 static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id,
750 unsigned int freq, int dir)
751 {
752 struct snd_soc_component *component = dai->component;
753 struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
754 int ret, sel, sel_mask, sel_shift;
755
756 switch (dai->driver->id) {
757 case WM8580_DAI_PAIFRX:
758 sel_mask = 0x3;
759 sel_shift = 0;
760 break;
761
762 case WM8580_DAI_PAIFTX:
763 sel_mask = 0xc;
764 sel_shift = 2;
765 break;
766
767 default:
768 WARN(1, "Unknown DAI driver ID\n");
769 return -EINVAL;
770 }
771
772 switch (clk_id) {
773 case WM8580_CLKSRC_ADCMCLK:
774 if (dai->driver->id != WM8580_DAI_PAIFTX)
775 return -EINVAL;
776 sel = 0 << sel_shift;
777 break;
778 case WM8580_CLKSRC_PLLA:
779 sel = 1 << sel_shift;
780 break;
781 case WM8580_CLKSRC_PLLB:
782 sel = 2 << sel_shift;
783 break;
784 case WM8580_CLKSRC_MCLK:
785 sel = 3 << sel_shift;
786 break;
787 default:
788 dev_err(component->dev, "Unknown clock %d\n", clk_id);
789 return -EINVAL;
790 }
791
792 /* We really should validate PLL settings but not yet */
793 wm8580->sysclk[dai->driver->id] = freq;
794
795 ret = snd_soc_component_update_bits(component, WM8580_CLKSEL, sel_mask, sel);
796 if (ret < 0)
797 return ret;
798
799 return 0;
800 }
801
wm8580_mute(struct snd_soc_dai * codec_dai,int mute,int direction)802 static int wm8580_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
803 {
804 struct snd_soc_component *component = codec_dai->component;
805 unsigned int reg;
806
807 reg = snd_soc_component_read(component, WM8580_DAC_CONTROL5);
808
809 if (mute)
810 reg |= WM8580_DAC_CONTROL5_MUTEALL;
811 else
812 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
813
814 snd_soc_component_write(component, WM8580_DAC_CONTROL5, reg);
815
816 return 0;
817 }
818
wm8580_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)819 static int wm8580_set_bias_level(struct snd_soc_component *component,
820 enum snd_soc_bias_level level)
821 {
822 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
823
824 switch (level) {
825 case SND_SOC_BIAS_ON:
826 case SND_SOC_BIAS_PREPARE:
827 break;
828
829 case SND_SOC_BIAS_STANDBY:
830 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) {
831 /* Power up and get individual control of the DACs */
832 snd_soc_component_update_bits(component, WM8580_PWRDN1,
833 WM8580_PWRDN1_PWDN |
834 WM8580_PWRDN1_ALLDACPD, 0);
835
836 /* Make VMID high impedance */
837 snd_soc_component_update_bits(component, WM8580_ADC_CONTROL1,
838 0x100, 0);
839 }
840 break;
841
842 case SND_SOC_BIAS_OFF:
843 snd_soc_component_update_bits(component, WM8580_PWRDN1,
844 WM8580_PWRDN1_PWDN, WM8580_PWRDN1_PWDN);
845 break;
846 }
847 return 0;
848 }
849
wm8580_playback_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)850 static int wm8580_playback_startup(struct snd_pcm_substream *substream,
851 struct snd_soc_dai *dai)
852 {
853 struct snd_soc_component *component = dai->component;
854 struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
855
856 return snd_pcm_hw_constraint_minmax(substream->runtime,
857 SNDRV_PCM_HW_PARAM_CHANNELS, 1, wm8580->drvdata->num_dacs * 2);
858 }
859
860 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
861 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
862
863 static const struct snd_soc_dai_ops wm8580_dai_ops_playback = {
864 .startup = wm8580_playback_startup,
865 .set_sysclk = wm8580_set_sysclk,
866 .hw_params = wm8580_paif_hw_params,
867 .set_fmt = wm8580_set_paif_dai_fmt,
868 .set_clkdiv = wm8580_set_dai_clkdiv,
869 .set_pll = wm8580_set_dai_pll,
870 .mute_stream = wm8580_mute,
871 .no_capture_mute = 1,
872 };
873
874 static const struct snd_soc_dai_ops wm8580_dai_ops_capture = {
875 .set_sysclk = wm8580_set_sysclk,
876 .hw_params = wm8580_paif_hw_params,
877 .set_fmt = wm8580_set_paif_dai_fmt,
878 .set_clkdiv = wm8580_set_dai_clkdiv,
879 .set_pll = wm8580_set_dai_pll,
880 };
881
882 static struct snd_soc_dai_driver wm8580_dai[] = {
883 {
884 .name = "wm8580-hifi-playback",
885 .id = WM8580_DAI_PAIFRX,
886 .playback = {
887 .stream_name = "Playback",
888 .channels_min = 1,
889 .rates = SNDRV_PCM_RATE_8000_192000,
890 .formats = WM8580_FORMATS,
891 },
892 .ops = &wm8580_dai_ops_playback,
893 },
894 {
895 .name = "wm8580-hifi-capture",
896 .id = WM8580_DAI_PAIFTX,
897 .capture = {
898 .stream_name = "Capture",
899 .channels_min = 2,
900 .channels_max = 2,
901 .rates = SNDRV_PCM_RATE_8000_192000,
902 .formats = WM8580_FORMATS,
903 },
904 .ops = &wm8580_dai_ops_capture,
905 },
906 };
907
wm8580_probe(struct snd_soc_component * component)908 static int wm8580_probe(struct snd_soc_component *component)
909 {
910 struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
911 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
912 int ret = 0;
913
914 switch (wm8580->drvdata->num_dacs) {
915 case 4:
916 snd_soc_add_component_controls(component, wm8581_snd_controls,
917 ARRAY_SIZE(wm8581_snd_controls));
918 snd_soc_dapm_new_controls(dapm, wm8581_dapm_widgets,
919 ARRAY_SIZE(wm8581_dapm_widgets));
920 snd_soc_dapm_add_routes(dapm, wm8581_dapm_routes,
921 ARRAY_SIZE(wm8581_dapm_routes));
922 break;
923 default:
924 break;
925 }
926
927 ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
928 wm8580->supplies);
929 if (ret != 0) {
930 dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
931 goto err_regulator_get;
932 }
933
934 /* Get the codec into a known state */
935 ret = snd_soc_component_write(component, WM8580_RESET, 0);
936 if (ret != 0) {
937 dev_err(component->dev, "Failed to reset component: %d\n", ret);
938 goto err_regulator_enable;
939 }
940
941 return 0;
942
943 err_regulator_enable:
944 regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
945 err_regulator_get:
946 return ret;
947 }
948
949 /* power down chip */
wm8580_remove(struct snd_soc_component * component)950 static void wm8580_remove(struct snd_soc_component *component)
951 {
952 struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
953
954 regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
955 }
956
957 static const struct snd_soc_component_driver soc_component_dev_wm8580 = {
958 .probe = wm8580_probe,
959 .remove = wm8580_remove,
960 .set_bias_level = wm8580_set_bias_level,
961 .controls = wm8580_snd_controls,
962 .num_controls = ARRAY_SIZE(wm8580_snd_controls),
963 .dapm_widgets = wm8580_dapm_widgets,
964 .num_dapm_widgets = ARRAY_SIZE(wm8580_dapm_widgets),
965 .dapm_routes = wm8580_dapm_routes,
966 .num_dapm_routes = ARRAY_SIZE(wm8580_dapm_routes),
967 .idle_bias_on = 1,
968 .use_pmdown_time = 1,
969 .endianness = 1,
970 };
971
972 static const struct regmap_config wm8580_regmap = {
973 .reg_bits = 7,
974 .val_bits = 9,
975 .max_register = WM8580_MAX_REGISTER,
976
977 .reg_defaults = wm8580_reg_defaults,
978 .num_reg_defaults = ARRAY_SIZE(wm8580_reg_defaults),
979 .cache_type = REGCACHE_MAPLE,
980
981 .volatile_reg = wm8580_volatile,
982 };
983
984 static const struct wm8580_driver_data wm8580_data = {
985 .num_dacs = 3,
986 };
987
988 static const struct wm8580_driver_data wm8581_data = {
989 .num_dacs = 4,
990 };
991
wm8580_i2c_probe(struct i2c_client * i2c)992 static int wm8580_i2c_probe(struct i2c_client *i2c)
993 {
994 struct wm8580_priv *wm8580;
995 int ret, i;
996
997 wm8580 = devm_kzalloc(&i2c->dev, sizeof(struct wm8580_priv),
998 GFP_KERNEL);
999 if (wm8580 == NULL)
1000 return -ENOMEM;
1001
1002 wm8580->regmap = devm_regmap_init_i2c(i2c, &wm8580_regmap);
1003 if (IS_ERR(wm8580->regmap))
1004 return PTR_ERR(wm8580->regmap);
1005
1006 for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
1007 wm8580->supplies[i].supply = wm8580_supply_names[i];
1008
1009 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8580->supplies),
1010 wm8580->supplies);
1011 if (ret != 0) {
1012 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1013 return ret;
1014 }
1015
1016 i2c_set_clientdata(i2c, wm8580);
1017
1018 wm8580->drvdata = i2c_get_match_data(i2c);
1019 if (!wm8580->drvdata)
1020 return dev_err_probe(&i2c->dev, -EINVAL, "failed to find driver data\n");
1021
1022 ret = devm_snd_soc_register_component(&i2c->dev,
1023 &soc_component_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai));
1024
1025 return ret;
1026 }
1027
1028 static const struct of_device_id wm8580_of_match[] = {
1029 { .compatible = "wlf,wm8580", .data = &wm8580_data },
1030 { .compatible = "wlf,wm8581", .data = &wm8581_data },
1031 { }
1032 };
1033 MODULE_DEVICE_TABLE(of, wm8580_of_match);
1034
1035 static const struct i2c_device_id wm8580_i2c_id[] = {
1036 { .name = "wm8580", .driver_data = (kernel_ulong_t)&wm8580_data },
1037 { .name = "wm8581", .driver_data = (kernel_ulong_t)&wm8581_data },
1038 { }
1039 };
1040 MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
1041
1042 static struct i2c_driver wm8580_i2c_driver = {
1043 .driver = {
1044 .name = "wm8580",
1045 .of_match_table = wm8580_of_match,
1046 },
1047 .probe = wm8580_i2c_probe,
1048 .id_table = wm8580_i2c_id,
1049 };
1050
1051 module_i2c_driver(wm8580_i2c_driver);
1052
1053 MODULE_DESCRIPTION("ASoC WM8580 driver");
1054 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1055 MODULE_AUTHOR("Matt Flax <flatmax@flatmax.org>");
1056 MODULE_LICENSE("GPL");
1057