xref: /linux/include/linux/mfd/wm831x/regulator.h (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * linux/mfd/wm831x/regulator.h -- Regulator definitons for wm831x
4  *
5  * Copyright 2009 Wolfson Microelectronics PLC.
6  *
7  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8  */
9 
10 #ifndef __MFD_WM831X_REGULATOR_H__
11 #define __MFD_WM831X_REGULATOR_H__
12 
13 /*
14  * R16462 (0x404E) - Current Sink 1
15  */
16 #define WM831X_CS1_ENA                          0x8000  /* CS1_ENA */
17 #define WM831X_CS1_ENA_MASK                     0x8000  /* CS1_ENA */
18 #define WM831X_CS1_ENA_SHIFT                        15  /* CS1_ENA */
19 #define WM831X_CS1_ENA_WIDTH                         1  /* CS1_ENA */
20 #define WM831X_CS1_DRIVE                        0x4000  /* CS1_DRIVE */
21 #define WM831X_CS1_DRIVE_MASK                   0x4000  /* CS1_DRIVE */
22 #define WM831X_CS1_DRIVE_SHIFT                      14  /* CS1_DRIVE */
23 #define WM831X_CS1_DRIVE_WIDTH                       1  /* CS1_DRIVE */
24 #define WM831X_CS1_SLPENA                       0x1000  /* CS1_SLPENA */
25 #define WM831X_CS1_SLPENA_MASK                  0x1000  /* CS1_SLPENA */
26 #define WM831X_CS1_SLPENA_SHIFT                     12  /* CS1_SLPENA */
27 #define WM831X_CS1_SLPENA_WIDTH                      1  /* CS1_SLPENA */
28 #define WM831X_CS1_OFF_RAMP_MASK                0x0C00  /* CS1_OFF_RAMP - [11:10] */
29 #define WM831X_CS1_OFF_RAMP_SHIFT                   10  /* CS1_OFF_RAMP - [11:10] */
30 #define WM831X_CS1_OFF_RAMP_WIDTH                    2  /* CS1_OFF_RAMP - [11:10] */
31 #define WM831X_CS1_ON_RAMP_MASK                 0x0300  /* CS1_ON_RAMP - [9:8] */
32 #define WM831X_CS1_ON_RAMP_SHIFT                     8  /* CS1_ON_RAMP - [9:8] */
33 #define WM831X_CS1_ON_RAMP_WIDTH                     2  /* CS1_ON_RAMP - [9:8] */
34 #define WM831X_CS1_ISEL_MASK                    0x003F  /* CS1_ISEL - [5:0] */
35 #define WM831X_CS1_ISEL_SHIFT                        0  /* CS1_ISEL - [5:0] */
36 #define WM831X_CS1_ISEL_WIDTH                        6  /* CS1_ISEL - [5:0] */
37 
38 /*
39  * R16463 (0x404F) - Current Sink 2
40  */
41 #define WM831X_CS2_ENA                          0x8000  /* CS2_ENA */
42 #define WM831X_CS2_ENA_MASK                     0x8000  /* CS2_ENA */
43 #define WM831X_CS2_ENA_SHIFT                        15  /* CS2_ENA */
44 #define WM831X_CS2_ENA_WIDTH                         1  /* CS2_ENA */
45 #define WM831X_CS2_DRIVE                        0x4000  /* CS2_DRIVE */
46 #define WM831X_CS2_DRIVE_MASK                   0x4000  /* CS2_DRIVE */
47 #define WM831X_CS2_DRIVE_SHIFT                      14  /* CS2_DRIVE */
48 #define WM831X_CS2_DRIVE_WIDTH                       1  /* CS2_DRIVE */
49 #define WM831X_CS2_SLPENA                       0x1000  /* CS2_SLPENA */
50 #define WM831X_CS2_SLPENA_MASK                  0x1000  /* CS2_SLPENA */
51 #define WM831X_CS2_SLPENA_SHIFT                     12  /* CS2_SLPENA */
52 #define WM831X_CS2_SLPENA_WIDTH                      1  /* CS2_SLPENA */
53 #define WM831X_CS2_OFF_RAMP_MASK                0x0C00  /* CS2_OFF_RAMP - [11:10] */
54 #define WM831X_CS2_OFF_RAMP_SHIFT                   10  /* CS2_OFF_RAMP - [11:10] */
55 #define WM831X_CS2_OFF_RAMP_WIDTH                    2  /* CS2_OFF_RAMP - [11:10] */
56 #define WM831X_CS2_ON_RAMP_MASK                 0x0300  /* CS2_ON_RAMP - [9:8] */
57 #define WM831X_CS2_ON_RAMP_SHIFT                     8  /* CS2_ON_RAMP - [9:8] */
58 #define WM831X_CS2_ON_RAMP_WIDTH                     2  /* CS2_ON_RAMP - [9:8] */
59 #define WM831X_CS2_ISEL_MASK                    0x003F  /* CS2_ISEL - [5:0] */
60 #define WM831X_CS2_ISEL_SHIFT                        0  /* CS2_ISEL - [5:0] */
61 #define WM831X_CS2_ISEL_WIDTH                        6  /* CS2_ISEL - [5:0] */
62 
63 /*
64  * R16464 (0x4050) - DCDC Enable
65  */
66 #define WM831X_EPE2_ENA                         0x0080  /* EPE2_ENA */
67 #define WM831X_EPE2_ENA_MASK                    0x0080  /* EPE2_ENA */
68 #define WM831X_EPE2_ENA_SHIFT                        7  /* EPE2_ENA */
69 #define WM831X_EPE2_ENA_WIDTH                        1  /* EPE2_ENA */
70 #define WM831X_EPE1_ENA                         0x0040  /* EPE1_ENA */
71 #define WM831X_EPE1_ENA_MASK                    0x0040  /* EPE1_ENA */
72 #define WM831X_EPE1_ENA_SHIFT                        6  /* EPE1_ENA */
73 #define WM831X_EPE1_ENA_WIDTH                        1  /* EPE1_ENA */
74 #define WM831X_DC4_ENA                          0x0008  /* DC4_ENA */
75 #define WM831X_DC4_ENA_MASK                     0x0008  /* DC4_ENA */
76 #define WM831X_DC4_ENA_SHIFT                         3  /* DC4_ENA */
77 #define WM831X_DC4_ENA_WIDTH                         1  /* DC4_ENA */
78 #define WM831X_DC3_ENA                          0x0004  /* DC3_ENA */
79 #define WM831X_DC3_ENA_MASK                     0x0004  /* DC3_ENA */
80 #define WM831X_DC3_ENA_SHIFT                         2  /* DC3_ENA */
81 #define WM831X_DC3_ENA_WIDTH                         1  /* DC3_ENA */
82 #define WM831X_DC2_ENA                          0x0002  /* DC2_ENA */
83 #define WM831X_DC2_ENA_MASK                     0x0002  /* DC2_ENA */
84 #define WM831X_DC2_ENA_SHIFT                         1  /* DC2_ENA */
85 #define WM831X_DC2_ENA_WIDTH                         1  /* DC2_ENA */
86 #define WM831X_DC1_ENA                          0x0001  /* DC1_ENA */
87 #define WM831X_DC1_ENA_MASK                     0x0001  /* DC1_ENA */
88 #define WM831X_DC1_ENA_SHIFT                         0  /* DC1_ENA */
89 #define WM831X_DC1_ENA_WIDTH                         1  /* DC1_ENA */
90 
91 /*
92  * R16465 (0x4051) - LDO Enable
93  */
94 #define WM831X_LDO11_ENA                        0x0400  /* LDO11_ENA */
95 #define WM831X_LDO11_ENA_MASK                   0x0400  /* LDO11_ENA */
96 #define WM831X_LDO11_ENA_SHIFT                      10  /* LDO11_ENA */
97 #define WM831X_LDO11_ENA_WIDTH                       1  /* LDO11_ENA */
98 #define WM831X_LDO10_ENA                        0x0200  /* LDO10_ENA */
99 #define WM831X_LDO10_ENA_MASK                   0x0200  /* LDO10_ENA */
100 #define WM831X_LDO10_ENA_SHIFT                       9  /* LDO10_ENA */
101 #define WM831X_LDO10_ENA_WIDTH                       1  /* LDO10_ENA */
102 #define WM831X_LDO9_ENA                         0x0100  /* LDO9_ENA */
103 #define WM831X_LDO9_ENA_MASK                    0x0100  /* LDO9_ENA */
104 #define WM831X_LDO9_ENA_SHIFT                        8  /* LDO9_ENA */
105 #define WM831X_LDO9_ENA_WIDTH                        1  /* LDO9_ENA */
106 #define WM831X_LDO8_ENA                         0x0080  /* LDO8_ENA */
107 #define WM831X_LDO8_ENA_MASK                    0x0080  /* LDO8_ENA */
108 #define WM831X_LDO8_ENA_SHIFT                        7  /* LDO8_ENA */
109 #define WM831X_LDO8_ENA_WIDTH                        1  /* LDO8_ENA */
110 #define WM831X_LDO7_ENA                         0x0040  /* LDO7_ENA */
111 #define WM831X_LDO7_ENA_MASK                    0x0040  /* LDO7_ENA */
112 #define WM831X_LDO7_ENA_SHIFT                        6  /* LDO7_ENA */
113 #define WM831X_LDO7_ENA_WIDTH                        1  /* LDO7_ENA */
114 #define WM831X_LDO6_ENA                         0x0020  /* LDO6_ENA */
115 #define WM831X_LDO6_ENA_MASK                    0x0020  /* LDO6_ENA */
116 #define WM831X_LDO6_ENA_SHIFT                        5  /* LDO6_ENA */
117 #define WM831X_LDO6_ENA_WIDTH                        1  /* LDO6_ENA */
118 #define WM831X_LDO5_ENA                         0x0010  /* LDO5_ENA */
119 #define WM831X_LDO5_ENA_MASK                    0x0010  /* LDO5_ENA */
120 #define WM831X_LDO5_ENA_SHIFT                        4  /* LDO5_ENA */
121 #define WM831X_LDO5_ENA_WIDTH                        1  /* LDO5_ENA */
122 #define WM831X_LDO4_ENA                         0x0008  /* LDO4_ENA */
123 #define WM831X_LDO4_ENA_MASK                    0x0008  /* LDO4_ENA */
124 #define WM831X_LDO4_ENA_SHIFT                        3  /* LDO4_ENA */
125 #define WM831X_LDO4_ENA_WIDTH                        1  /* LDO4_ENA */
126 #define WM831X_LDO3_ENA                         0x0004  /* LDO3_ENA */
127 #define WM831X_LDO3_ENA_MASK                    0x0004  /* LDO3_ENA */
128 #define WM831X_LDO3_ENA_SHIFT                        2  /* LDO3_ENA */
129 #define WM831X_LDO3_ENA_WIDTH                        1  /* LDO3_ENA */
130 #define WM831X_LDO2_ENA                         0x0002  /* LDO2_ENA */
131 #define WM831X_LDO2_ENA_MASK                    0x0002  /* LDO2_ENA */
132 #define WM831X_LDO2_ENA_SHIFT                        1  /* LDO2_ENA */
133 #define WM831X_LDO2_ENA_WIDTH                        1  /* LDO2_ENA */
134 #define WM831X_LDO1_ENA                         0x0001  /* LDO1_ENA */
135 #define WM831X_LDO1_ENA_MASK                    0x0001  /* LDO1_ENA */
136 #define WM831X_LDO1_ENA_SHIFT                        0  /* LDO1_ENA */
137 #define WM831X_LDO1_ENA_WIDTH                        1  /* LDO1_ENA */
138 
139 /*
140  * R16466 (0x4052) - DCDC Status
141  */
142 #define WM831X_EPE2_STS                         0x0080  /* EPE2_STS */
143 #define WM831X_EPE2_STS_MASK                    0x0080  /* EPE2_STS */
144 #define WM831X_EPE2_STS_SHIFT                        7  /* EPE2_STS */
145 #define WM831X_EPE2_STS_WIDTH                        1  /* EPE2_STS */
146 #define WM831X_EPE1_STS                         0x0040  /* EPE1_STS */
147 #define WM831X_EPE1_STS_MASK                    0x0040  /* EPE1_STS */
148 #define WM831X_EPE1_STS_SHIFT                        6  /* EPE1_STS */
149 #define WM831X_EPE1_STS_WIDTH                        1  /* EPE1_STS */
150 #define WM831X_DC4_STS                          0x0008  /* DC4_STS */
151 #define WM831X_DC4_STS_MASK                     0x0008  /* DC4_STS */
152 #define WM831X_DC4_STS_SHIFT                         3  /* DC4_STS */
153 #define WM831X_DC4_STS_WIDTH                         1  /* DC4_STS */
154 #define WM831X_DC3_STS                          0x0004  /* DC3_STS */
155 #define WM831X_DC3_STS_MASK                     0x0004  /* DC3_STS */
156 #define WM831X_DC3_STS_SHIFT                         2  /* DC3_STS */
157 #define WM831X_DC3_STS_WIDTH                         1  /* DC3_STS */
158 #define WM831X_DC2_STS                          0x0002  /* DC2_STS */
159 #define WM831X_DC2_STS_MASK                     0x0002  /* DC2_STS */
160 #define WM831X_DC2_STS_SHIFT                         1  /* DC2_STS */
161 #define WM831X_DC2_STS_WIDTH                         1  /* DC2_STS */
162 #define WM831X_DC1_STS                          0x0001  /* DC1_STS */
163 #define WM831X_DC1_STS_MASK                     0x0001  /* DC1_STS */
164 #define WM831X_DC1_STS_SHIFT                         0  /* DC1_STS */
165 #define WM831X_DC1_STS_WIDTH                         1  /* DC1_STS */
166 
167 /*
168  * R16467 (0x4053) - LDO Status
169  */
170 #define WM831X_LDO11_STS                        0x0400  /* LDO11_STS */
171 #define WM831X_LDO11_STS_MASK                   0x0400  /* LDO11_STS */
172 #define WM831X_LDO11_STS_SHIFT                      10  /* LDO11_STS */
173 #define WM831X_LDO11_STS_WIDTH                       1  /* LDO11_STS */
174 #define WM831X_LDO10_STS                        0x0200  /* LDO10_STS */
175 #define WM831X_LDO10_STS_MASK                   0x0200  /* LDO10_STS */
176 #define WM831X_LDO10_STS_SHIFT                       9  /* LDO10_STS */
177 #define WM831X_LDO10_STS_WIDTH                       1  /* LDO10_STS */
178 #define WM831X_LDO9_STS                         0x0100  /* LDO9_STS */
179 #define WM831X_LDO9_STS_MASK                    0x0100  /* LDO9_STS */
180 #define WM831X_LDO9_STS_SHIFT                        8  /* LDO9_STS */
181 #define WM831X_LDO9_STS_WIDTH                        1  /* LDO9_STS */
182 #define WM831X_LDO8_STS                         0x0080  /* LDO8_STS */
183 #define WM831X_LDO8_STS_MASK                    0x0080  /* LDO8_STS */
184 #define WM831X_LDO8_STS_SHIFT                        7  /* LDO8_STS */
185 #define WM831X_LDO8_STS_WIDTH                        1  /* LDO8_STS */
186 #define WM831X_LDO7_STS                         0x0040  /* LDO7_STS */
187 #define WM831X_LDO7_STS_MASK                    0x0040  /* LDO7_STS */
188 #define WM831X_LDO7_STS_SHIFT                        6  /* LDO7_STS */
189 #define WM831X_LDO7_STS_WIDTH                        1  /* LDO7_STS */
190 #define WM831X_LDO6_STS                         0x0020  /* LDO6_STS */
191 #define WM831X_LDO6_STS_MASK                    0x0020  /* LDO6_STS */
192 #define WM831X_LDO6_STS_SHIFT                        5  /* LDO6_STS */
193 #define WM831X_LDO6_STS_WIDTH                        1  /* LDO6_STS */
194 #define WM831X_LDO5_STS                         0x0010  /* LDO5_STS */
195 #define WM831X_LDO5_STS_MASK                    0x0010  /* LDO5_STS */
196 #define WM831X_LDO5_STS_SHIFT                        4  /* LDO5_STS */
197 #define WM831X_LDO5_STS_WIDTH                        1  /* LDO5_STS */
198 #define WM831X_LDO4_STS                         0x0008  /* LDO4_STS */
199 #define WM831X_LDO4_STS_MASK                    0x0008  /* LDO4_STS */
200 #define WM831X_LDO4_STS_SHIFT                        3  /* LDO4_STS */
201 #define WM831X_LDO4_STS_WIDTH                        1  /* LDO4_STS */
202 #define WM831X_LDO3_STS                         0x0004  /* LDO3_STS */
203 #define WM831X_LDO3_STS_MASK                    0x0004  /* LDO3_STS */
204 #define WM831X_LDO3_STS_SHIFT                        2  /* LDO3_STS */
205 #define WM831X_LDO3_STS_WIDTH                        1  /* LDO3_STS */
206 #define WM831X_LDO2_STS                         0x0002  /* LDO2_STS */
207 #define WM831X_LDO2_STS_MASK                    0x0002  /* LDO2_STS */
208 #define WM831X_LDO2_STS_SHIFT                        1  /* LDO2_STS */
209 #define WM831X_LDO2_STS_WIDTH                        1  /* LDO2_STS */
210 #define WM831X_LDO1_STS                         0x0001  /* LDO1_STS */
211 #define WM831X_LDO1_STS_MASK                    0x0001  /* LDO1_STS */
212 #define WM831X_LDO1_STS_SHIFT                        0  /* LDO1_STS */
213 #define WM831X_LDO1_STS_WIDTH                        1  /* LDO1_STS */
214 
215 /*
216  * R16468 (0x4054) - DCDC UV Status
217  */
218 #define WM831X_DC2_OV_STS                       0x2000  /* DC2_OV_STS */
219 #define WM831X_DC2_OV_STS_MASK                  0x2000  /* DC2_OV_STS */
220 #define WM831X_DC2_OV_STS_SHIFT                     13  /* DC2_OV_STS */
221 #define WM831X_DC2_OV_STS_WIDTH                      1  /* DC2_OV_STS */
222 #define WM831X_DC1_OV_STS                       0x1000  /* DC1_OV_STS */
223 #define WM831X_DC1_OV_STS_MASK                  0x1000  /* DC1_OV_STS */
224 #define WM831X_DC1_OV_STS_SHIFT                     12  /* DC1_OV_STS */
225 #define WM831X_DC1_OV_STS_WIDTH                      1  /* DC1_OV_STS */
226 #define WM831X_DC2_HC_STS                       0x0200  /* DC2_HC_STS */
227 #define WM831X_DC2_HC_STS_MASK                  0x0200  /* DC2_HC_STS */
228 #define WM831X_DC2_HC_STS_SHIFT                      9  /* DC2_HC_STS */
229 #define WM831X_DC2_HC_STS_WIDTH                      1  /* DC2_HC_STS */
230 #define WM831X_DC1_HC_STS                       0x0100  /* DC1_HC_STS */
231 #define WM831X_DC1_HC_STS_MASK                  0x0100  /* DC1_HC_STS */
232 #define WM831X_DC1_HC_STS_SHIFT                      8  /* DC1_HC_STS */
233 #define WM831X_DC1_HC_STS_WIDTH                      1  /* DC1_HC_STS */
234 #define WM831X_DC4_UV_STS                       0x0008  /* DC4_UV_STS */
235 #define WM831X_DC4_UV_STS_MASK                  0x0008  /* DC4_UV_STS */
236 #define WM831X_DC4_UV_STS_SHIFT                      3  /* DC4_UV_STS */
237 #define WM831X_DC4_UV_STS_WIDTH                      1  /* DC4_UV_STS */
238 #define WM831X_DC3_UV_STS                       0x0004  /* DC3_UV_STS */
239 #define WM831X_DC3_UV_STS_MASK                  0x0004  /* DC3_UV_STS */
240 #define WM831X_DC3_UV_STS_SHIFT                      2  /* DC3_UV_STS */
241 #define WM831X_DC3_UV_STS_WIDTH                      1  /* DC3_UV_STS */
242 #define WM831X_DC2_UV_STS                       0x0002  /* DC2_UV_STS */
243 #define WM831X_DC2_UV_STS_MASK                  0x0002  /* DC2_UV_STS */
244 #define WM831X_DC2_UV_STS_SHIFT                      1  /* DC2_UV_STS */
245 #define WM831X_DC2_UV_STS_WIDTH                      1  /* DC2_UV_STS */
246 #define WM831X_DC1_UV_STS                       0x0001  /* DC1_UV_STS */
247 #define WM831X_DC1_UV_STS_MASK                  0x0001  /* DC1_UV_STS */
248 #define WM831X_DC1_UV_STS_SHIFT                      0  /* DC1_UV_STS */
249 #define WM831X_DC1_UV_STS_WIDTH                      1  /* DC1_UV_STS */
250 
251 /*
252  * R16469 (0x4055) - LDO UV Status
253  */
254 #define WM831X_INTLDO_UV_STS                    0x8000  /* INTLDO_UV_STS */
255 #define WM831X_INTLDO_UV_STS_MASK               0x8000  /* INTLDO_UV_STS */
256 #define WM831X_INTLDO_UV_STS_SHIFT                  15  /* INTLDO_UV_STS */
257 #define WM831X_INTLDO_UV_STS_WIDTH                   1  /* INTLDO_UV_STS */
258 #define WM831X_LDO10_UV_STS                     0x0200  /* LDO10_UV_STS */
259 #define WM831X_LDO10_UV_STS_MASK                0x0200  /* LDO10_UV_STS */
260 #define WM831X_LDO10_UV_STS_SHIFT                    9  /* LDO10_UV_STS */
261 #define WM831X_LDO10_UV_STS_WIDTH                    1  /* LDO10_UV_STS */
262 #define WM831X_LDO9_UV_STS                      0x0100  /* LDO9_UV_STS */
263 #define WM831X_LDO9_UV_STS_MASK                 0x0100  /* LDO9_UV_STS */
264 #define WM831X_LDO9_UV_STS_SHIFT                     8  /* LDO9_UV_STS */
265 #define WM831X_LDO9_UV_STS_WIDTH                     1  /* LDO9_UV_STS */
266 #define WM831X_LDO8_UV_STS                      0x0080  /* LDO8_UV_STS */
267 #define WM831X_LDO8_UV_STS_MASK                 0x0080  /* LDO8_UV_STS */
268 #define WM831X_LDO8_UV_STS_SHIFT                     7  /* LDO8_UV_STS */
269 #define WM831X_LDO8_UV_STS_WIDTH                     1  /* LDO8_UV_STS */
270 #define WM831X_LDO7_UV_STS                      0x0040  /* LDO7_UV_STS */
271 #define WM831X_LDO7_UV_STS_MASK                 0x0040  /* LDO7_UV_STS */
272 #define WM831X_LDO7_UV_STS_SHIFT                     6  /* LDO7_UV_STS */
273 #define WM831X_LDO7_UV_STS_WIDTH                     1  /* LDO7_UV_STS */
274 #define WM831X_LDO6_UV_STS                      0x0020  /* LDO6_UV_STS */
275 #define WM831X_LDO6_UV_STS_MASK                 0x0020  /* LDO6_UV_STS */
276 #define WM831X_LDO6_UV_STS_SHIFT                     5  /* LDO6_UV_STS */
277 #define WM831X_LDO6_UV_STS_WIDTH                     1  /* LDO6_UV_STS */
278 #define WM831X_LDO5_UV_STS                      0x0010  /* LDO5_UV_STS */
279 #define WM831X_LDO5_UV_STS_MASK                 0x0010  /* LDO5_UV_STS */
280 #define WM831X_LDO5_UV_STS_SHIFT                     4  /* LDO5_UV_STS */
281 #define WM831X_LDO5_UV_STS_WIDTH                     1  /* LDO5_UV_STS */
282 #define WM831X_LDO4_UV_STS                      0x0008  /* LDO4_UV_STS */
283 #define WM831X_LDO4_UV_STS_MASK                 0x0008  /* LDO4_UV_STS */
284 #define WM831X_LDO4_UV_STS_SHIFT                     3  /* LDO4_UV_STS */
285 #define WM831X_LDO4_UV_STS_WIDTH                     1  /* LDO4_UV_STS */
286 #define WM831X_LDO3_UV_STS                      0x0004  /* LDO3_UV_STS */
287 #define WM831X_LDO3_UV_STS_MASK                 0x0004  /* LDO3_UV_STS */
288 #define WM831X_LDO3_UV_STS_SHIFT                     2  /* LDO3_UV_STS */
289 #define WM831X_LDO3_UV_STS_WIDTH                     1  /* LDO3_UV_STS */
290 #define WM831X_LDO2_UV_STS                      0x0002  /* LDO2_UV_STS */
291 #define WM831X_LDO2_UV_STS_MASK                 0x0002  /* LDO2_UV_STS */
292 #define WM831X_LDO2_UV_STS_SHIFT                     1  /* LDO2_UV_STS */
293 #define WM831X_LDO2_UV_STS_WIDTH                     1  /* LDO2_UV_STS */
294 #define WM831X_LDO1_UV_STS                      0x0001  /* LDO1_UV_STS */
295 #define WM831X_LDO1_UV_STS_MASK                 0x0001  /* LDO1_UV_STS */
296 #define WM831X_LDO1_UV_STS_SHIFT                     0  /* LDO1_UV_STS */
297 #define WM831X_LDO1_UV_STS_WIDTH                     1  /* LDO1_UV_STS */
298 
299 /*
300  * R16470 (0x4056) - DC1 Control 1
301  */
302 #define WM831X_DC1_RATE_MASK                    0xC000  /* DC1_RATE - [15:14] */
303 #define WM831X_DC1_RATE_SHIFT                       14  /* DC1_RATE - [15:14] */
304 #define WM831X_DC1_RATE_WIDTH                        2  /* DC1_RATE - [15:14] */
305 #define WM831X_DC1_PHASE                        0x1000  /* DC1_PHASE */
306 #define WM831X_DC1_PHASE_MASK                   0x1000  /* DC1_PHASE */
307 #define WM831X_DC1_PHASE_SHIFT                      12  /* DC1_PHASE */
308 #define WM831X_DC1_PHASE_WIDTH                       1  /* DC1_PHASE */
309 #define WM831X_DC1_FREQ_MASK                    0x0300  /* DC1_FREQ - [9:8] */
310 #define WM831X_DC1_FREQ_SHIFT                        8  /* DC1_FREQ - [9:8] */
311 #define WM831X_DC1_FREQ_WIDTH                        2  /* DC1_FREQ - [9:8] */
312 #define WM831X_DC1_FLT                          0x0080  /* DC1_FLT */
313 #define WM831X_DC1_FLT_MASK                     0x0080  /* DC1_FLT */
314 #define WM831X_DC1_FLT_SHIFT                         7  /* DC1_FLT */
315 #define WM831X_DC1_FLT_WIDTH                         1  /* DC1_FLT */
316 #define WM831X_DC1_SOFT_START_MASK              0x0030  /* DC1_SOFT_START - [5:4] */
317 #define WM831X_DC1_SOFT_START_SHIFT                  4  /* DC1_SOFT_START - [5:4] */
318 #define WM831X_DC1_SOFT_START_WIDTH                  2  /* DC1_SOFT_START - [5:4] */
319 #define WM831X_DC1_CAP_MASK                     0x0003  /* DC1_CAP - [1:0] */
320 #define WM831X_DC1_CAP_SHIFT                         0  /* DC1_CAP - [1:0] */
321 #define WM831X_DC1_CAP_WIDTH                         2  /* DC1_CAP - [1:0] */
322 
323 /*
324  * R16471 (0x4057) - DC1 Control 2
325  */
326 #define WM831X_DC1_ERR_ACT_MASK                 0xC000  /* DC1_ERR_ACT - [15:14] */
327 #define WM831X_DC1_ERR_ACT_SHIFT                    14  /* DC1_ERR_ACT - [15:14] */
328 #define WM831X_DC1_ERR_ACT_WIDTH                     2  /* DC1_ERR_ACT - [15:14] */
329 #define WM831X_DC1_HWC_SRC_MASK                 0x1800  /* DC1_HWC_SRC - [12:11] */
330 #define WM831X_DC1_HWC_SRC_SHIFT                    11  /* DC1_HWC_SRC - [12:11] */
331 #define WM831X_DC1_HWC_SRC_WIDTH                     2  /* DC1_HWC_SRC - [12:11] */
332 #define WM831X_DC1_HWC_VSEL                     0x0400  /* DC1_HWC_VSEL */
333 #define WM831X_DC1_HWC_VSEL_MASK                0x0400  /* DC1_HWC_VSEL */
334 #define WM831X_DC1_HWC_VSEL_SHIFT                   10  /* DC1_HWC_VSEL */
335 #define WM831X_DC1_HWC_VSEL_WIDTH                    1  /* DC1_HWC_VSEL */
336 #define WM831X_DC1_HWC_MODE_MASK                0x0300  /* DC1_HWC_MODE - [9:8] */
337 #define WM831X_DC1_HWC_MODE_SHIFT                    8  /* DC1_HWC_MODE - [9:8] */
338 #define WM831X_DC1_HWC_MODE_WIDTH                    2  /* DC1_HWC_MODE - [9:8] */
339 #define WM831X_DC1_HC_THR_MASK                  0x0070  /* DC1_HC_THR - [6:4] */
340 #define WM831X_DC1_HC_THR_SHIFT                      4  /* DC1_HC_THR - [6:4] */
341 #define WM831X_DC1_HC_THR_WIDTH                      3  /* DC1_HC_THR - [6:4] */
342 #define WM831X_DC1_HC_IND_ENA                   0x0001  /* DC1_HC_IND_ENA */
343 #define WM831X_DC1_HC_IND_ENA_MASK              0x0001  /* DC1_HC_IND_ENA */
344 #define WM831X_DC1_HC_IND_ENA_SHIFT                  0  /* DC1_HC_IND_ENA */
345 #define WM831X_DC1_HC_IND_ENA_WIDTH                  1  /* DC1_HC_IND_ENA */
346 
347 /*
348  * R16472 (0x4058) - DC1 ON Config
349  */
350 #define WM831X_DC1_ON_SLOT_MASK                 0xE000  /* DC1_ON_SLOT - [15:13] */
351 #define WM831X_DC1_ON_SLOT_SHIFT                    13  /* DC1_ON_SLOT - [15:13] */
352 #define WM831X_DC1_ON_SLOT_WIDTH                     3  /* DC1_ON_SLOT - [15:13] */
353 #define WM831X_DC1_ON_MODE_MASK                 0x0300  /* DC1_ON_MODE - [9:8] */
354 #define WM831X_DC1_ON_MODE_SHIFT                     8  /* DC1_ON_MODE - [9:8] */
355 #define WM831X_DC1_ON_MODE_WIDTH                     2  /* DC1_ON_MODE - [9:8] */
356 #define WM831X_DC1_ON_VSEL_MASK                 0x007F  /* DC1_ON_VSEL - [6:0] */
357 #define WM831X_DC1_ON_VSEL_SHIFT                     0  /* DC1_ON_VSEL - [6:0] */
358 #define WM831X_DC1_ON_VSEL_WIDTH                     7  /* DC1_ON_VSEL - [6:0] */
359 
360 /*
361  * R16473 (0x4059) - DC1 SLEEP Control
362  */
363 #define WM831X_DC1_SLP_SLOT_MASK                0xE000  /* DC1_SLP_SLOT - [15:13] */
364 #define WM831X_DC1_SLP_SLOT_SHIFT                   13  /* DC1_SLP_SLOT - [15:13] */
365 #define WM831X_DC1_SLP_SLOT_WIDTH                    3  /* DC1_SLP_SLOT - [15:13] */
366 #define WM831X_DC1_SLP_MODE_MASK                0x0300  /* DC1_SLP_MODE - [9:8] */
367 #define WM831X_DC1_SLP_MODE_SHIFT                    8  /* DC1_SLP_MODE - [9:8] */
368 #define WM831X_DC1_SLP_MODE_WIDTH                    2  /* DC1_SLP_MODE - [9:8] */
369 #define WM831X_DC1_SLP_VSEL_MASK                0x007F  /* DC1_SLP_VSEL - [6:0] */
370 #define WM831X_DC1_SLP_VSEL_SHIFT                    0  /* DC1_SLP_VSEL - [6:0] */
371 #define WM831X_DC1_SLP_VSEL_WIDTH                    7  /* DC1_SLP_VSEL - [6:0] */
372 
373 /*
374  * R16474 (0x405A) - DC1 DVS Control
375  */
376 #define WM831X_DC1_DVS_SRC_MASK                 0x1800  /* DC1_DVS_SRC - [12:11] */
377 #define WM831X_DC1_DVS_SRC_SHIFT                    11  /* DC1_DVS_SRC - [12:11] */
378 #define WM831X_DC1_DVS_SRC_WIDTH                     2  /* DC1_DVS_SRC - [12:11] */
379 #define WM831X_DC1_DVS_VSEL_MASK                0x007F  /* DC1_DVS_VSEL - [6:0] */
380 #define WM831X_DC1_DVS_VSEL_SHIFT                    0  /* DC1_DVS_VSEL - [6:0] */
381 #define WM831X_DC1_DVS_VSEL_WIDTH                    7  /* DC1_DVS_VSEL - [6:0] */
382 
383 /*
384  * R16475 (0x405B) - DC2 Control 1
385  */
386 #define WM831X_DC2_RATE_MASK                    0xC000  /* DC2_RATE - [15:14] */
387 #define WM831X_DC2_RATE_SHIFT                       14  /* DC2_RATE - [15:14] */
388 #define WM831X_DC2_RATE_WIDTH                        2  /* DC2_RATE - [15:14] */
389 #define WM831X_DC2_PHASE                        0x1000  /* DC2_PHASE */
390 #define WM831X_DC2_PHASE_MASK                   0x1000  /* DC2_PHASE */
391 #define WM831X_DC2_PHASE_SHIFT                      12  /* DC2_PHASE */
392 #define WM831X_DC2_PHASE_WIDTH                       1  /* DC2_PHASE */
393 #define WM831X_DC2_FREQ_MASK                    0x0300  /* DC2_FREQ - [9:8] */
394 #define WM831X_DC2_FREQ_SHIFT                        8  /* DC2_FREQ - [9:8] */
395 #define WM831X_DC2_FREQ_WIDTH                        2  /* DC2_FREQ - [9:8] */
396 #define WM831X_DC2_FLT                          0x0080  /* DC2_FLT */
397 #define WM831X_DC2_FLT_MASK                     0x0080  /* DC2_FLT */
398 #define WM831X_DC2_FLT_SHIFT                         7  /* DC2_FLT */
399 #define WM831X_DC2_FLT_WIDTH                         1  /* DC2_FLT */
400 #define WM831X_DC2_SOFT_START_MASK              0x0030  /* DC2_SOFT_START - [5:4] */
401 #define WM831X_DC2_SOFT_START_SHIFT                  4  /* DC2_SOFT_START - [5:4] */
402 #define WM831X_DC2_SOFT_START_WIDTH                  2  /* DC2_SOFT_START - [5:4] */
403 #define WM831X_DC2_CAP_MASK                     0x0003  /* DC2_CAP - [1:0] */
404 #define WM831X_DC2_CAP_SHIFT                         0  /* DC2_CAP - [1:0] */
405 #define WM831X_DC2_CAP_WIDTH                         2  /* DC2_CAP - [1:0] */
406 
407 /*
408  * R16476 (0x405C) - DC2 Control 2
409  */
410 #define WM831X_DC2_ERR_ACT_MASK                 0xC000  /* DC2_ERR_ACT - [15:14] */
411 #define WM831X_DC2_ERR_ACT_SHIFT                    14  /* DC2_ERR_ACT - [15:14] */
412 #define WM831X_DC2_ERR_ACT_WIDTH                     2  /* DC2_ERR_ACT - [15:14] */
413 #define WM831X_DC2_HWC_SRC_MASK                 0x1800  /* DC2_HWC_SRC - [12:11] */
414 #define WM831X_DC2_HWC_SRC_SHIFT                    11  /* DC2_HWC_SRC - [12:11] */
415 #define WM831X_DC2_HWC_SRC_WIDTH                     2  /* DC2_HWC_SRC - [12:11] */
416 #define WM831X_DC2_HWC_VSEL                     0x0400  /* DC2_HWC_VSEL */
417 #define WM831X_DC2_HWC_VSEL_MASK                0x0400  /* DC2_HWC_VSEL */
418 #define WM831X_DC2_HWC_VSEL_SHIFT                   10  /* DC2_HWC_VSEL */
419 #define WM831X_DC2_HWC_VSEL_WIDTH                    1  /* DC2_HWC_VSEL */
420 #define WM831X_DC2_HWC_MODE_MASK                0x0300  /* DC2_HWC_MODE - [9:8] */
421 #define WM831X_DC2_HWC_MODE_SHIFT                    8  /* DC2_HWC_MODE - [9:8] */
422 #define WM831X_DC2_HWC_MODE_WIDTH                    2  /* DC2_HWC_MODE - [9:8] */
423 #define WM831X_DC2_HC_THR_MASK                  0x0070  /* DC2_HC_THR - [6:4] */
424 #define WM831X_DC2_HC_THR_SHIFT                      4  /* DC2_HC_THR - [6:4] */
425 #define WM831X_DC2_HC_THR_WIDTH                      3  /* DC2_HC_THR - [6:4] */
426 #define WM831X_DC2_HC_IND_ENA                   0x0001  /* DC2_HC_IND_ENA */
427 #define WM831X_DC2_HC_IND_ENA_MASK              0x0001  /* DC2_HC_IND_ENA */
428 #define WM831X_DC2_HC_IND_ENA_SHIFT                  0  /* DC2_HC_IND_ENA */
429 #define WM831X_DC2_HC_IND_ENA_WIDTH                  1  /* DC2_HC_IND_ENA */
430 
431 /*
432  * R16477 (0x405D) - DC2 ON Config
433  */
434 #define WM831X_DC2_ON_SLOT_MASK                 0xE000  /* DC2_ON_SLOT - [15:13] */
435 #define WM831X_DC2_ON_SLOT_SHIFT                    13  /* DC2_ON_SLOT - [15:13] */
436 #define WM831X_DC2_ON_SLOT_WIDTH                     3  /* DC2_ON_SLOT - [15:13] */
437 #define WM831X_DC2_ON_MODE_MASK                 0x0300  /* DC2_ON_MODE - [9:8] */
438 #define WM831X_DC2_ON_MODE_SHIFT                     8  /* DC2_ON_MODE - [9:8] */
439 #define WM831X_DC2_ON_MODE_WIDTH                     2  /* DC2_ON_MODE - [9:8] */
440 #define WM831X_DC2_ON_VSEL_MASK                 0x007F  /* DC2_ON_VSEL - [6:0] */
441 #define WM831X_DC2_ON_VSEL_SHIFT                     0  /* DC2_ON_VSEL - [6:0] */
442 #define WM831X_DC2_ON_VSEL_WIDTH                     7  /* DC2_ON_VSEL - [6:0] */
443 
444 /*
445  * R16478 (0x405E) - DC2 SLEEP Control
446  */
447 #define WM831X_DC2_SLP_SLOT_MASK                0xE000  /* DC2_SLP_SLOT - [15:13] */
448 #define WM831X_DC2_SLP_SLOT_SHIFT                   13  /* DC2_SLP_SLOT - [15:13] */
449 #define WM831X_DC2_SLP_SLOT_WIDTH                    3  /* DC2_SLP_SLOT - [15:13] */
450 #define WM831X_DC2_SLP_MODE_MASK                0x0300  /* DC2_SLP_MODE - [9:8] */
451 #define WM831X_DC2_SLP_MODE_SHIFT                    8  /* DC2_SLP_MODE - [9:8] */
452 #define WM831X_DC2_SLP_MODE_WIDTH                    2  /* DC2_SLP_MODE - [9:8] */
453 #define WM831X_DC2_SLP_VSEL_MASK                0x007F  /* DC2_SLP_VSEL - [6:0] */
454 #define WM831X_DC2_SLP_VSEL_SHIFT                    0  /* DC2_SLP_VSEL - [6:0] */
455 #define WM831X_DC2_SLP_VSEL_WIDTH                    7  /* DC2_SLP_VSEL - [6:0] */
456 
457 /*
458  * R16479 (0x405F) - DC2 DVS Control
459  */
460 #define WM831X_DC2_DVS_SRC_MASK                 0x1800  /* DC2_DVS_SRC - [12:11] */
461 #define WM831X_DC2_DVS_SRC_SHIFT                    11  /* DC2_DVS_SRC - [12:11] */
462 #define WM831X_DC2_DVS_SRC_WIDTH                     2  /* DC2_DVS_SRC - [12:11] */
463 #define WM831X_DC2_DVS_VSEL_MASK                0x007F  /* DC2_DVS_VSEL - [6:0] */
464 #define WM831X_DC2_DVS_VSEL_SHIFT                    0  /* DC2_DVS_VSEL - [6:0] */
465 #define WM831X_DC2_DVS_VSEL_WIDTH                    7  /* DC2_DVS_VSEL - [6:0] */
466 
467 /*
468  * R16480 (0x4060) - DC3 Control 1
469  */
470 #define WM831X_DC3_PHASE                        0x1000  /* DC3_PHASE */
471 #define WM831X_DC3_PHASE_MASK                   0x1000  /* DC3_PHASE */
472 #define WM831X_DC3_PHASE_SHIFT                      12  /* DC3_PHASE */
473 #define WM831X_DC3_PHASE_WIDTH                       1  /* DC3_PHASE */
474 #define WM831X_DC3_FLT                          0x0080  /* DC3_FLT */
475 #define WM831X_DC3_FLT_MASK                     0x0080  /* DC3_FLT */
476 #define WM831X_DC3_FLT_SHIFT                         7  /* DC3_FLT */
477 #define WM831X_DC3_FLT_WIDTH                         1  /* DC3_FLT */
478 #define WM831X_DC3_SOFT_START_MASK              0x0030  /* DC3_SOFT_START - [5:4] */
479 #define WM831X_DC3_SOFT_START_SHIFT                  4  /* DC3_SOFT_START - [5:4] */
480 #define WM831X_DC3_SOFT_START_WIDTH                  2  /* DC3_SOFT_START - [5:4] */
481 #define WM831X_DC3_STNBY_LIM_MASK               0x000C  /* DC3_STNBY_LIM - [3:2] */
482 #define WM831X_DC3_STNBY_LIM_SHIFT                   2  /* DC3_STNBY_LIM - [3:2] */
483 #define WM831X_DC3_STNBY_LIM_WIDTH                   2  /* DC3_STNBY_LIM - [3:2] */
484 #define WM831X_DC3_CAP_MASK                     0x0003  /* DC3_CAP - [1:0] */
485 #define WM831X_DC3_CAP_SHIFT                         0  /* DC3_CAP - [1:0] */
486 #define WM831X_DC3_CAP_WIDTH                         2  /* DC3_CAP - [1:0] */
487 
488 /*
489  * R16481 (0x4061) - DC3 Control 2
490  */
491 #define WM831X_DC3_ERR_ACT_MASK                 0xC000  /* DC3_ERR_ACT - [15:14] */
492 #define WM831X_DC3_ERR_ACT_SHIFT                    14  /* DC3_ERR_ACT - [15:14] */
493 #define WM831X_DC3_ERR_ACT_WIDTH                     2  /* DC3_ERR_ACT - [15:14] */
494 #define WM831X_DC3_HWC_SRC_MASK                 0x1800  /* DC3_HWC_SRC - [12:11] */
495 #define WM831X_DC3_HWC_SRC_SHIFT                    11  /* DC3_HWC_SRC - [12:11] */
496 #define WM831X_DC3_HWC_SRC_WIDTH                     2  /* DC3_HWC_SRC - [12:11] */
497 #define WM831X_DC3_HWC_VSEL                     0x0400  /* DC3_HWC_VSEL */
498 #define WM831X_DC3_HWC_VSEL_MASK                0x0400  /* DC3_HWC_VSEL */
499 #define WM831X_DC3_HWC_VSEL_SHIFT                   10  /* DC3_HWC_VSEL */
500 #define WM831X_DC3_HWC_VSEL_WIDTH                    1  /* DC3_HWC_VSEL */
501 #define WM831X_DC3_HWC_MODE_MASK                0x0300  /* DC3_HWC_MODE - [9:8] */
502 #define WM831X_DC3_HWC_MODE_SHIFT                    8  /* DC3_HWC_MODE - [9:8] */
503 #define WM831X_DC3_HWC_MODE_WIDTH                    2  /* DC3_HWC_MODE - [9:8] */
504 #define WM831X_DC3_OVP                          0x0080  /* DC3_OVP */
505 #define WM831X_DC3_OVP_MASK                     0x0080  /* DC3_OVP */
506 #define WM831X_DC3_OVP_SHIFT                         7  /* DC3_OVP */
507 #define WM831X_DC3_OVP_WIDTH                         1  /* DC3_OVP */
508 
509 /*
510  * R16482 (0x4062) - DC3 ON Config
511  */
512 #define WM831X_DC3_ON_SLOT_MASK                 0xE000  /* DC3_ON_SLOT - [15:13] */
513 #define WM831X_DC3_ON_SLOT_SHIFT                    13  /* DC3_ON_SLOT - [15:13] */
514 #define WM831X_DC3_ON_SLOT_WIDTH                     3  /* DC3_ON_SLOT - [15:13] */
515 #define WM831X_DC3_ON_MODE_MASK                 0x0300  /* DC3_ON_MODE - [9:8] */
516 #define WM831X_DC3_ON_MODE_SHIFT                     8  /* DC3_ON_MODE - [9:8] */
517 #define WM831X_DC3_ON_MODE_WIDTH                     2  /* DC3_ON_MODE - [9:8] */
518 #define WM831X_DC3_ON_VSEL_MASK                 0x007F  /* DC3_ON_VSEL - [6:0] */
519 #define WM831X_DC3_ON_VSEL_SHIFT                     0  /* DC3_ON_VSEL - [6:0] */
520 #define WM831X_DC3_ON_VSEL_WIDTH                     7  /* DC3_ON_VSEL - [6:0] */
521 
522 /*
523  * R16483 (0x4063) - DC3 SLEEP Control
524  */
525 #define WM831X_DC3_SLP_SLOT_MASK                0xE000  /* DC3_SLP_SLOT - [15:13] */
526 #define WM831X_DC3_SLP_SLOT_SHIFT                   13  /* DC3_SLP_SLOT - [15:13] */
527 #define WM831X_DC3_SLP_SLOT_WIDTH                    3  /* DC3_SLP_SLOT - [15:13] */
528 #define WM831X_DC3_SLP_MODE_MASK                0x0300  /* DC3_SLP_MODE - [9:8] */
529 #define WM831X_DC3_SLP_MODE_SHIFT                    8  /* DC3_SLP_MODE - [9:8] */
530 #define WM831X_DC3_SLP_MODE_WIDTH                    2  /* DC3_SLP_MODE - [9:8] */
531 #define WM831X_DC3_SLP_VSEL_MASK                0x007F  /* DC3_SLP_VSEL - [6:0] */
532 #define WM831X_DC3_SLP_VSEL_SHIFT                    0  /* DC3_SLP_VSEL - [6:0] */
533 #define WM831X_DC3_SLP_VSEL_WIDTH                    7  /* DC3_SLP_VSEL - [6:0] */
534 
535 /*
536  * R16484 (0x4064) - DC4 Control
537  */
538 #define WM831X_DC4_ERR_ACT_MASK                 0xC000  /* DC4_ERR_ACT - [15:14] */
539 #define WM831X_DC4_ERR_ACT_SHIFT                    14  /* DC4_ERR_ACT - [15:14] */
540 #define WM831X_DC4_ERR_ACT_WIDTH                     2  /* DC4_ERR_ACT - [15:14] */
541 #define WM831X_DC4_HWC_SRC_MASK                 0x1800  /* DC4_HWC_SRC - [12:11] */
542 #define WM831X_DC4_HWC_SRC_SHIFT                    11  /* DC4_HWC_SRC - [12:11] */
543 #define WM831X_DC4_HWC_SRC_WIDTH                     2  /* DC4_HWC_SRC - [12:11] */
544 #define WM831X_DC4_HWC_MODE                     0x0100  /* DC4_HWC_MODE */
545 #define WM831X_DC4_HWC_MODE_MASK                0x0100  /* DC4_HWC_MODE */
546 #define WM831X_DC4_HWC_MODE_SHIFT                    8  /* DC4_HWC_MODE */
547 #define WM831X_DC4_HWC_MODE_WIDTH                    1  /* DC4_HWC_MODE */
548 #define WM831X_DC4_RANGE_MASK                   0x000C  /* DC4_RANGE - [3:2] */
549 #define WM831X_DC4_RANGE_SHIFT                       2  /* DC4_RANGE - [3:2] */
550 #define WM831X_DC4_RANGE_WIDTH                       2  /* DC4_RANGE - [3:2] */
551 #define WM831X_DC4_FBSRC                        0x0001  /* DC4_FBSRC */
552 #define WM831X_DC4_FBSRC_MASK                   0x0001  /* DC4_FBSRC */
553 #define WM831X_DC4_FBSRC_SHIFT                       0  /* DC4_FBSRC */
554 #define WM831X_DC4_FBSRC_WIDTH                       1  /* DC4_FBSRC */
555 
556 /*
557  * R16485 (0x4065) - DC4 SLEEP Control
558  */
559 #define WM831X_DC4_SLPENA                       0x0100  /* DC4_SLPENA */
560 #define WM831X_DC4_SLPENA_MASK                  0x0100  /* DC4_SLPENA */
561 #define WM831X_DC4_SLPENA_SHIFT                      8  /* DC4_SLPENA */
562 #define WM831X_DC4_SLPENA_WIDTH                      1  /* DC4_SLPENA */
563 
564 /*
565  * R16488 (0x4068) - LDO1 Control
566  */
567 #define WM831X_LDO1_ERR_ACT_MASK                0xC000  /* LDO1_ERR_ACT - [15:14] */
568 #define WM831X_LDO1_ERR_ACT_SHIFT                   14  /* LDO1_ERR_ACT - [15:14] */
569 #define WM831X_LDO1_ERR_ACT_WIDTH                    2  /* LDO1_ERR_ACT - [15:14] */
570 #define WM831X_LDO1_HWC_SRC_MASK                0x1800  /* LDO1_HWC_SRC - [12:11] */
571 #define WM831X_LDO1_HWC_SRC_SHIFT                   11  /* LDO1_HWC_SRC - [12:11] */
572 #define WM831X_LDO1_HWC_SRC_WIDTH                    2  /* LDO1_HWC_SRC - [12:11] */
573 #define WM831X_LDO1_HWC_VSEL                    0x0400  /* LDO1_HWC_VSEL */
574 #define WM831X_LDO1_HWC_VSEL_MASK               0x0400  /* LDO1_HWC_VSEL */
575 #define WM831X_LDO1_HWC_VSEL_SHIFT                  10  /* LDO1_HWC_VSEL */
576 #define WM831X_LDO1_HWC_VSEL_WIDTH                   1  /* LDO1_HWC_VSEL */
577 #define WM831X_LDO1_HWC_MODE_MASK               0x0300  /* LDO1_HWC_MODE - [9:8] */
578 #define WM831X_LDO1_HWC_MODE_SHIFT                   8  /* LDO1_HWC_MODE - [9:8] */
579 #define WM831X_LDO1_HWC_MODE_WIDTH                   2  /* LDO1_HWC_MODE - [9:8] */
580 #define WM831X_LDO1_FLT                         0x0080  /* LDO1_FLT */
581 #define WM831X_LDO1_FLT_MASK                    0x0080  /* LDO1_FLT */
582 #define WM831X_LDO1_FLT_SHIFT                        7  /* LDO1_FLT */
583 #define WM831X_LDO1_FLT_WIDTH                        1  /* LDO1_FLT */
584 #define WM831X_LDO1_SWI                         0x0040  /* LDO1_SWI */
585 #define WM831X_LDO1_SWI_MASK                    0x0040  /* LDO1_SWI */
586 #define WM831X_LDO1_SWI_SHIFT                        6  /* LDO1_SWI */
587 #define WM831X_LDO1_SWI_WIDTH                        1  /* LDO1_SWI */
588 #define WM831X_LDO1_LP_MODE                     0x0001  /* LDO1_LP_MODE */
589 #define WM831X_LDO1_LP_MODE_MASK                0x0001  /* LDO1_LP_MODE */
590 #define WM831X_LDO1_LP_MODE_SHIFT                    0  /* LDO1_LP_MODE */
591 #define WM831X_LDO1_LP_MODE_WIDTH                    1  /* LDO1_LP_MODE */
592 
593 /*
594  * R16489 (0x4069) - LDO1 ON Control
595  */
596 #define WM831X_LDO1_ON_SLOT_MASK                0xE000  /* LDO1_ON_SLOT - [15:13] */
597 #define WM831X_LDO1_ON_SLOT_SHIFT                   13  /* LDO1_ON_SLOT - [15:13] */
598 #define WM831X_LDO1_ON_SLOT_WIDTH                    3  /* LDO1_ON_SLOT - [15:13] */
599 #define WM831X_LDO1_ON_MODE                     0x0100  /* LDO1_ON_MODE */
600 #define WM831X_LDO1_ON_MODE_MASK                0x0100  /* LDO1_ON_MODE */
601 #define WM831X_LDO1_ON_MODE_SHIFT                    8  /* LDO1_ON_MODE */
602 #define WM831X_LDO1_ON_MODE_WIDTH                    1  /* LDO1_ON_MODE */
603 #define WM831X_LDO1_ON_VSEL_MASK                0x001F  /* LDO1_ON_VSEL - [4:0] */
604 #define WM831X_LDO1_ON_VSEL_SHIFT                    0  /* LDO1_ON_VSEL - [4:0] */
605 #define WM831X_LDO1_ON_VSEL_WIDTH                    5  /* LDO1_ON_VSEL - [4:0] */
606 
607 /*
608  * R16490 (0x406A) - LDO1 SLEEP Control
609  */
610 #define WM831X_LDO1_SLP_SLOT_MASK               0xE000  /* LDO1_SLP_SLOT - [15:13] */
611 #define WM831X_LDO1_SLP_SLOT_SHIFT                  13  /* LDO1_SLP_SLOT - [15:13] */
612 #define WM831X_LDO1_SLP_SLOT_WIDTH                   3  /* LDO1_SLP_SLOT - [15:13] */
613 #define WM831X_LDO1_SLP_MODE                    0x0100  /* LDO1_SLP_MODE */
614 #define WM831X_LDO1_SLP_MODE_MASK               0x0100  /* LDO1_SLP_MODE */
615 #define WM831X_LDO1_SLP_MODE_SHIFT                   8  /* LDO1_SLP_MODE */
616 #define WM831X_LDO1_SLP_MODE_WIDTH                   1  /* LDO1_SLP_MODE */
617 #define WM831X_LDO1_SLP_VSEL_MASK               0x001F  /* LDO1_SLP_VSEL - [4:0] */
618 #define WM831X_LDO1_SLP_VSEL_SHIFT                   0  /* LDO1_SLP_VSEL - [4:0] */
619 #define WM831X_LDO1_SLP_VSEL_WIDTH                   5  /* LDO1_SLP_VSEL - [4:0] */
620 
621 /*
622  * R16491 (0x406B) - LDO2 Control
623  */
624 #define WM831X_LDO2_ERR_ACT_MASK                0xC000  /* LDO2_ERR_ACT - [15:14] */
625 #define WM831X_LDO2_ERR_ACT_SHIFT                   14  /* LDO2_ERR_ACT - [15:14] */
626 #define WM831X_LDO2_ERR_ACT_WIDTH                    2  /* LDO2_ERR_ACT - [15:14] */
627 #define WM831X_LDO2_HWC_SRC_MASK                0x1800  /* LDO2_HWC_SRC - [12:11] */
628 #define WM831X_LDO2_HWC_SRC_SHIFT                   11  /* LDO2_HWC_SRC - [12:11] */
629 #define WM831X_LDO2_HWC_SRC_WIDTH                    2  /* LDO2_HWC_SRC - [12:11] */
630 #define WM831X_LDO2_HWC_VSEL                    0x0400  /* LDO2_HWC_VSEL */
631 #define WM831X_LDO2_HWC_VSEL_MASK               0x0400  /* LDO2_HWC_VSEL */
632 #define WM831X_LDO2_HWC_VSEL_SHIFT                  10  /* LDO2_HWC_VSEL */
633 #define WM831X_LDO2_HWC_VSEL_WIDTH                   1  /* LDO2_HWC_VSEL */
634 #define WM831X_LDO2_HWC_MODE_MASK               0x0300  /* LDO2_HWC_MODE - [9:8] */
635 #define WM831X_LDO2_HWC_MODE_SHIFT                   8  /* LDO2_HWC_MODE - [9:8] */
636 #define WM831X_LDO2_HWC_MODE_WIDTH                   2  /* LDO2_HWC_MODE - [9:8] */
637 #define WM831X_LDO2_FLT                         0x0080  /* LDO2_FLT */
638 #define WM831X_LDO2_FLT_MASK                    0x0080  /* LDO2_FLT */
639 #define WM831X_LDO2_FLT_SHIFT                        7  /* LDO2_FLT */
640 #define WM831X_LDO2_FLT_WIDTH                        1  /* LDO2_FLT */
641 #define WM831X_LDO2_SWI                         0x0040  /* LDO2_SWI */
642 #define WM831X_LDO2_SWI_MASK                    0x0040  /* LDO2_SWI */
643 #define WM831X_LDO2_SWI_SHIFT                        6  /* LDO2_SWI */
644 #define WM831X_LDO2_SWI_WIDTH                        1  /* LDO2_SWI */
645 #define WM831X_LDO2_LP_MODE                     0x0001  /* LDO2_LP_MODE */
646 #define WM831X_LDO2_LP_MODE_MASK                0x0001  /* LDO2_LP_MODE */
647 #define WM831X_LDO2_LP_MODE_SHIFT                    0  /* LDO2_LP_MODE */
648 #define WM831X_LDO2_LP_MODE_WIDTH                    1  /* LDO2_LP_MODE */
649 
650 /*
651  * R16492 (0x406C) - LDO2 ON Control
652  */
653 #define WM831X_LDO2_ON_SLOT_MASK                0xE000  /* LDO2_ON_SLOT - [15:13] */
654 #define WM831X_LDO2_ON_SLOT_SHIFT                   13  /* LDO2_ON_SLOT - [15:13] */
655 #define WM831X_LDO2_ON_SLOT_WIDTH                    3  /* LDO2_ON_SLOT - [15:13] */
656 #define WM831X_LDO2_ON_MODE                     0x0100  /* LDO2_ON_MODE */
657 #define WM831X_LDO2_ON_MODE_MASK                0x0100  /* LDO2_ON_MODE */
658 #define WM831X_LDO2_ON_MODE_SHIFT                    8  /* LDO2_ON_MODE */
659 #define WM831X_LDO2_ON_MODE_WIDTH                    1  /* LDO2_ON_MODE */
660 #define WM831X_LDO2_ON_VSEL_MASK                0x001F  /* LDO2_ON_VSEL - [4:0] */
661 #define WM831X_LDO2_ON_VSEL_SHIFT                    0  /* LDO2_ON_VSEL - [4:0] */
662 #define WM831X_LDO2_ON_VSEL_WIDTH                    5  /* LDO2_ON_VSEL - [4:0] */
663 
664 /*
665  * R16493 (0x406D) - LDO2 SLEEP Control
666  */
667 #define WM831X_LDO2_SLP_SLOT_MASK               0xE000  /* LDO2_SLP_SLOT - [15:13] */
668 #define WM831X_LDO2_SLP_SLOT_SHIFT                  13  /* LDO2_SLP_SLOT - [15:13] */
669 #define WM831X_LDO2_SLP_SLOT_WIDTH                   3  /* LDO2_SLP_SLOT - [15:13] */
670 #define WM831X_LDO2_SLP_MODE                    0x0100  /* LDO2_SLP_MODE */
671 #define WM831X_LDO2_SLP_MODE_MASK               0x0100  /* LDO2_SLP_MODE */
672 #define WM831X_LDO2_SLP_MODE_SHIFT                   8  /* LDO2_SLP_MODE */
673 #define WM831X_LDO2_SLP_MODE_WIDTH                   1  /* LDO2_SLP_MODE */
674 #define WM831X_LDO2_SLP_VSEL_MASK               0x001F  /* LDO2_SLP_VSEL - [4:0] */
675 #define WM831X_LDO2_SLP_VSEL_SHIFT                   0  /* LDO2_SLP_VSEL - [4:0] */
676 #define WM831X_LDO2_SLP_VSEL_WIDTH                   5  /* LDO2_SLP_VSEL - [4:0] */
677 
678 /*
679  * R16494 (0x406E) - LDO3 Control
680  */
681 #define WM831X_LDO3_ERR_ACT_MASK                0xC000  /* LDO3_ERR_ACT - [15:14] */
682 #define WM831X_LDO3_ERR_ACT_SHIFT                   14  /* LDO3_ERR_ACT - [15:14] */
683 #define WM831X_LDO3_ERR_ACT_WIDTH                    2  /* LDO3_ERR_ACT - [15:14] */
684 #define WM831X_LDO3_HWC_SRC_MASK                0x1800  /* LDO3_HWC_SRC - [12:11] */
685 #define WM831X_LDO3_HWC_SRC_SHIFT                   11  /* LDO3_HWC_SRC - [12:11] */
686 #define WM831X_LDO3_HWC_SRC_WIDTH                    2  /* LDO3_HWC_SRC - [12:11] */
687 #define WM831X_LDO3_HWC_VSEL                    0x0400  /* LDO3_HWC_VSEL */
688 #define WM831X_LDO3_HWC_VSEL_MASK               0x0400  /* LDO3_HWC_VSEL */
689 #define WM831X_LDO3_HWC_VSEL_SHIFT                  10  /* LDO3_HWC_VSEL */
690 #define WM831X_LDO3_HWC_VSEL_WIDTH                   1  /* LDO3_HWC_VSEL */
691 #define WM831X_LDO3_HWC_MODE_MASK               0x0300  /* LDO3_HWC_MODE - [9:8] */
692 #define WM831X_LDO3_HWC_MODE_SHIFT                   8  /* LDO3_HWC_MODE - [9:8] */
693 #define WM831X_LDO3_HWC_MODE_WIDTH                   2  /* LDO3_HWC_MODE - [9:8] */
694 #define WM831X_LDO3_FLT                         0x0080  /* LDO3_FLT */
695 #define WM831X_LDO3_FLT_MASK                    0x0080  /* LDO3_FLT */
696 #define WM831X_LDO3_FLT_SHIFT                        7  /* LDO3_FLT */
697 #define WM831X_LDO3_FLT_WIDTH                        1  /* LDO3_FLT */
698 #define WM831X_LDO3_SWI                         0x0040  /* LDO3_SWI */
699 #define WM831X_LDO3_SWI_MASK                    0x0040  /* LDO3_SWI */
700 #define WM831X_LDO3_SWI_SHIFT                        6  /* LDO3_SWI */
701 #define WM831X_LDO3_SWI_WIDTH                        1  /* LDO3_SWI */
702 #define WM831X_LDO3_LP_MODE                     0x0001  /* LDO3_LP_MODE */
703 #define WM831X_LDO3_LP_MODE_MASK                0x0001  /* LDO3_LP_MODE */
704 #define WM831X_LDO3_LP_MODE_SHIFT                    0  /* LDO3_LP_MODE */
705 #define WM831X_LDO3_LP_MODE_WIDTH                    1  /* LDO3_LP_MODE */
706 
707 /*
708  * R16495 (0x406F) - LDO3 ON Control
709  */
710 #define WM831X_LDO3_ON_SLOT_MASK                0xE000  /* LDO3_ON_SLOT - [15:13] */
711 #define WM831X_LDO3_ON_SLOT_SHIFT                   13  /* LDO3_ON_SLOT - [15:13] */
712 #define WM831X_LDO3_ON_SLOT_WIDTH                    3  /* LDO3_ON_SLOT - [15:13] */
713 #define WM831X_LDO3_ON_MODE                     0x0100  /* LDO3_ON_MODE */
714 #define WM831X_LDO3_ON_MODE_MASK                0x0100  /* LDO3_ON_MODE */
715 #define WM831X_LDO3_ON_MODE_SHIFT                    8  /* LDO3_ON_MODE */
716 #define WM831X_LDO3_ON_MODE_WIDTH                    1  /* LDO3_ON_MODE */
717 #define WM831X_LDO3_ON_VSEL_MASK                0x001F  /* LDO3_ON_VSEL - [4:0] */
718 #define WM831X_LDO3_ON_VSEL_SHIFT                    0  /* LDO3_ON_VSEL - [4:0] */
719 #define WM831X_LDO3_ON_VSEL_WIDTH                    5  /* LDO3_ON_VSEL - [4:0] */
720 
721 /*
722  * R16496 (0x4070) - LDO3 SLEEP Control
723  */
724 #define WM831X_LDO3_SLP_SLOT_MASK               0xE000  /* LDO3_SLP_SLOT - [15:13] */
725 #define WM831X_LDO3_SLP_SLOT_SHIFT                  13  /* LDO3_SLP_SLOT - [15:13] */
726 #define WM831X_LDO3_SLP_SLOT_WIDTH                   3  /* LDO3_SLP_SLOT - [15:13] */
727 #define WM831X_LDO3_SLP_MODE                    0x0100  /* LDO3_SLP_MODE */
728 #define WM831X_LDO3_SLP_MODE_MASK               0x0100  /* LDO3_SLP_MODE */
729 #define WM831X_LDO3_SLP_MODE_SHIFT                   8  /* LDO3_SLP_MODE */
730 #define WM831X_LDO3_SLP_MODE_WIDTH                   1  /* LDO3_SLP_MODE */
731 #define WM831X_LDO3_SLP_VSEL_MASK               0x001F  /* LDO3_SLP_VSEL - [4:0] */
732 #define WM831X_LDO3_SLP_VSEL_SHIFT                   0  /* LDO3_SLP_VSEL - [4:0] */
733 #define WM831X_LDO3_SLP_VSEL_WIDTH                   5  /* LDO3_SLP_VSEL - [4:0] */
734 
735 /*
736  * R16497 (0x4071) - LDO4 Control
737  */
738 #define WM831X_LDO4_ERR_ACT_MASK                0xC000  /* LDO4_ERR_ACT - [15:14] */
739 #define WM831X_LDO4_ERR_ACT_SHIFT                   14  /* LDO4_ERR_ACT - [15:14] */
740 #define WM831X_LDO4_ERR_ACT_WIDTH                    2  /* LDO4_ERR_ACT - [15:14] */
741 #define WM831X_LDO4_HWC_SRC_MASK                0x1800  /* LDO4_HWC_SRC - [12:11] */
742 #define WM831X_LDO4_HWC_SRC_SHIFT                   11  /* LDO4_HWC_SRC - [12:11] */
743 #define WM831X_LDO4_HWC_SRC_WIDTH                    2  /* LDO4_HWC_SRC - [12:11] */
744 #define WM831X_LDO4_HWC_VSEL                    0x0400  /* LDO4_HWC_VSEL */
745 #define WM831X_LDO4_HWC_VSEL_MASK               0x0400  /* LDO4_HWC_VSEL */
746 #define WM831X_LDO4_HWC_VSEL_SHIFT                  10  /* LDO4_HWC_VSEL */
747 #define WM831X_LDO4_HWC_VSEL_WIDTH                   1  /* LDO4_HWC_VSEL */
748 #define WM831X_LDO4_HWC_MODE_MASK               0x0300  /* LDO4_HWC_MODE - [9:8] */
749 #define WM831X_LDO4_HWC_MODE_SHIFT                   8  /* LDO4_HWC_MODE - [9:8] */
750 #define WM831X_LDO4_HWC_MODE_WIDTH                   2  /* LDO4_HWC_MODE - [9:8] */
751 #define WM831X_LDO4_FLT                         0x0080  /* LDO4_FLT */
752 #define WM831X_LDO4_FLT_MASK                    0x0080  /* LDO4_FLT */
753 #define WM831X_LDO4_FLT_SHIFT                        7  /* LDO4_FLT */
754 #define WM831X_LDO4_FLT_WIDTH                        1  /* LDO4_FLT */
755 #define WM831X_LDO4_SWI                         0x0040  /* LDO4_SWI */
756 #define WM831X_LDO4_SWI_MASK                    0x0040  /* LDO4_SWI */
757 #define WM831X_LDO4_SWI_SHIFT                        6  /* LDO4_SWI */
758 #define WM831X_LDO4_SWI_WIDTH                        1  /* LDO4_SWI */
759 #define WM831X_LDO4_LP_MODE                     0x0001  /* LDO4_LP_MODE */
760 #define WM831X_LDO4_LP_MODE_MASK                0x0001  /* LDO4_LP_MODE */
761 #define WM831X_LDO4_LP_MODE_SHIFT                    0  /* LDO4_LP_MODE */
762 #define WM831X_LDO4_LP_MODE_WIDTH                    1  /* LDO4_LP_MODE */
763 
764 /*
765  * R16498 (0x4072) - LDO4 ON Control
766  */
767 #define WM831X_LDO4_ON_SLOT_MASK                0xE000  /* LDO4_ON_SLOT - [15:13] */
768 #define WM831X_LDO4_ON_SLOT_SHIFT                   13  /* LDO4_ON_SLOT - [15:13] */
769 #define WM831X_LDO4_ON_SLOT_WIDTH                    3  /* LDO4_ON_SLOT - [15:13] */
770 #define WM831X_LDO4_ON_MODE                     0x0100  /* LDO4_ON_MODE */
771 #define WM831X_LDO4_ON_MODE_MASK                0x0100  /* LDO4_ON_MODE */
772 #define WM831X_LDO4_ON_MODE_SHIFT                    8  /* LDO4_ON_MODE */
773 #define WM831X_LDO4_ON_MODE_WIDTH                    1  /* LDO4_ON_MODE */
774 #define WM831X_LDO4_ON_VSEL_MASK                0x001F  /* LDO4_ON_VSEL - [4:0] */
775 #define WM831X_LDO4_ON_VSEL_SHIFT                    0  /* LDO4_ON_VSEL - [4:0] */
776 #define WM831X_LDO4_ON_VSEL_WIDTH                    5  /* LDO4_ON_VSEL - [4:0] */
777 
778 /*
779  * R16499 (0x4073) - LDO4 SLEEP Control
780  */
781 #define WM831X_LDO4_SLP_SLOT_MASK               0xE000  /* LDO4_SLP_SLOT - [15:13] */
782 #define WM831X_LDO4_SLP_SLOT_SHIFT                  13  /* LDO4_SLP_SLOT - [15:13] */
783 #define WM831X_LDO4_SLP_SLOT_WIDTH                   3  /* LDO4_SLP_SLOT - [15:13] */
784 #define WM831X_LDO4_SLP_MODE                    0x0100  /* LDO4_SLP_MODE */
785 #define WM831X_LDO4_SLP_MODE_MASK               0x0100  /* LDO4_SLP_MODE */
786 #define WM831X_LDO4_SLP_MODE_SHIFT                   8  /* LDO4_SLP_MODE */
787 #define WM831X_LDO4_SLP_MODE_WIDTH                   1  /* LDO4_SLP_MODE */
788 #define WM831X_LDO4_SLP_VSEL_MASK               0x001F  /* LDO4_SLP_VSEL - [4:0] */
789 #define WM831X_LDO4_SLP_VSEL_SHIFT                   0  /* LDO4_SLP_VSEL - [4:0] */
790 #define WM831X_LDO4_SLP_VSEL_WIDTH                   5  /* LDO4_SLP_VSEL - [4:0] */
791 
792 /*
793  * R16500 (0x4074) - LDO5 Control
794  */
795 #define WM831X_LDO5_ERR_ACT_MASK                0xC000  /* LDO5_ERR_ACT - [15:14] */
796 #define WM831X_LDO5_ERR_ACT_SHIFT                   14  /* LDO5_ERR_ACT - [15:14] */
797 #define WM831X_LDO5_ERR_ACT_WIDTH                    2  /* LDO5_ERR_ACT - [15:14] */
798 #define WM831X_LDO5_HWC_SRC_MASK                0x1800  /* LDO5_HWC_SRC - [12:11] */
799 #define WM831X_LDO5_HWC_SRC_SHIFT                   11  /* LDO5_HWC_SRC - [12:11] */
800 #define WM831X_LDO5_HWC_SRC_WIDTH                    2  /* LDO5_HWC_SRC - [12:11] */
801 #define WM831X_LDO5_HWC_VSEL                    0x0400  /* LDO5_HWC_VSEL */
802 #define WM831X_LDO5_HWC_VSEL_MASK               0x0400  /* LDO5_HWC_VSEL */
803 #define WM831X_LDO5_HWC_VSEL_SHIFT                  10  /* LDO5_HWC_VSEL */
804 #define WM831X_LDO5_HWC_VSEL_WIDTH                   1  /* LDO5_HWC_VSEL */
805 #define WM831X_LDO5_HWC_MODE_MASK               0x0300  /* LDO5_HWC_MODE - [9:8] */
806 #define WM831X_LDO5_HWC_MODE_SHIFT                   8  /* LDO5_HWC_MODE - [9:8] */
807 #define WM831X_LDO5_HWC_MODE_WIDTH                   2  /* LDO5_HWC_MODE - [9:8] */
808 #define WM831X_LDO5_FLT                         0x0080  /* LDO5_FLT */
809 #define WM831X_LDO5_FLT_MASK                    0x0080  /* LDO5_FLT */
810 #define WM831X_LDO5_FLT_SHIFT                        7  /* LDO5_FLT */
811 #define WM831X_LDO5_FLT_WIDTH                        1  /* LDO5_FLT */
812 #define WM831X_LDO5_SWI                         0x0040  /* LDO5_SWI */
813 #define WM831X_LDO5_SWI_MASK                    0x0040  /* LDO5_SWI */
814 #define WM831X_LDO5_SWI_SHIFT                        6  /* LDO5_SWI */
815 #define WM831X_LDO5_SWI_WIDTH                        1  /* LDO5_SWI */
816 #define WM831X_LDO5_LP_MODE                     0x0001  /* LDO5_LP_MODE */
817 #define WM831X_LDO5_LP_MODE_MASK                0x0001  /* LDO5_LP_MODE */
818 #define WM831X_LDO5_LP_MODE_SHIFT                    0  /* LDO5_LP_MODE */
819 #define WM831X_LDO5_LP_MODE_WIDTH                    1  /* LDO5_LP_MODE */
820 
821 /*
822  * R16501 (0x4075) - LDO5 ON Control
823  */
824 #define WM831X_LDO5_ON_SLOT_MASK                0xE000  /* LDO5_ON_SLOT - [15:13] */
825 #define WM831X_LDO5_ON_SLOT_SHIFT                   13  /* LDO5_ON_SLOT - [15:13] */
826 #define WM831X_LDO5_ON_SLOT_WIDTH                    3  /* LDO5_ON_SLOT - [15:13] */
827 #define WM831X_LDO5_ON_MODE                     0x0100  /* LDO5_ON_MODE */
828 #define WM831X_LDO5_ON_MODE_MASK                0x0100  /* LDO5_ON_MODE */
829 #define WM831X_LDO5_ON_MODE_SHIFT                    8  /* LDO5_ON_MODE */
830 #define WM831X_LDO5_ON_MODE_WIDTH                    1  /* LDO5_ON_MODE */
831 #define WM831X_LDO5_ON_VSEL_MASK                0x001F  /* LDO5_ON_VSEL - [4:0] */
832 #define WM831X_LDO5_ON_VSEL_SHIFT                    0  /* LDO5_ON_VSEL - [4:0] */
833 #define WM831X_LDO5_ON_VSEL_WIDTH                    5  /* LDO5_ON_VSEL - [4:0] */
834 
835 /*
836  * R16502 (0x4076) - LDO5 SLEEP Control
837  */
838 #define WM831X_LDO5_SLP_SLOT_MASK               0xE000  /* LDO5_SLP_SLOT - [15:13] */
839 #define WM831X_LDO5_SLP_SLOT_SHIFT                  13  /* LDO5_SLP_SLOT - [15:13] */
840 #define WM831X_LDO5_SLP_SLOT_WIDTH                   3  /* LDO5_SLP_SLOT - [15:13] */
841 #define WM831X_LDO5_SLP_MODE                    0x0100  /* LDO5_SLP_MODE */
842 #define WM831X_LDO5_SLP_MODE_MASK               0x0100  /* LDO5_SLP_MODE */
843 #define WM831X_LDO5_SLP_MODE_SHIFT                   8  /* LDO5_SLP_MODE */
844 #define WM831X_LDO5_SLP_MODE_WIDTH                   1  /* LDO5_SLP_MODE */
845 #define WM831X_LDO5_SLP_VSEL_MASK               0x001F  /* LDO5_SLP_VSEL - [4:0] */
846 #define WM831X_LDO5_SLP_VSEL_SHIFT                   0  /* LDO5_SLP_VSEL - [4:0] */
847 #define WM831X_LDO5_SLP_VSEL_WIDTH                   5  /* LDO5_SLP_VSEL - [4:0] */
848 
849 /*
850  * R16503 (0x4077) - LDO6 Control
851  */
852 #define WM831X_LDO6_ERR_ACT_MASK                0xC000  /* LDO6_ERR_ACT - [15:14] */
853 #define WM831X_LDO6_ERR_ACT_SHIFT                   14  /* LDO6_ERR_ACT - [15:14] */
854 #define WM831X_LDO6_ERR_ACT_WIDTH                    2  /* LDO6_ERR_ACT - [15:14] */
855 #define WM831X_LDO6_HWC_SRC_MASK                0x1800  /* LDO6_HWC_SRC - [12:11] */
856 #define WM831X_LDO6_HWC_SRC_SHIFT                   11  /* LDO6_HWC_SRC - [12:11] */
857 #define WM831X_LDO6_HWC_SRC_WIDTH                    2  /* LDO6_HWC_SRC - [12:11] */
858 #define WM831X_LDO6_HWC_VSEL                    0x0400  /* LDO6_HWC_VSEL */
859 #define WM831X_LDO6_HWC_VSEL_MASK               0x0400  /* LDO6_HWC_VSEL */
860 #define WM831X_LDO6_HWC_VSEL_SHIFT                  10  /* LDO6_HWC_VSEL */
861 #define WM831X_LDO6_HWC_VSEL_WIDTH                   1  /* LDO6_HWC_VSEL */
862 #define WM831X_LDO6_HWC_MODE_MASK               0x0300  /* LDO6_HWC_MODE - [9:8] */
863 #define WM831X_LDO6_HWC_MODE_SHIFT                   8  /* LDO6_HWC_MODE - [9:8] */
864 #define WM831X_LDO6_HWC_MODE_WIDTH                   2  /* LDO6_HWC_MODE - [9:8] */
865 #define WM831X_LDO6_FLT                         0x0080  /* LDO6_FLT */
866 #define WM831X_LDO6_FLT_MASK                    0x0080  /* LDO6_FLT */
867 #define WM831X_LDO6_FLT_SHIFT                        7  /* LDO6_FLT */
868 #define WM831X_LDO6_FLT_WIDTH                        1  /* LDO6_FLT */
869 #define WM831X_LDO6_SWI                         0x0040  /* LDO6_SWI */
870 #define WM831X_LDO6_SWI_MASK                    0x0040  /* LDO6_SWI */
871 #define WM831X_LDO6_SWI_SHIFT                        6  /* LDO6_SWI */
872 #define WM831X_LDO6_SWI_WIDTH                        1  /* LDO6_SWI */
873 #define WM831X_LDO6_LP_MODE                     0x0001  /* LDO6_LP_MODE */
874 #define WM831X_LDO6_LP_MODE_MASK                0x0001  /* LDO6_LP_MODE */
875 #define WM831X_LDO6_LP_MODE_SHIFT                    0  /* LDO6_LP_MODE */
876 #define WM831X_LDO6_LP_MODE_WIDTH                    1  /* LDO6_LP_MODE */
877 
878 /*
879  * R16504 (0x4078) - LDO6 ON Control
880  */
881 #define WM831X_LDO6_ON_SLOT_MASK                0xE000  /* LDO6_ON_SLOT - [15:13] */
882 #define WM831X_LDO6_ON_SLOT_SHIFT                   13  /* LDO6_ON_SLOT - [15:13] */
883 #define WM831X_LDO6_ON_SLOT_WIDTH                    3  /* LDO6_ON_SLOT - [15:13] */
884 #define WM831X_LDO6_ON_MODE                     0x0100  /* LDO6_ON_MODE */
885 #define WM831X_LDO6_ON_MODE_MASK                0x0100  /* LDO6_ON_MODE */
886 #define WM831X_LDO6_ON_MODE_SHIFT                    8  /* LDO6_ON_MODE */
887 #define WM831X_LDO6_ON_MODE_WIDTH                    1  /* LDO6_ON_MODE */
888 #define WM831X_LDO6_ON_VSEL_MASK                0x001F  /* LDO6_ON_VSEL - [4:0] */
889 #define WM831X_LDO6_ON_VSEL_SHIFT                    0  /* LDO6_ON_VSEL - [4:0] */
890 #define WM831X_LDO6_ON_VSEL_WIDTH                    5  /* LDO6_ON_VSEL - [4:0] */
891 
892 /*
893  * R16505 (0x4079) - LDO6 SLEEP Control
894  */
895 #define WM831X_LDO6_SLP_SLOT_MASK               0xE000  /* LDO6_SLP_SLOT - [15:13] */
896 #define WM831X_LDO6_SLP_SLOT_SHIFT                  13  /* LDO6_SLP_SLOT - [15:13] */
897 #define WM831X_LDO6_SLP_SLOT_WIDTH                   3  /* LDO6_SLP_SLOT - [15:13] */
898 #define WM831X_LDO6_SLP_MODE                    0x0100  /* LDO6_SLP_MODE */
899 #define WM831X_LDO6_SLP_MODE_MASK               0x0100  /* LDO6_SLP_MODE */
900 #define WM831X_LDO6_SLP_MODE_SHIFT                   8  /* LDO6_SLP_MODE */
901 #define WM831X_LDO6_SLP_MODE_WIDTH                   1  /* LDO6_SLP_MODE */
902 #define WM831X_LDO6_SLP_VSEL_MASK               0x001F  /* LDO6_SLP_VSEL - [4:0] */
903 #define WM831X_LDO6_SLP_VSEL_SHIFT                   0  /* LDO6_SLP_VSEL - [4:0] */
904 #define WM831X_LDO6_SLP_VSEL_WIDTH                   5  /* LDO6_SLP_VSEL - [4:0] */
905 
906 /*
907  * R16506 (0x407A) - LDO7 Control
908  */
909 #define WM831X_LDO7_ERR_ACT_MASK                0xC000  /* LDO7_ERR_ACT - [15:14] */
910 #define WM831X_LDO7_ERR_ACT_SHIFT                   14  /* LDO7_ERR_ACT - [15:14] */
911 #define WM831X_LDO7_ERR_ACT_WIDTH                    2  /* LDO7_ERR_ACT - [15:14] */
912 #define WM831X_LDO7_HWC_SRC_MASK                0x1800  /* LDO7_HWC_SRC - [12:11] */
913 #define WM831X_LDO7_HWC_SRC_SHIFT                   11  /* LDO7_HWC_SRC - [12:11] */
914 #define WM831X_LDO7_HWC_SRC_WIDTH                    2  /* LDO7_HWC_SRC - [12:11] */
915 #define WM831X_LDO7_HWC_VSEL                    0x0400  /* LDO7_HWC_VSEL */
916 #define WM831X_LDO7_HWC_VSEL_MASK               0x0400  /* LDO7_HWC_VSEL */
917 #define WM831X_LDO7_HWC_VSEL_SHIFT                  10  /* LDO7_HWC_VSEL */
918 #define WM831X_LDO7_HWC_VSEL_WIDTH                   1  /* LDO7_HWC_VSEL */
919 #define WM831X_LDO7_HWC_MODE_MASK               0x0300  /* LDO7_HWC_MODE - [9:8] */
920 #define WM831X_LDO7_HWC_MODE_SHIFT                   8  /* LDO7_HWC_MODE - [9:8] */
921 #define WM831X_LDO7_HWC_MODE_WIDTH                   2  /* LDO7_HWC_MODE - [9:8] */
922 #define WM831X_LDO7_FLT                         0x0080  /* LDO7_FLT */
923 #define WM831X_LDO7_FLT_MASK                    0x0080  /* LDO7_FLT */
924 #define WM831X_LDO7_FLT_SHIFT                        7  /* LDO7_FLT */
925 #define WM831X_LDO7_FLT_WIDTH                        1  /* LDO7_FLT */
926 #define WM831X_LDO7_SWI                         0x0040  /* LDO7_SWI */
927 #define WM831X_LDO7_SWI_MASK                    0x0040  /* LDO7_SWI */
928 #define WM831X_LDO7_SWI_SHIFT                        6  /* LDO7_SWI */
929 #define WM831X_LDO7_SWI_WIDTH                        1  /* LDO7_SWI */
930 
931 /*
932  * R16507 (0x407B) - LDO7 ON Control
933  */
934 #define WM831X_LDO7_ON_SLOT_MASK                0xE000  /* LDO7_ON_SLOT - [15:13] */
935 #define WM831X_LDO7_ON_SLOT_SHIFT                   13  /* LDO7_ON_SLOT - [15:13] */
936 #define WM831X_LDO7_ON_SLOT_WIDTH                    3  /* LDO7_ON_SLOT - [15:13] */
937 #define WM831X_LDO7_ON_MODE                     0x0100  /* LDO7_ON_MODE */
938 #define WM831X_LDO7_ON_MODE_MASK                0x0100  /* LDO7_ON_MODE */
939 #define WM831X_LDO7_ON_MODE_SHIFT                    8  /* LDO7_ON_MODE */
940 #define WM831X_LDO7_ON_MODE_WIDTH                    1  /* LDO7_ON_MODE */
941 #define WM831X_LDO7_ON_VSEL_MASK                0x001F  /* LDO7_ON_VSEL - [4:0] */
942 #define WM831X_LDO7_ON_VSEL_SHIFT                    0  /* LDO7_ON_VSEL - [4:0] */
943 #define WM831X_LDO7_ON_VSEL_WIDTH                    5  /* LDO7_ON_VSEL - [4:0] */
944 
945 /*
946  * R16508 (0x407C) - LDO7 SLEEP Control
947  */
948 #define WM831X_LDO7_SLP_SLOT_MASK               0xE000  /* LDO7_SLP_SLOT - [15:13] */
949 #define WM831X_LDO7_SLP_SLOT_SHIFT                  13  /* LDO7_SLP_SLOT - [15:13] */
950 #define WM831X_LDO7_SLP_SLOT_WIDTH                   3  /* LDO7_SLP_SLOT - [15:13] */
951 #define WM831X_LDO7_SLP_MODE                    0x0100  /* LDO7_SLP_MODE */
952 #define WM831X_LDO7_SLP_MODE_MASK               0x0100  /* LDO7_SLP_MODE */
953 #define WM831X_LDO7_SLP_MODE_SHIFT                   8  /* LDO7_SLP_MODE */
954 #define WM831X_LDO7_SLP_MODE_WIDTH                   1  /* LDO7_SLP_MODE */
955 #define WM831X_LDO7_SLP_VSEL_MASK               0x001F  /* LDO7_SLP_VSEL - [4:0] */
956 #define WM831X_LDO7_SLP_VSEL_SHIFT                   0  /* LDO7_SLP_VSEL - [4:0] */
957 #define WM831X_LDO7_SLP_VSEL_WIDTH                   5  /* LDO7_SLP_VSEL - [4:0] */
958 
959 /*
960  * R16509 (0x407D) - LDO8 Control
961  */
962 #define WM831X_LDO8_ERR_ACT_MASK                0xC000  /* LDO8_ERR_ACT - [15:14] */
963 #define WM831X_LDO8_ERR_ACT_SHIFT                   14  /* LDO8_ERR_ACT - [15:14] */
964 #define WM831X_LDO8_ERR_ACT_WIDTH                    2  /* LDO8_ERR_ACT - [15:14] */
965 #define WM831X_LDO8_HWC_SRC_MASK                0x1800  /* LDO8_HWC_SRC - [12:11] */
966 #define WM831X_LDO8_HWC_SRC_SHIFT                   11  /* LDO8_HWC_SRC - [12:11] */
967 #define WM831X_LDO8_HWC_SRC_WIDTH                    2  /* LDO8_HWC_SRC - [12:11] */
968 #define WM831X_LDO8_HWC_VSEL                    0x0400  /* LDO8_HWC_VSEL */
969 #define WM831X_LDO8_HWC_VSEL_MASK               0x0400  /* LDO8_HWC_VSEL */
970 #define WM831X_LDO8_HWC_VSEL_SHIFT                  10  /* LDO8_HWC_VSEL */
971 #define WM831X_LDO8_HWC_VSEL_WIDTH                   1  /* LDO8_HWC_VSEL */
972 #define WM831X_LDO8_HWC_MODE_MASK               0x0300  /* LDO8_HWC_MODE - [9:8] */
973 #define WM831X_LDO8_HWC_MODE_SHIFT                   8  /* LDO8_HWC_MODE - [9:8] */
974 #define WM831X_LDO8_HWC_MODE_WIDTH                   2  /* LDO8_HWC_MODE - [9:8] */
975 #define WM831X_LDO8_FLT                         0x0080  /* LDO8_FLT */
976 #define WM831X_LDO8_FLT_MASK                    0x0080  /* LDO8_FLT */
977 #define WM831X_LDO8_FLT_SHIFT                        7  /* LDO8_FLT */
978 #define WM831X_LDO8_FLT_WIDTH                        1  /* LDO8_FLT */
979 #define WM831X_LDO8_SWI                         0x0040  /* LDO8_SWI */
980 #define WM831X_LDO8_SWI_MASK                    0x0040  /* LDO8_SWI */
981 #define WM831X_LDO8_SWI_SHIFT                        6  /* LDO8_SWI */
982 #define WM831X_LDO8_SWI_WIDTH                        1  /* LDO8_SWI */
983 
984 /*
985  * R16510 (0x407E) - LDO8 ON Control
986  */
987 #define WM831X_LDO8_ON_SLOT_MASK                0xE000  /* LDO8_ON_SLOT - [15:13] */
988 #define WM831X_LDO8_ON_SLOT_SHIFT                   13  /* LDO8_ON_SLOT - [15:13] */
989 #define WM831X_LDO8_ON_SLOT_WIDTH                    3  /* LDO8_ON_SLOT - [15:13] */
990 #define WM831X_LDO8_ON_MODE                     0x0100  /* LDO8_ON_MODE */
991 #define WM831X_LDO8_ON_MODE_MASK                0x0100  /* LDO8_ON_MODE */
992 #define WM831X_LDO8_ON_MODE_SHIFT                    8  /* LDO8_ON_MODE */
993 #define WM831X_LDO8_ON_MODE_WIDTH                    1  /* LDO8_ON_MODE */
994 #define WM831X_LDO8_ON_VSEL_MASK                0x001F  /* LDO8_ON_VSEL - [4:0] */
995 #define WM831X_LDO8_ON_VSEL_SHIFT                    0  /* LDO8_ON_VSEL - [4:0] */
996 #define WM831X_LDO8_ON_VSEL_WIDTH                    5  /* LDO8_ON_VSEL - [4:0] */
997 
998 /*
999  * R16511 (0x407F) - LDO8 SLEEP Control
1000  */
1001 #define WM831X_LDO8_SLP_SLOT_MASK               0xE000  /* LDO8_SLP_SLOT - [15:13] */
1002 #define WM831X_LDO8_SLP_SLOT_SHIFT                  13  /* LDO8_SLP_SLOT - [15:13] */
1003 #define WM831X_LDO8_SLP_SLOT_WIDTH                   3  /* LDO8_SLP_SLOT - [15:13] */
1004 #define WM831X_LDO8_SLP_MODE                    0x0100  /* LDO8_SLP_MODE */
1005 #define WM831X_LDO8_SLP_MODE_MASK               0x0100  /* LDO8_SLP_MODE */
1006 #define WM831X_LDO8_SLP_MODE_SHIFT                   8  /* LDO8_SLP_MODE */
1007 #define WM831X_LDO8_SLP_MODE_WIDTH                   1  /* LDO8_SLP_MODE */
1008 #define WM831X_LDO8_SLP_VSEL_MASK               0x001F  /* LDO8_SLP_VSEL - [4:0] */
1009 #define WM831X_LDO8_SLP_VSEL_SHIFT                   0  /* LDO8_SLP_VSEL - [4:0] */
1010 #define WM831X_LDO8_SLP_VSEL_WIDTH                   5  /* LDO8_SLP_VSEL - [4:0] */
1011 
1012 /*
1013  * R16512 (0x4080) - LDO9 Control
1014  */
1015 #define WM831X_LDO9_ERR_ACT_MASK                0xC000  /* LDO9_ERR_ACT - [15:14] */
1016 #define WM831X_LDO9_ERR_ACT_SHIFT                   14  /* LDO9_ERR_ACT - [15:14] */
1017 #define WM831X_LDO9_ERR_ACT_WIDTH                    2  /* LDO9_ERR_ACT - [15:14] */
1018 #define WM831X_LDO9_HWC_SRC_MASK                0x1800  /* LDO9_HWC_SRC - [12:11] */
1019 #define WM831X_LDO9_HWC_SRC_SHIFT                   11  /* LDO9_HWC_SRC - [12:11] */
1020 #define WM831X_LDO9_HWC_SRC_WIDTH                    2  /* LDO9_HWC_SRC - [12:11] */
1021 #define WM831X_LDO9_HWC_VSEL                    0x0400  /* LDO9_HWC_VSEL */
1022 #define WM831X_LDO9_HWC_VSEL_MASK               0x0400  /* LDO9_HWC_VSEL */
1023 #define WM831X_LDO9_HWC_VSEL_SHIFT                  10  /* LDO9_HWC_VSEL */
1024 #define WM831X_LDO9_HWC_VSEL_WIDTH                   1  /* LDO9_HWC_VSEL */
1025 #define WM831X_LDO9_HWC_MODE_MASK               0x0300  /* LDO9_HWC_MODE - [9:8] */
1026 #define WM831X_LDO9_HWC_MODE_SHIFT                   8  /* LDO9_HWC_MODE - [9:8] */
1027 #define WM831X_LDO9_HWC_MODE_WIDTH                   2  /* LDO9_HWC_MODE - [9:8] */
1028 #define WM831X_LDO9_FLT                         0x0080  /* LDO9_FLT */
1029 #define WM831X_LDO9_FLT_MASK                    0x0080  /* LDO9_FLT */
1030 #define WM831X_LDO9_FLT_SHIFT                        7  /* LDO9_FLT */
1031 #define WM831X_LDO9_FLT_WIDTH                        1  /* LDO9_FLT */
1032 #define WM831X_LDO9_SWI                         0x0040  /* LDO9_SWI */
1033 #define WM831X_LDO9_SWI_MASK                    0x0040  /* LDO9_SWI */
1034 #define WM831X_LDO9_SWI_SHIFT                        6  /* LDO9_SWI */
1035 #define WM831X_LDO9_SWI_WIDTH                        1  /* LDO9_SWI */
1036 
1037 /*
1038  * R16513 (0x4081) - LDO9 ON Control
1039  */
1040 #define WM831X_LDO9_ON_SLOT_MASK                0xE000  /* LDO9_ON_SLOT - [15:13] */
1041 #define WM831X_LDO9_ON_SLOT_SHIFT                   13  /* LDO9_ON_SLOT - [15:13] */
1042 #define WM831X_LDO9_ON_SLOT_WIDTH                    3  /* LDO9_ON_SLOT - [15:13] */
1043 #define WM831X_LDO9_ON_MODE                     0x0100  /* LDO9_ON_MODE */
1044 #define WM831X_LDO9_ON_MODE_MASK                0x0100  /* LDO9_ON_MODE */
1045 #define WM831X_LDO9_ON_MODE_SHIFT                    8  /* LDO9_ON_MODE */
1046 #define WM831X_LDO9_ON_MODE_WIDTH                    1  /* LDO9_ON_MODE */
1047 #define WM831X_LDO9_ON_VSEL_MASK                0x001F  /* LDO9_ON_VSEL - [4:0] */
1048 #define WM831X_LDO9_ON_VSEL_SHIFT                    0  /* LDO9_ON_VSEL - [4:0] */
1049 #define WM831X_LDO9_ON_VSEL_WIDTH                    5  /* LDO9_ON_VSEL - [4:0] */
1050 
1051 /*
1052  * R16514 (0x4082) - LDO9 SLEEP Control
1053  */
1054 #define WM831X_LDO9_SLP_SLOT_MASK               0xE000  /* LDO9_SLP_SLOT - [15:13] */
1055 #define WM831X_LDO9_SLP_SLOT_SHIFT                  13  /* LDO9_SLP_SLOT - [15:13] */
1056 #define WM831X_LDO9_SLP_SLOT_WIDTH                   3  /* LDO9_SLP_SLOT - [15:13] */
1057 #define WM831X_LDO9_SLP_MODE                    0x0100  /* LDO9_SLP_MODE */
1058 #define WM831X_LDO9_SLP_MODE_MASK               0x0100  /* LDO9_SLP_MODE */
1059 #define WM831X_LDO9_SLP_MODE_SHIFT                   8  /* LDO9_SLP_MODE */
1060 #define WM831X_LDO9_SLP_MODE_WIDTH                   1  /* LDO9_SLP_MODE */
1061 #define WM831X_LDO9_SLP_VSEL_MASK               0x001F  /* LDO9_SLP_VSEL - [4:0] */
1062 #define WM831X_LDO9_SLP_VSEL_SHIFT                   0  /* LDO9_SLP_VSEL - [4:0] */
1063 #define WM831X_LDO9_SLP_VSEL_WIDTH                   5  /* LDO9_SLP_VSEL - [4:0] */
1064 
1065 /*
1066  * R16515 (0x4083) - LDO10 Control
1067  */
1068 #define WM831X_LDO10_ERR_ACT_MASK               0xC000  /* LDO10_ERR_ACT - [15:14] */
1069 #define WM831X_LDO10_ERR_ACT_SHIFT                  14  /* LDO10_ERR_ACT - [15:14] */
1070 #define WM831X_LDO10_ERR_ACT_WIDTH                   2  /* LDO10_ERR_ACT - [15:14] */
1071 #define WM831X_LDO10_HWC_SRC_MASK               0x1800  /* LDO10_HWC_SRC - [12:11] */
1072 #define WM831X_LDO10_HWC_SRC_SHIFT                  11  /* LDO10_HWC_SRC - [12:11] */
1073 #define WM831X_LDO10_HWC_SRC_WIDTH                   2  /* LDO10_HWC_SRC - [12:11] */
1074 #define WM831X_LDO10_HWC_VSEL                   0x0400  /* LDO10_HWC_VSEL */
1075 #define WM831X_LDO10_HWC_VSEL_MASK              0x0400  /* LDO10_HWC_VSEL */
1076 #define WM831X_LDO10_HWC_VSEL_SHIFT                 10  /* LDO10_HWC_VSEL */
1077 #define WM831X_LDO10_HWC_VSEL_WIDTH                  1  /* LDO10_HWC_VSEL */
1078 #define WM831X_LDO10_HWC_MODE_MASK              0x0300  /* LDO10_HWC_MODE - [9:8] */
1079 #define WM831X_LDO10_HWC_MODE_SHIFT                  8  /* LDO10_HWC_MODE - [9:8] */
1080 #define WM831X_LDO10_HWC_MODE_WIDTH                  2  /* LDO10_HWC_MODE - [9:8] */
1081 #define WM831X_LDO10_FLT                        0x0080  /* LDO10_FLT */
1082 #define WM831X_LDO10_FLT_MASK                   0x0080  /* LDO10_FLT */
1083 #define WM831X_LDO10_FLT_SHIFT                       7  /* LDO10_FLT */
1084 #define WM831X_LDO10_FLT_WIDTH                       1  /* LDO10_FLT */
1085 #define WM831X_LDO10_SWI                        0x0040  /* LDO10_SWI */
1086 #define WM831X_LDO10_SWI_MASK                   0x0040  /* LDO10_SWI */
1087 #define WM831X_LDO10_SWI_SHIFT                       6  /* LDO10_SWI */
1088 #define WM831X_LDO10_SWI_WIDTH                       1  /* LDO10_SWI */
1089 
1090 /*
1091  * R16516 (0x4084) - LDO10 ON Control
1092  */
1093 #define WM831X_LDO10_ON_SLOT_MASK               0xE000  /* LDO10_ON_SLOT - [15:13] */
1094 #define WM831X_LDO10_ON_SLOT_SHIFT                  13  /* LDO10_ON_SLOT - [15:13] */
1095 #define WM831X_LDO10_ON_SLOT_WIDTH                   3  /* LDO10_ON_SLOT - [15:13] */
1096 #define WM831X_LDO10_ON_MODE                    0x0100  /* LDO10_ON_MODE */
1097 #define WM831X_LDO10_ON_MODE_MASK               0x0100  /* LDO10_ON_MODE */
1098 #define WM831X_LDO10_ON_MODE_SHIFT                   8  /* LDO10_ON_MODE */
1099 #define WM831X_LDO10_ON_MODE_WIDTH                   1  /* LDO10_ON_MODE */
1100 #define WM831X_LDO10_ON_VSEL_MASK               0x001F  /* LDO10_ON_VSEL - [4:0] */
1101 #define WM831X_LDO10_ON_VSEL_SHIFT                   0  /* LDO10_ON_VSEL - [4:0] */
1102 #define WM831X_LDO10_ON_VSEL_WIDTH                   5  /* LDO10_ON_VSEL - [4:0] */
1103 
1104 /*
1105  * R16517 (0x4085) - LDO10 SLEEP Control
1106  */
1107 #define WM831X_LDO10_SLP_SLOT_MASK              0xE000  /* LDO10_SLP_SLOT - [15:13] */
1108 #define WM831X_LDO10_SLP_SLOT_SHIFT                 13  /* LDO10_SLP_SLOT - [15:13] */
1109 #define WM831X_LDO10_SLP_SLOT_WIDTH                  3  /* LDO10_SLP_SLOT - [15:13] */
1110 #define WM831X_LDO10_SLP_MODE                   0x0100  /* LDO10_SLP_MODE */
1111 #define WM831X_LDO10_SLP_MODE_MASK              0x0100  /* LDO10_SLP_MODE */
1112 #define WM831X_LDO10_SLP_MODE_SHIFT                  8  /* LDO10_SLP_MODE */
1113 #define WM831X_LDO10_SLP_MODE_WIDTH                  1  /* LDO10_SLP_MODE */
1114 #define WM831X_LDO10_SLP_VSEL_MASK              0x001F  /* LDO10_SLP_VSEL - [4:0] */
1115 #define WM831X_LDO10_SLP_VSEL_SHIFT                  0  /* LDO10_SLP_VSEL - [4:0] */
1116 #define WM831X_LDO10_SLP_VSEL_WIDTH                  5  /* LDO10_SLP_VSEL - [4:0] */
1117 
1118 /*
1119  * R16519 (0x4087) - LDO11 ON Control
1120  */
1121 #define WM831X_LDO11_ON_SLOT_MASK               0xE000  /* LDO11_ON_SLOT - [15:13] */
1122 #define WM831X_LDO11_ON_SLOT_SHIFT                  13  /* LDO11_ON_SLOT - [15:13] */
1123 #define WM831X_LDO11_ON_SLOT_WIDTH                   3  /* LDO11_ON_SLOT - [15:13] */
1124 #define WM831X_LDO11_OFFENA                     0x1000  /* LDO11_OFFENA */
1125 #define WM831X_LDO11_OFFENA_MASK                0x1000  /* LDO11_OFFENA */
1126 #define WM831X_LDO11_OFFENA_SHIFT                   12  /* LDO11_OFFENA */
1127 #define WM831X_LDO11_OFFENA_WIDTH                    1  /* LDO11_OFFENA */
1128 #define WM831X_LDO11_VSEL_SRC                   0x0080  /* LDO11_VSEL_SRC */
1129 #define WM831X_LDO11_VSEL_SRC_MASK              0x0080  /* LDO11_VSEL_SRC */
1130 #define WM831X_LDO11_VSEL_SRC_SHIFT                  7  /* LDO11_VSEL_SRC */
1131 #define WM831X_LDO11_VSEL_SRC_WIDTH                  1  /* LDO11_VSEL_SRC */
1132 #define WM831X_LDO11_ON_VSEL_MASK               0x000F  /* LDO11_ON_VSEL - [3:0] */
1133 #define WM831X_LDO11_ON_VSEL_SHIFT                   0  /* LDO11_ON_VSEL - [3:0] */
1134 #define WM831X_LDO11_ON_VSEL_WIDTH                   4  /* LDO11_ON_VSEL - [3:0] */
1135 
1136 /*
1137  * R16520 (0x4088) - LDO11 SLEEP Control
1138  */
1139 #define WM831X_LDO11_SLP_SLOT_MASK              0xE000  /* LDO11_SLP_SLOT - [15:13] */
1140 #define WM831X_LDO11_SLP_SLOT_SHIFT                 13  /* LDO11_SLP_SLOT - [15:13] */
1141 #define WM831X_LDO11_SLP_SLOT_WIDTH                  3  /* LDO11_SLP_SLOT - [15:13] */
1142 #define WM831X_LDO11_SLP_VSEL_MASK              0x000F  /* LDO11_SLP_VSEL - [3:0] */
1143 #define WM831X_LDO11_SLP_VSEL_SHIFT                  0  /* LDO11_SLP_VSEL - [3:0] */
1144 #define WM831X_LDO11_SLP_VSEL_WIDTH                  4  /* LDO11_SLP_VSEL - [3:0] */
1145 
1146 /*
1147  * R16526 (0x408E) - Power Good Source 1
1148  */
1149 #define WM831X_DC4_OK                           0x0008  /* DC4_OK */
1150 #define WM831X_DC4_OK_MASK                      0x0008  /* DC4_OK */
1151 #define WM831X_DC4_OK_SHIFT                          3  /* DC4_OK */
1152 #define WM831X_DC4_OK_WIDTH                          1  /* DC4_OK */
1153 #define WM831X_DC3_OK                           0x0004  /* DC3_OK */
1154 #define WM831X_DC3_OK_MASK                      0x0004  /* DC3_OK */
1155 #define WM831X_DC3_OK_SHIFT                          2  /* DC3_OK */
1156 #define WM831X_DC3_OK_WIDTH                          1  /* DC3_OK */
1157 #define WM831X_DC2_OK                           0x0002  /* DC2_OK */
1158 #define WM831X_DC2_OK_MASK                      0x0002  /* DC2_OK */
1159 #define WM831X_DC2_OK_SHIFT                          1  /* DC2_OK */
1160 #define WM831X_DC2_OK_WIDTH                          1  /* DC2_OK */
1161 #define WM831X_DC1_OK                           0x0001  /* DC1_OK */
1162 #define WM831X_DC1_OK_MASK                      0x0001  /* DC1_OK */
1163 #define WM831X_DC1_OK_SHIFT                          0  /* DC1_OK */
1164 #define WM831X_DC1_OK_WIDTH                          1  /* DC1_OK */
1165 
1166 /*
1167  * R16527 (0x408F) - Power Good Source 2
1168  */
1169 #define WM831X_LDO10_OK                         0x0200  /* LDO10_OK */
1170 #define WM831X_LDO10_OK_MASK                    0x0200  /* LDO10_OK */
1171 #define WM831X_LDO10_OK_SHIFT                        9  /* LDO10_OK */
1172 #define WM831X_LDO10_OK_WIDTH                        1  /* LDO10_OK */
1173 #define WM831X_LDO9_OK                          0x0100  /* LDO9_OK */
1174 #define WM831X_LDO9_OK_MASK                     0x0100  /* LDO9_OK */
1175 #define WM831X_LDO9_OK_SHIFT                         8  /* LDO9_OK */
1176 #define WM831X_LDO9_OK_WIDTH                         1  /* LDO9_OK */
1177 #define WM831X_LDO8_OK                          0x0080  /* LDO8_OK */
1178 #define WM831X_LDO8_OK_MASK                     0x0080  /* LDO8_OK */
1179 #define WM831X_LDO8_OK_SHIFT                         7  /* LDO8_OK */
1180 #define WM831X_LDO8_OK_WIDTH                         1  /* LDO8_OK */
1181 #define WM831X_LDO7_OK                          0x0040  /* LDO7_OK */
1182 #define WM831X_LDO7_OK_MASK                     0x0040  /* LDO7_OK */
1183 #define WM831X_LDO7_OK_SHIFT                         6  /* LDO7_OK */
1184 #define WM831X_LDO7_OK_WIDTH                         1  /* LDO7_OK */
1185 #define WM831X_LDO6_OK                          0x0020  /* LDO6_OK */
1186 #define WM831X_LDO6_OK_MASK                     0x0020  /* LDO6_OK */
1187 #define WM831X_LDO6_OK_SHIFT                         5  /* LDO6_OK */
1188 #define WM831X_LDO6_OK_WIDTH                         1  /* LDO6_OK */
1189 #define WM831X_LDO5_OK                          0x0010  /* LDO5_OK */
1190 #define WM831X_LDO5_OK_MASK                     0x0010  /* LDO5_OK */
1191 #define WM831X_LDO5_OK_SHIFT                         4  /* LDO5_OK */
1192 #define WM831X_LDO5_OK_WIDTH                         1  /* LDO5_OK */
1193 #define WM831X_LDO4_OK                          0x0008  /* LDO4_OK */
1194 #define WM831X_LDO4_OK_MASK                     0x0008  /* LDO4_OK */
1195 #define WM831X_LDO4_OK_SHIFT                         3  /* LDO4_OK */
1196 #define WM831X_LDO4_OK_WIDTH                         1  /* LDO4_OK */
1197 #define WM831X_LDO3_OK                          0x0004  /* LDO3_OK */
1198 #define WM831X_LDO3_OK_MASK                     0x0004  /* LDO3_OK */
1199 #define WM831X_LDO3_OK_SHIFT                         2  /* LDO3_OK */
1200 #define WM831X_LDO3_OK_WIDTH                         1  /* LDO3_OK */
1201 #define WM831X_LDO2_OK                          0x0002  /* LDO2_OK */
1202 #define WM831X_LDO2_OK_MASK                     0x0002  /* LDO2_OK */
1203 #define WM831X_LDO2_OK_SHIFT                         1  /* LDO2_OK */
1204 #define WM831X_LDO2_OK_WIDTH                         1  /* LDO2_OK */
1205 #define WM831X_LDO1_OK                          0x0001  /* LDO1_OK */
1206 #define WM831X_LDO1_OK_MASK                     0x0001  /* LDO1_OK */
1207 #define WM831X_LDO1_OK_SHIFT                         0  /* LDO1_OK */
1208 #define WM831X_LDO1_OK_WIDTH                         1  /* LDO1_OK */
1209 
1210 #define WM831X_ISINK_MAX_ISEL 55
1211 extern const unsigned int wm831x_isinkv_values[WM831X_ISINK_MAX_ISEL + 1];
1212 
1213 #endif
1214