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Searched refs:VceLevel (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvegam_smumgr.c1211 table->VceLevel[count].Frequency = mm_table->entries[count].eclk; in vegam_populate_smc_vce_level()
1212 table->VceLevel[count].MinVoltage = 0; in vegam_populate_smc_vce_level()
1213 table->VceLevel[count].MinVoltage |= in vegam_populate_smc_vce_level()
1225 table->VceLevel[count].MinVoltage |= in vegam_populate_smc_vce_level()
1227 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT; in vegam_populate_smc_vce_level()
1231 table->VceLevel[count].Frequency, &dividers); in vegam_populate_smc_vce_level()
1236 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in vegam_populate_smc_vce_level()
1238 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency); in vegam_populate_smc_vce_level()
1239 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage); in vegam_populate_smc_vce_level()
H A Dfiji_smumgr.c1433 table->VceLevel[count].Frequency = mm_table->entries[count].eclk; in fiji_populate_smc_vce_level()
1434 table->VceLevel[count].MinVoltage = 0; in fiji_populate_smc_vce_level()
1435 table->VceLevel[count].MinVoltage |= in fiji_populate_smc_vce_level()
1437 table->VceLevel[count].MinVoltage |= in fiji_populate_smc_vce_level()
1440 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT; in fiji_populate_smc_vce_level()
1444 table->VceLevel[count].Frequency, &dividers); in fiji_populate_smc_vce_level()
1449 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in fiji_populate_smc_vce_level()
1451 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency); in fiji_populate_smc_vce_level()
1452 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage); in fiji_populate_smc_vce_level()
H A Dpolaris10_smumgr.c1382 table->VceLevel[count].Frequency = mm_table->entries[count].eclk; in polaris10_populate_smc_vce_level()
1383 table->VceLevel[count].MinVoltage = 0; in polaris10_populate_smc_vce_level()
1384 table->VceLevel[count].MinVoltage |= in polaris10_populate_smc_vce_level()
1396 table->VceLevel[count].MinVoltage |= in polaris10_populate_smc_vce_level()
1398 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT; in polaris10_populate_smc_vce_level()
1402 table->VceLevel[count].Frequency, &dividers); in polaris10_populate_smc_vce_level()
1407 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in polaris10_populate_smc_vce_level()
1409 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency); in polaris10_populate_smc_vce_level()
1410 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage); in polaris10_populate_smc_vce_level()
H A Dtonga_smumgr.c1384 table->VceLevel[count].Frequency = in tonga_populate_smc_vce_level()
1386 table->VceLevel[count].MinVoltage.Vddc = in tonga_populate_smc_vce_level()
1389 table->VceLevel[count].MinVoltage.VddGfx = in tonga_populate_smc_vce_level()
1393 table->VceLevel[count].MinVoltage.Vddci = in tonga_populate_smc_vce_level()
1396 table->VceLevel[count].MinVoltage.Phases = 1; in tonga_populate_smc_vce_level()
1400 table->VceLevel[count].Frequency, &dividers); in tonga_populate_smc_vce_level()
1405 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in tonga_populate_smc_vce_level()
1407 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency); in tonga_populate_smc_vce_level()
H A Dci_smumgr.c1580 table->VceLevel[count].Frequency = vce_table->entries[count].evclk; in ci_populate_smc_vce_level()
1581 table->VceLevel[count].MinVoltage = in ci_populate_smc_vce_level()
1583 table->VceLevel[count].MinPhases = 1; in ci_populate_smc_vce_level()
1586 table->VceLevel[count].Frequency, &dividers); in ci_populate_smc_vce_level()
1591 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_vce_level()
1593 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency); in ci_populate_smc_vce_level()
1594 CONVERT_FROM_HOST_TO_SMC_US(table->VceLevel[count].MinVoltage); in ci_populate_smc_vce_level()
/linux/drivers/gpu/drm/radeon/
H A Dsmu7_fusion.h227 SMU7_Fusion_ExtClkLevel VceLevel[SMU7_MAX_LEVELS_VCE]; member
H A Dsmu7_discrete.h315 SMU7_Discrete_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE]; member
H A Dci_dpm.c2659 table->VceLevel[count].Frequency = in ci_populate_smc_vce_level()
2661 table->VceLevel[count].MinVoltage = in ci_populate_smc_vce_level()
2663 table->VceLevel[count].MinPhases = 1; in ci_populate_smc_vce_level()
2667 table->VceLevel[count].Frequency, false, &dividers); in ci_populate_smc_vce_level()
2671 table->VceLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_vce_level()
2673 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency); in ci_populate_smc_vce_level()
2674 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage); in ci_populate_smc_vce_level()
H A Dkv_dpm.c785 offsetof(SMU7_Fusion_DpmTable, VceLevel), in kv_populate_vce_table()
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu7_fusion.h227 SMU7_Fusion_ExtClkLevel VceLevel[SMU7_MAX_LEVELS_VCE]; member
H A Dsmu7_discrete.h329 SMU7_Discrete_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE]; member
H A Dsmu72_discrete.h271 SMU72_Discrete_ExtClkLevel VceLevel[SMU72_MAX_LEVELS_VCE]; member
H A Dsmu74_discrete.h288 SMU74_Discrete_ExtClkLevel VceLevel[SMU74_MAX_LEVELS_VCE]; member
H A Dsmu73_discrete.h245 SMU73_Discrete_ExtClkLevel VceLevel[SMU73_MAX_LEVELS_VCE]; member
H A Dsmu75_discrete.h293 SMU75_Discrete_ExtClkLevel VceLevel [SMU75_MAX_LEVELS_VCE]; member