1 // SPDX-License-Identifier: GPL-2.0
2 /* DSA driver for:
3 * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
4 * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
5 * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
6 * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
7 *
8 * These switches have a built-in 8051 CPU and can download and execute a
9 * firmware in this CPU. They can also be configured to use an external CPU
10 * handling the switch in a memory-mapped manner by connecting to that external
11 * CPU's memory bus.
12 *
13 * Copyright (C) 2018 Linus Wallej <linus.walleij@linaro.org>
14 * Includes portions of code from the firmware uploader by:
15 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
16 */
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/iopoll.h>
21 #include <linux/of.h>
22 #include <linux/of_mdio.h>
23 #include <linux/bitops.h>
24 #include <linux/bitfield.h>
25 #include <linux/if_bridge.h>
26 #include <linux/if_vlan.h>
27 #include <linux/etherdevice.h>
28 #include <linux/gpio/consumer.h>
29 #include <linux/gpio/driver.h>
30 #include <linux/dsa/8021q.h>
31 #include <linux/random.h>
32 #include <net/dsa.h>
33
34 #include "vitesse-vsc73xx.h"
35
36 #define VSC73XX_BLOCK_MAC 0x1 /* Subblocks 0-4, 6 (CPU port) */
37 #define VSC73XX_BLOCK_ANALYZER 0x2 /* Only subblock 0 */
38 #define VSC73XX_BLOCK_MII 0x3 /* Subblocks 0 and 1 */
39 #define VSC73XX_BLOCK_MEMINIT 0x3 /* Only subblock 2 */
40 #define VSC73XX_BLOCK_CAPTURE 0x4 /* Subblocks 0-4, 6, 7 */
41 #define VSC73XX_BLOCK_ARBITER 0x5 /* Only subblock 0 */
42 #define VSC73XX_BLOCK_SYSTEM 0x7 /* Only subblock 0 */
43
44 /* MII Block subblock */
45 #define VSC73XX_BLOCK_MII_INTERNAL 0x0 /* Internal MDIO subblock */
46 #define VSC73XX_BLOCK_MII_EXTERNAL 0x1 /* External MDIO subblock */
47
48 #define CPU_PORT 6 /* CPU port */
49 #define VSC73XX_NUM_FDB_ROWS 2048
50 #define VSC73XX_NUM_BUCKETS 4
51
52 /* MAC Block registers */
53 #define VSC73XX_MAC_CFG 0x00
54 #define VSC73XX_MACHDXGAP 0x02
55 #define VSC73XX_FCCONF 0x04
56 #define VSC73XX_FCMACHI 0x08
57 #define VSC73XX_FCMACLO 0x0c
58 #define VSC73XX_MAXLEN 0x10
59 #define VSC73XX_ADVPORTM 0x19
60 #define VSC73XX_TXUPDCFG 0x24
61 #define VSC73XX_TXQ_SELECT_CFG 0x28
62 #define VSC73XX_RXOCT 0x50
63 #define VSC73XX_TXOCT 0x51
64 #define VSC73XX_C_RX0 0x52
65 #define VSC73XX_C_RX1 0x53
66 #define VSC73XX_C_RX2 0x54
67 #define VSC73XX_C_TX0 0x55
68 #define VSC73XX_C_TX1 0x56
69 #define VSC73XX_C_TX2 0x57
70 #define VSC73XX_C_CFG 0x58
71 #define VSC73XX_CAT_DROP 0x6e
72 #define VSC73XX_CAT_PR_MISC_L2 0x6f
73 #define VSC73XX_CAT_PR_USR_PRIO 0x75
74 #define VSC73XX_CAT_VLAN_MISC 0x79
75 #define VSC73XX_CAT_PORT_VLAN 0x7a
76 #define VSC73XX_Q_MISC_CONF 0xdf
77
78 /* MAC_CFG register bits */
79 #define VSC73XX_MAC_CFG_WEXC_DIS BIT(31)
80 #define VSC73XX_MAC_CFG_PORT_RST BIT(29)
81 #define VSC73XX_MAC_CFG_TX_EN BIT(28)
82 #define VSC73XX_MAC_CFG_SEED_LOAD BIT(27)
83 #define VSC73XX_MAC_CFG_SEED_MASK GENMASK(26, 19)
84 #define VSC73XX_MAC_CFG_SEED_OFFSET 19
85 #define VSC73XX_MAC_CFG_FDX BIT(18)
86 #define VSC73XX_MAC_CFG_GIGA_MODE BIT(17)
87 #define VSC73XX_MAC_CFG_RX_EN BIT(16)
88 #define VSC73XX_MAC_CFG_VLAN_DBLAWR BIT(15)
89 #define VSC73XX_MAC_CFG_VLAN_AWR BIT(14)
90 #define VSC73XX_MAC_CFG_100_BASE_T BIT(13) /* Not in manual */
91 #define VSC73XX_MAC_CFG_TX_IPG_MASK GENMASK(10, 6)
92 #define VSC73XX_MAC_CFG_TX_IPG_OFFSET 6
93 #define VSC73XX_MAC_CFG_TX_IPG_1000M (6 << VSC73XX_MAC_CFG_TX_IPG_OFFSET)
94 #define VSC73XX_MAC_CFG_TX_IPG_100_10M (17 << VSC73XX_MAC_CFG_TX_IPG_OFFSET)
95 #define VSC73XX_MAC_CFG_MAC_RX_RST BIT(5)
96 #define VSC73XX_MAC_CFG_MAC_TX_RST BIT(4)
97 #define VSC73XX_MAC_CFG_CLK_SEL_MASK GENMASK(2, 0)
98 #define VSC73XX_MAC_CFG_CLK_SEL_OFFSET 0
99 #define VSC73XX_MAC_CFG_CLK_SEL_1000M 1
100 #define VSC73XX_MAC_CFG_CLK_SEL_100M 2
101 #define VSC73XX_MAC_CFG_CLK_SEL_10M 3
102 #define VSC73XX_MAC_CFG_CLK_SEL_EXT 4
103
104 #define VSC73XX_MAC_CFG_1000M_F_PHY (VSC73XX_MAC_CFG_FDX | \
105 VSC73XX_MAC_CFG_GIGA_MODE | \
106 VSC73XX_MAC_CFG_TX_IPG_1000M | \
107 VSC73XX_MAC_CFG_CLK_SEL_EXT)
108 #define VSC73XX_MAC_CFG_100_10M_F_PHY (VSC73XX_MAC_CFG_FDX | \
109 VSC73XX_MAC_CFG_TX_IPG_100_10M | \
110 VSC73XX_MAC_CFG_CLK_SEL_EXT)
111 #define VSC73XX_MAC_CFG_100_10M_H_PHY (VSC73XX_MAC_CFG_TX_IPG_100_10M | \
112 VSC73XX_MAC_CFG_CLK_SEL_EXT)
113 #define VSC73XX_MAC_CFG_1000M_F_RGMII (VSC73XX_MAC_CFG_FDX | \
114 VSC73XX_MAC_CFG_GIGA_MODE | \
115 VSC73XX_MAC_CFG_TX_IPG_1000M | \
116 VSC73XX_MAC_CFG_CLK_SEL_1000M)
117 #define VSC73XX_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \
118 VSC73XX_MAC_CFG_MAC_RX_RST | \
119 VSC73XX_MAC_CFG_MAC_TX_RST)
120
121 /* Flow control register bits */
122 #define VSC73XX_FCCONF_ZERO_PAUSE_EN BIT(17)
123 #define VSC73XX_FCCONF_FLOW_CTRL_OBEY BIT(16)
124 #define VSC73XX_FCCONF_PAUSE_VAL_MASK GENMASK(15, 0)
125
126 /* ADVPORTM advanced port setup register bits */
127 #define VSC73XX_ADVPORTM_IFG_PPM BIT(7)
128 #define VSC73XX_ADVPORTM_EXC_COL_CONT BIT(6)
129 #define VSC73XX_ADVPORTM_EXT_PORT BIT(5)
130 #define VSC73XX_ADVPORTM_INV_GTX BIT(4)
131 #define VSC73XX_ADVPORTM_ENA_GTX BIT(3)
132 #define VSC73XX_ADVPORTM_DDR_MODE BIT(2)
133 #define VSC73XX_ADVPORTM_IO_LOOPBACK BIT(1)
134 #define VSC73XX_ADVPORTM_HOST_LOOPBACK BIT(0)
135
136 /* TXUPDCFG transmit modify setup bits */
137 #define VSC73XX_TXUPDCFG_DSCP_REWR_MODE GENMASK(20, 19)
138 #define VSC73XX_TXUPDCFG_DSCP_REWR_ENA BIT(18)
139 #define VSC73XX_TXUPDCFG_TX_INT_TO_USRPRIO_ENA BIT(17)
140 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID GENMASK(15, 4)
141 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA BIT(3)
142 #define VSC73XX_TXUPDCFG_TX_UPDATE_CRC_CPU_ENA BIT(1)
143 #define VSC73XX_TXUPDCFG_TX_INSERT_TAG BIT(0)
144
145 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_SHIFT 4
146
147 /* CAT_DROP categorizer frame dropping register bits */
148 #define VSC73XX_CAT_DROP_DROP_MC_SMAC_ENA BIT(6)
149 #define VSC73XX_CAT_DROP_FWD_CTRL_ENA BIT(4)
150 #define VSC73XX_CAT_DROP_FWD_PAUSE_ENA BIT(3)
151 #define VSC73XX_CAT_DROP_UNTAGGED_ENA BIT(2)
152 #define VSC73XX_CAT_DROP_TAGGED_ENA BIT(1)
153 #define VSC73XX_CAT_DROP_NULL_MAC_ENA BIT(0)
154
155 #define VSC73XX_Q_MISC_CONF_EXTENT_MEM BIT(31)
156 #define VSC73XX_Q_MISC_CONF_EARLY_TX_MASK GENMASK(4, 1)
157 #define VSC73XX_Q_MISC_CONF_EARLY_TX_512 (1 << 1)
158 #define VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE BIT(0)
159
160 /* CAT_VLAN_MISC categorizer VLAN miscellaneous bits */
161 #define VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA BIT(8)
162 #define VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA BIT(7)
163
164 /* CAT_PORT_VLAN categorizer port VLAN */
165 #define VSC73XX_CAT_PORT_VLAN_VLAN_CFI BIT(15)
166 #define VSC73XX_CAT_PORT_VLAN_VLAN_USR_PRIO GENMASK(14, 12)
167 #define VSC73XX_CAT_PORT_VLAN_VLAN_VID GENMASK(11, 0)
168
169 /* Frame analyzer block 2 registers */
170 #define VSC73XX_STORMLIMIT 0x02
171 #define VSC73XX_ADVLEARN 0x03
172 #define VSC73XX_IFLODMSK 0x04
173 #define VSC73XX_VLANMASK 0x05
174 #define VSC73XX_MACHDATA 0x06
175 #define VSC73XX_MACLDATA 0x07
176 #define VSC73XX_ANMOVED 0x08
177 #define VSC73XX_ANAGEFIL 0x09
178 #define VSC73XX_ANEVENTS 0x0a
179 #define VSC73XX_ANCNTMASK 0x0b
180 #define VSC73XX_ANCNTVAL 0x0c
181 #define VSC73XX_LEARNMASK 0x0d
182 #define VSC73XX_UFLODMASK 0x0e
183 #define VSC73XX_MFLODMASK 0x0f
184 #define VSC73XX_RECVMASK 0x10
185 #define VSC73XX_AGGRCTRL 0x20
186 #define VSC73XX_AGGRMSKS 0x30 /* Until 0x3f */
187 #define VSC73XX_DSTMASKS 0x40 /* Until 0x7f */
188 #define VSC73XX_SRCMASKS 0x80 /* Until 0x87 */
189 #define VSC73XX_CAPENAB 0xa0
190 #define VSC73XX_MACACCESS 0xb0
191 #define VSC73XX_IPMCACCESS 0xb1
192 #define VSC73XX_MACTINDX 0xc0
193 #define VSC73XX_VLANACCESS 0xd0
194 #define VSC73XX_VLANTIDX 0xe0
195 #define VSC73XX_AGENCTRL 0xf0
196 #define VSC73XX_CAPRST 0xff
197
198 #define VSC73XX_SRCMASKS_CPU_COPY BIT(27)
199 #define VSC73XX_SRCMASKS_MIRROR BIT(26)
200 #define VSC73XX_SRCMASKS_PORTS_MASK GENMASK(7, 0)
201
202 #define VSC73XX_MACHDATA_VID GENMASK(27, 16)
203 #define VSC73XX_MACHDATA_MAC0 GENMASK(15, 8)
204 #define VSC73XX_MACHDATA_MAC1 GENMASK(7, 0)
205 #define VSC73XX_MACLDATA_MAC2 GENMASK(31, 24)
206 #define VSC73XX_MACLDATA_MAC3 GENMASK(23, 16)
207 #define VSC73XX_MACLDATA_MAC4 GENMASK(15, 8)
208 #define VSC73XX_MACLDATA_MAC5 GENMASK(7, 0)
209
210 #define VSC73XX_HASH0_VID_FROM_MASK GENMASK(5, 0)
211 #define VSC73XX_HASH0_MAC0_FROM_MASK GENMASK(7, 4)
212 #define VSC73XX_HASH1_MAC0_FROM_MASK GENMASK(3, 0)
213 #define VSC73XX_HASH1_MAC1_FROM_MASK GENMASK(7, 1)
214 #define VSC73XX_HASH2_MAC1_FROM_MASK BIT(0)
215 #define VSC73XX_HASH2_MAC2_FROM_MASK GENMASK(7, 0)
216 #define VSC73XX_HASH2_MAC3_FROM_MASK GENMASK(7, 6)
217 #define VSC73XX_HASH3_MAC3_FROM_MASK GENMASK(5, 0)
218 #define VSC73XX_HASH3_MAC4_FROM_MASK GENMASK(7, 3)
219 #define VSC73XX_HASH4_MAC4_FROM_MASK GENMASK(2, 0)
220
221 #define VSC73XX_HASH0_VID_TO_MASK GENMASK(9, 4)
222 #define VSC73XX_HASH0_MAC0_TO_MASK GENMASK(3, 0)
223 #define VSC73XX_HASH1_MAC0_TO_MASK GENMASK(10, 7)
224 #define VSC73XX_HASH1_MAC1_TO_MASK GENMASK(6, 0)
225 #define VSC73XX_HASH2_MAC1_TO_MASK BIT(10)
226 #define VSC73XX_HASH2_MAC2_TO_MASK GENMASK(9, 2)
227 #define VSC73XX_HASH2_MAC3_TO_MASK GENMASK(1, 0)
228 #define VSC73XX_HASH3_MAC3_TO_MASK GENMASK(10, 5)
229 #define VSC73XX_HASH3_MAC4_TO_MASK GENMASK(4, 0)
230 #define VSC73XX_HASH4_MAC4_TO_MASK GENMASK(10, 8)
231
232 #define VSC73XX_MACTINDX_SHADOW BIT(13)
233 #define VSC73XX_MACTINDX_BUCKET_MSK GENMASK(12, 11)
234 #define VSC73XX_MACTINDX_INDEX_MSK GENMASK(10, 0)
235
236 #define VSC73XX_MACACCESS_CPU_COPY BIT(14)
237 #define VSC73XX_MACACCESS_FWD_KILL BIT(13)
238 #define VSC73XX_MACACCESS_IGNORE_VLAN BIT(12)
239 #define VSC73XX_MACACCESS_AGED_FLAG BIT(11)
240 #define VSC73XX_MACACCESS_VALID BIT(10)
241 #define VSC73XX_MACACCESS_LOCKED BIT(9)
242 #define VSC73XX_MACACCESS_DEST_IDX_MASK GENMASK(8, 3)
243 #define VSC73XX_MACACCESS_CMD_MASK GENMASK(2, 0)
244 #define VSC73XX_MACACCESS_CMD_IDLE 0
245 #define VSC73XX_MACACCESS_CMD_LEARN 1
246 #define VSC73XX_MACACCESS_CMD_FORGET 2
247 #define VSC73XX_MACACCESS_CMD_AGE_TABLE 3
248 #define VSC73XX_MACACCESS_CMD_FLUSH_TABLE 4
249 #define VSC73XX_MACACCESS_CMD_CLEAR_TABLE 5
250 #define VSC73XX_MACACCESS_CMD_READ_ENTRY 6
251 #define VSC73XX_MACACCESS_CMD_WRITE_ENTRY 7
252
253 #define VSC73XX_VLANACCESS_LEARN_DISABLED BIT(30)
254 #define VSC73XX_VLANACCESS_VLAN_MIRROR BIT(29)
255 #define VSC73XX_VLANACCESS_VLAN_SRC_CHECK BIT(28)
256 #define VSC73XX_VLANACCESS_VLAN_PORT_MASK GENMASK(9, 2)
257 #define VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT 2
258 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK GENMASK(1, 0)
259 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE 0
260 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY 1
261 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY 2
262 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE 3
263
264 /* MII block 3 registers */
265 #define VSC73XX_MII_STAT 0x0
266 #define VSC73XX_MII_CMD 0x1
267 #define VSC73XX_MII_DATA 0x2
268 #define VSC73XX_MII_MPRES 0x3
269
270 #define VSC73XX_MII_STAT_BUSY BIT(3)
271 #define VSC73XX_MII_STAT_READ BIT(2)
272 #define VSC73XX_MII_STAT_WRITE BIT(1)
273
274 #define VSC73XX_MII_CMD_SCAN BIT(27)
275 #define VSC73XX_MII_CMD_OPERATION BIT(26)
276 #define VSC73XX_MII_CMD_PHY_ADDR GENMASK(25, 21)
277 #define VSC73XX_MII_CMD_PHY_REG GENMASK(20, 16)
278 #define VSC73XX_MII_CMD_WRITE_DATA GENMASK(15, 0)
279
280 #define VSC73XX_MII_DATA_FAILURE BIT(16)
281 #define VSC73XX_MII_DATA_READ_DATA GENMASK(15, 0)
282
283 #define VSC73XX_MII_MPRES_NOPREAMBLE BIT(6)
284 #define VSC73XX_MII_MPRES_PRESCALEVAL GENMASK(5, 0)
285 #define VSC73XX_MII_PRESCALEVAL_MIN 3 /* min allowed mdio clock prescaler */
286
287 #define VSC73XX_MII_STAT_BUSY BIT(3)
288
289 /* Arbiter block 5 registers */
290 #define VSC73XX_ARBEMPTY 0x0c
291 #define VSC73XX_ARBDISC 0x0e
292 #define VSC73XX_SBACKWDROP 0x12
293 #define VSC73XX_DBACKWDROP 0x13
294 #define VSC73XX_ARBBURSTPROB 0x15
295
296 /* System block 7 registers */
297 #define VSC73XX_ICPU_SIPAD 0x01
298 #define VSC73XX_GMIIDELAY 0x05
299 #define VSC73XX_ICPU_CTRL 0x10
300 #define VSC73XX_ICPU_ADDR 0x11
301 #define VSC73XX_ICPU_SRAM 0x12
302 #define VSC73XX_HWSEM 0x13
303 #define VSC73XX_GLORESET 0x14
304 #define VSC73XX_ICPU_MBOX_VAL 0x15
305 #define VSC73XX_ICPU_MBOX_SET 0x16
306 #define VSC73XX_ICPU_MBOX_CLR 0x17
307 #define VSC73XX_CHIPID 0x18
308 #define VSC73XX_GPIO 0x34
309
310 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE 0
311 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS 1
312 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS 2
313 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS 3
314
315 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_NONE (0 << 4)
316 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_4_NS (1 << 4)
317 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_7_NS (2 << 4)
318 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS (3 << 4)
319
320 #define VSC73XX_ICPU_CTRL_WATCHDOG_RST BIT(31)
321 #define VSC73XX_ICPU_CTRL_CLK_DIV_MASK GENMASK(12, 8)
322 #define VSC73XX_ICPU_CTRL_SRST_HOLD BIT(7)
323 #define VSC73XX_ICPU_CTRL_ICPU_PI_EN BIT(6)
324 #define VSC73XX_ICPU_CTRL_BOOT_EN BIT(3)
325 #define VSC73XX_ICPU_CTRL_EXT_ACC_EN BIT(2)
326 #define VSC73XX_ICPU_CTRL_CLK_EN BIT(1)
327 #define VSC73XX_ICPU_CTRL_SRST BIT(0)
328
329 #define VSC73XX_CHIPID_ID_SHIFT 12
330 #define VSC73XX_CHIPID_ID_MASK 0xffff
331 #define VSC73XX_CHIPID_REV_SHIFT 28
332 #define VSC73XX_CHIPID_REV_MASK 0xf
333 #define VSC73XX_CHIPID_ID_7385 0x7385
334 #define VSC73XX_CHIPID_ID_7388 0x7388
335 #define VSC73XX_CHIPID_ID_7395 0x7395
336 #define VSC73XX_CHIPID_ID_7398 0x7398
337
338 #define VSC73XX_GLORESET_STROBE BIT(4)
339 #define VSC73XX_GLORESET_ICPU_LOCK BIT(3)
340 #define VSC73XX_GLORESET_MEM_LOCK BIT(2)
341 #define VSC73XX_GLORESET_PHY_RESET BIT(1)
342 #define VSC73XX_GLORESET_MASTER_RESET BIT(0)
343
344 #define VSC7385_CLOCK_DELAY ((3 << 4) | 3)
345 #define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3)
346
347 #define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \
348 VSC73XX_ICPU_CTRL_BOOT_EN | \
349 VSC73XX_ICPU_CTRL_EXT_ACC_EN)
350
351 #define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \
352 VSC73XX_ICPU_CTRL_BOOT_EN | \
353 VSC73XX_ICPU_CTRL_CLK_EN | \
354 VSC73XX_ICPU_CTRL_SRST)
355
356 #define IS_7385(a) ((a)->chipid == VSC73XX_CHIPID_ID_7385)
357 #define IS_7388(a) ((a)->chipid == VSC73XX_CHIPID_ID_7388)
358 #define IS_7395(a) ((a)->chipid == VSC73XX_CHIPID_ID_7395)
359 #define IS_7398(a) ((a)->chipid == VSC73XX_CHIPID_ID_7398)
360 #define IS_739X(a) (IS_7395(a) || IS_7398(a))
361
362 #define VSC73XX_POLL_SLEEP_US 1000
363 #define VSC73XX_MDIO_POLL_SLEEP_US 5
364 #define VSC73XX_POLL_TIMEOUT_US 10000
365
366 struct vsc73xx_counter {
367 u8 counter;
368 const char *name;
369 };
370
371 struct vsc73xx_fdb {
372 u16 vid;
373 u8 port;
374 u8 mac[ETH_ALEN];
375 bool valid;
376 };
377
378 /* Counters are named according to the MIB standards where applicable.
379 * Some counters are custom, non-standard. The standard counters are
380 * named in accordance with RFC2819, RFC2021 and IEEE Std 802.3-2002 Annex
381 * 30A Counters.
382 */
383 static const struct vsc73xx_counter vsc73xx_rx_counters[] = {
384 { 0, "RxEtherStatsPkts" },
385 { 1, "RxBroadcast+MulticastPkts" }, /* non-standard counter */
386 { 2, "RxTotalErrorPackets" }, /* non-standard counter */
387 { 3, "RxEtherStatsBroadcastPkts" },
388 { 4, "RxEtherStatsMulticastPkts" },
389 { 5, "RxEtherStatsPkts64Octets" },
390 { 6, "RxEtherStatsPkts65to127Octets" },
391 { 7, "RxEtherStatsPkts128to255Octets" },
392 { 8, "RxEtherStatsPkts256to511Octets" },
393 { 9, "RxEtherStatsPkts512to1023Octets" },
394 { 10, "RxEtherStatsPkts1024to1518Octets" },
395 { 11, "RxJumboFrames" }, /* non-standard counter */
396 { 12, "RxaPauseMACControlFramesTransmitted" },
397 { 13, "RxFIFODrops" }, /* non-standard counter */
398 { 14, "RxBackwardDrops" }, /* non-standard counter */
399 { 15, "RxClassifierDrops" }, /* non-standard counter */
400 { 16, "RxEtherStatsCRCAlignErrors" },
401 { 17, "RxEtherStatsUndersizePkts" },
402 { 18, "RxEtherStatsOversizePkts" },
403 { 19, "RxEtherStatsFragments" },
404 { 20, "RxEtherStatsJabbers" },
405 { 21, "RxaMACControlFramesReceived" },
406 /* 22-24 are undefined */
407 { 25, "RxaFramesReceivedOK" },
408 { 26, "RxQoSClass0" }, /* non-standard counter */
409 { 27, "RxQoSClass1" }, /* non-standard counter */
410 { 28, "RxQoSClass2" }, /* non-standard counter */
411 { 29, "RxQoSClass3" }, /* non-standard counter */
412 };
413
414 static const struct vsc73xx_counter vsc73xx_tx_counters[] = {
415 { 0, "TxEtherStatsPkts" },
416 { 1, "TxBroadcast+MulticastPkts" }, /* non-standard counter */
417 { 2, "TxTotalErrorPackets" }, /* non-standard counter */
418 { 3, "TxEtherStatsBroadcastPkts" },
419 { 4, "TxEtherStatsMulticastPkts" },
420 { 5, "TxEtherStatsPkts64Octets" },
421 { 6, "TxEtherStatsPkts65to127Octets" },
422 { 7, "TxEtherStatsPkts128to255Octets" },
423 { 8, "TxEtherStatsPkts256to511Octets" },
424 { 9, "TxEtherStatsPkts512to1023Octets" },
425 { 10, "TxEtherStatsPkts1024to1518Octets" },
426 { 11, "TxJumboFrames" }, /* non-standard counter */
427 { 12, "TxaPauseMACControlFramesTransmitted" },
428 { 13, "TxFIFODrops" }, /* non-standard counter */
429 { 14, "TxDrops" }, /* non-standard counter */
430 { 15, "TxEtherStatsCollisions" },
431 { 16, "TxEtherStatsCRCAlignErrors" },
432 { 17, "TxEtherStatsUndersizePkts" },
433 { 18, "TxEtherStatsOversizePkts" },
434 { 19, "TxEtherStatsFragments" },
435 { 20, "TxEtherStatsJabbers" },
436 /* 21-24 are undefined */
437 { 25, "TxaFramesReceivedOK" },
438 { 26, "TxQoSClass0" }, /* non-standard counter */
439 { 27, "TxQoSClass1" }, /* non-standard counter */
440 { 28, "TxQoSClass2" }, /* non-standard counter */
441 { 29, "TxQoSClass3" }, /* non-standard counter */
442 };
443
444 struct vsc73xx_vlan_summary {
445 size_t num_tagged;
446 size_t num_untagged;
447 };
448
449 enum vsc73xx_port_vlan_conf {
450 VSC73XX_VLAN_FILTER,
451 VSC73XX_VLAN_FILTER_UNTAG_ALL,
452 VSC73XX_VLAN_IGNORE,
453 };
454
vsc73xx_is_addr_valid(u8 block,u8 subblock)455 int vsc73xx_is_addr_valid(u8 block, u8 subblock)
456 {
457 switch (block) {
458 case VSC73XX_BLOCK_MAC:
459 switch (subblock) {
460 case 0 ... 4:
461 case 6:
462 return 1;
463 }
464 break;
465
466 case VSC73XX_BLOCK_ANALYZER:
467 case VSC73XX_BLOCK_SYSTEM:
468 switch (subblock) {
469 case 0:
470 return 1;
471 }
472 break;
473
474 case VSC73XX_BLOCK_MII:
475 case VSC73XX_BLOCK_ARBITER:
476 switch (subblock) {
477 case 0 ... 1:
478 return 1;
479 }
480 break;
481 case VSC73XX_BLOCK_CAPTURE:
482 switch (subblock) {
483 case 0 ... 4:
484 case 6 ... 7:
485 return 1;
486 }
487 break;
488 }
489
490 return 0;
491 }
492 EXPORT_SYMBOL(vsc73xx_is_addr_valid);
493
vsc73xx_read(struct vsc73xx * vsc,u8 block,u8 subblock,u8 reg,u32 * val)494 static int vsc73xx_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
495 u32 *val)
496 {
497 return vsc->ops->read(vsc, block, subblock, reg, val);
498 }
499
vsc73xx_write(struct vsc73xx * vsc,u8 block,u8 subblock,u8 reg,u32 val)500 static int vsc73xx_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
501 u32 val)
502 {
503 return vsc->ops->write(vsc, block, subblock, reg, val);
504 }
505
vsc73xx_update_bits(struct vsc73xx * vsc,u8 block,u8 subblock,u8 reg,u32 mask,u32 val)506 static int vsc73xx_update_bits(struct vsc73xx *vsc, u8 block, u8 subblock,
507 u8 reg, u32 mask, u32 val)
508 {
509 u32 tmp, orig;
510 int ret;
511
512 /* Same read-modify-write algorithm as e.g. regmap */
513 ret = vsc73xx_read(vsc, block, subblock, reg, &orig);
514 if (ret)
515 return ret;
516 tmp = orig & ~mask;
517 tmp |= val & mask;
518 return vsc73xx_write(vsc, block, subblock, reg, tmp);
519 }
520
vsc73xx_detect(struct vsc73xx * vsc)521 static int vsc73xx_detect(struct vsc73xx *vsc)
522 {
523 bool icpu_si_boot_en;
524 bool icpu_pi_en;
525 u32 val;
526 u32 rev;
527 int ret;
528 u32 id;
529
530 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
531 VSC73XX_ICPU_MBOX_VAL, &val);
532 if (ret) {
533 dev_err(vsc->dev, "unable to read mailbox (%d)\n", ret);
534 return ret;
535 }
536
537 if (val == 0xffffffff) {
538 dev_info(vsc->dev, "chip seems dead.\n");
539 return -EAGAIN;
540 }
541
542 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
543 VSC73XX_CHIPID, &val);
544 if (ret) {
545 dev_err(vsc->dev, "unable to read chip id (%d)\n", ret);
546 return ret;
547 }
548
549 id = (val >> VSC73XX_CHIPID_ID_SHIFT) &
550 VSC73XX_CHIPID_ID_MASK;
551 switch (id) {
552 case VSC73XX_CHIPID_ID_7385:
553 case VSC73XX_CHIPID_ID_7388:
554 case VSC73XX_CHIPID_ID_7395:
555 case VSC73XX_CHIPID_ID_7398:
556 break;
557 default:
558 dev_err(vsc->dev, "unsupported chip, id=%04x\n", id);
559 return -ENODEV;
560 }
561
562 vsc->chipid = id;
563 rev = (val >> VSC73XX_CHIPID_REV_SHIFT) &
564 VSC73XX_CHIPID_REV_MASK;
565 dev_info(vsc->dev, "VSC%04X (rev: %d) switch found\n", id, rev);
566
567 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
568 VSC73XX_ICPU_CTRL, &val);
569 if (ret) {
570 dev_err(vsc->dev, "unable to read iCPU control\n");
571 return ret;
572 }
573
574 /* The iCPU can always be used but can boot in different ways.
575 * If it is initially disabled and has no external memory,
576 * we are in control and can do whatever we like, else we
577 * are probably in trouble (we need some way to communicate
578 * with the running firmware) so we bail out for now.
579 */
580 icpu_pi_en = !!(val & VSC73XX_ICPU_CTRL_ICPU_PI_EN);
581 icpu_si_boot_en = !!(val & VSC73XX_ICPU_CTRL_BOOT_EN);
582 if (icpu_si_boot_en && icpu_pi_en) {
583 dev_err(vsc->dev,
584 "iCPU enabled boots from SI, has external memory\n");
585 dev_err(vsc->dev, "no idea how to deal with this\n");
586 return -ENODEV;
587 }
588 if (icpu_si_boot_en && !icpu_pi_en) {
589 dev_err(vsc->dev,
590 "iCPU enabled boots from PI/SI, no external memory\n");
591 return -EAGAIN;
592 }
593 if (!icpu_si_boot_en && icpu_pi_en) {
594 dev_err(vsc->dev,
595 "iCPU enabled, boots from PI external memory\n");
596 dev_err(vsc->dev, "no idea how to deal with this\n");
597 return -ENODEV;
598 }
599 /* !icpu_si_boot_en && !cpu_pi_en */
600 dev_info(vsc->dev, "iCPU disabled, no external memory\n");
601
602 return 0;
603 }
604
vsc73xx_mdio_busy_check(struct vsc73xx * vsc)605 static int vsc73xx_mdio_busy_check(struct vsc73xx *vsc)
606 {
607 int ret, err;
608 u32 val;
609
610 ret = read_poll_timeout(vsc73xx_read, err,
611 err < 0 || !(val & VSC73XX_MII_STAT_BUSY),
612 VSC73XX_MDIO_POLL_SLEEP_US,
613 VSC73XX_POLL_TIMEOUT_US, false, vsc,
614 VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL,
615 VSC73XX_MII_STAT, &val);
616 if (ret)
617 return ret;
618 return err;
619 }
620
vsc73xx_phy_read(struct dsa_switch * ds,int phy,int regnum)621 static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum)
622 {
623 struct vsc73xx *vsc = ds->priv;
624 u32 cmd;
625 u32 val;
626 int ret;
627
628 ret = vsc73xx_mdio_busy_check(vsc);
629 if (ret)
630 return ret;
631
632 /* Setting bit 26 means "read" */
633 cmd = VSC73XX_MII_CMD_OPERATION |
634 FIELD_PREP(VSC73XX_MII_CMD_PHY_ADDR, phy) |
635 FIELD_PREP(VSC73XX_MII_CMD_PHY_REG, regnum);
636 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL,
637 VSC73XX_MII_CMD, cmd);
638 if (ret)
639 return ret;
640
641 ret = vsc73xx_mdio_busy_check(vsc);
642 if (ret)
643 return ret;
644
645 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL,
646 VSC73XX_MII_DATA, &val);
647 if (ret)
648 return ret;
649 if (val & VSC73XX_MII_DATA_FAILURE) {
650 dev_err(vsc->dev, "reading reg %02x from phy%d failed\n",
651 regnum, phy);
652 return -EIO;
653 }
654 val &= VSC73XX_MII_DATA_READ_DATA;
655
656 dev_dbg(vsc->dev, "read reg %02x from phy%d = %04x\n",
657 regnum, phy, val);
658
659 return val;
660 }
661
vsc73xx_phy_write(struct dsa_switch * ds,int phy,int regnum,u16 val)662 static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum,
663 u16 val)
664 {
665 struct vsc73xx *vsc = ds->priv;
666 u32 cmd;
667 int ret;
668
669 ret = vsc73xx_mdio_busy_check(vsc);
670 if (ret)
671 return ret;
672
673 cmd = FIELD_PREP(VSC73XX_MII_CMD_PHY_ADDR, phy) |
674 FIELD_PREP(VSC73XX_MII_CMD_PHY_REG, regnum) |
675 FIELD_PREP(VSC73XX_MII_CMD_WRITE_DATA, val);
676 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL,
677 VSC73XX_MII_CMD, cmd);
678 if (ret)
679 return ret;
680
681 dev_dbg(vsc->dev, "write %04x to reg %02x in phy%d\n",
682 val, regnum, phy);
683 return 0;
684 }
685
vsc73xx_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)686 static enum dsa_tag_protocol vsc73xx_get_tag_protocol(struct dsa_switch *ds,
687 int port,
688 enum dsa_tag_protocol mp)
689 {
690 /* The switch internally uses a 8 byte header with length,
691 * source port, tag, LPA and priority. This is supposedly
692 * only accessible when operating the switch using the internal
693 * CPU or with an external CPU mapping the device in, but not
694 * when operating the switch over SPI and putting frames in/out
695 * on port 6 (the CPU port). So far we must assume that we
696 * cannot access the tag. (See "Internal frame header" section
697 * 3.9.1 in the manual.)
698 */
699 return DSA_TAG_PROTO_VSC73XX_8021Q;
700 }
701
vsc73xx_wait_for_vlan_table_cmd(struct vsc73xx * vsc)702 static int vsc73xx_wait_for_vlan_table_cmd(struct vsc73xx *vsc)
703 {
704 int ret, err;
705 u32 val;
706
707 ret = read_poll_timeout(vsc73xx_read, err,
708 err < 0 ||
709 ((val & VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK) ==
710 VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE),
711 VSC73XX_POLL_SLEEP_US, VSC73XX_POLL_TIMEOUT_US,
712 false, vsc, VSC73XX_BLOCK_ANALYZER,
713 0, VSC73XX_VLANACCESS, &val);
714 if (ret)
715 return ret;
716 return err;
717 }
718
719 static int
vsc73xx_read_vlan_table_entry(struct vsc73xx * vsc,u16 vid,u8 * portmap)720 vsc73xx_read_vlan_table_entry(struct vsc73xx *vsc, u16 vid, u8 *portmap)
721 {
722 u32 val;
723 int ret;
724
725 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANTIDX, vid);
726
727 ret = vsc73xx_wait_for_vlan_table_cmd(vsc);
728 if (ret)
729 return ret;
730
731 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS,
732 VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK,
733 VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY);
734
735 ret = vsc73xx_wait_for_vlan_table_cmd(vsc);
736 if (ret)
737 return ret;
738
739 vsc73xx_read(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, &val);
740 *portmap = (val & VSC73XX_VLANACCESS_VLAN_PORT_MASK) >>
741 VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT;
742
743 return 0;
744 }
745
746 static int
vsc73xx_write_vlan_table_entry(struct vsc73xx * vsc,u16 vid,u8 portmap)747 vsc73xx_write_vlan_table_entry(struct vsc73xx *vsc, u16 vid, u8 portmap)
748 {
749 int ret;
750
751 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANTIDX, vid);
752
753 ret = vsc73xx_wait_for_vlan_table_cmd(vsc);
754 if (ret)
755 return ret;
756
757 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS,
758 VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK |
759 VSC73XX_VLANACCESS_VLAN_SRC_CHECK |
760 VSC73XX_VLANACCESS_VLAN_PORT_MASK,
761 VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY |
762 VSC73XX_VLANACCESS_VLAN_SRC_CHECK |
763 (portmap << VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT));
764
765 return vsc73xx_wait_for_vlan_table_cmd(vsc);
766 }
767
768 static int
vsc73xx_update_vlan_table(struct vsc73xx * vsc,int port,u16 vid,bool set)769 vsc73xx_update_vlan_table(struct vsc73xx *vsc, int port, u16 vid, bool set)
770 {
771 u8 portmap;
772 int ret;
773
774 ret = vsc73xx_read_vlan_table_entry(vsc, vid, &portmap);
775 if (ret)
776 return ret;
777
778 if (set)
779 portmap |= BIT(port);
780 else
781 portmap &= ~BIT(port);
782
783 return vsc73xx_write_vlan_table_entry(vsc, vid, portmap);
784 }
785
vsc73xx_configure_rgmii_port_delay(struct dsa_switch * ds)786 static int vsc73xx_configure_rgmii_port_delay(struct dsa_switch *ds)
787 {
788 /* Keep 2.0 ns delay for backward complatibility */
789 u32 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS;
790 u32 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS;
791 struct dsa_port *dp = dsa_to_port(ds, CPU_PORT);
792 struct device_node *port_dn = dp->dn;
793 struct vsc73xx *vsc = ds->priv;
794 u32 delay;
795
796 if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay)) {
797 switch (delay) {
798 case 0:
799 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE;
800 break;
801 case 1400:
802 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS;
803 break;
804 case 1700:
805 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS;
806 break;
807 case 2000:
808 break;
809 default:
810 dev_err(vsc->dev,
811 "Unsupported RGMII Transmit Clock Delay\n");
812 return -EINVAL;
813 }
814 } else {
815 dev_dbg(vsc->dev,
816 "RGMII Transmit Clock Delay isn't configured, set to 2.0 ns\n");
817 }
818
819 if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay)) {
820 switch (delay) {
821 case 0:
822 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_NONE;
823 break;
824 case 1400:
825 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_4_NS;
826 break;
827 case 1700:
828 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_7_NS;
829 break;
830 case 2000:
831 break;
832 default:
833 dev_err(vsc->dev,
834 "Unsupported RGMII Receive Clock Delay value\n");
835 return -EINVAL;
836 }
837 } else {
838 dev_dbg(vsc->dev,
839 "RGMII Receive Clock Delay isn't configured, set to 2.0 ns\n");
840 }
841
842 /* MII delay, set both GTX and RX delay */
843 return vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GMIIDELAY,
844 tx_delay | rx_delay);
845 }
846
vsc73xx_setup(struct dsa_switch * ds)847 static int vsc73xx_setup(struct dsa_switch *ds)
848 {
849 struct vsc73xx *vsc = ds->priv;
850 int i, ret, val;
851
852 dev_info(vsc->dev, "set up the switch\n");
853
854 ds->untag_bridge_pvid = true;
855 ds->max_num_bridges = DSA_TAG_8021Q_MAX_NUM_BRIDGES;
856 ds->fdb_isolation = true;
857
858 /* Issue RESET */
859 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET,
860 VSC73XX_GLORESET_MASTER_RESET);
861 usleep_range(125, 200);
862
863 /* Initialize memory, initialize RAM bank 0..15 except 6 and 7
864 * This sequence appears in the
865 * VSC7385 SparX-G5 datasheet section 6.6.1
866 * VSC7395 SparX-G5e datasheet section 6.6.1
867 * "initialization sequence".
868 * No explanation is given to the 0x1010400 magic number.
869 */
870 for (i = 0; i <= 15; i++) {
871 if (i != 6 && i != 7) {
872 vsc73xx_write(vsc, VSC73XX_BLOCK_MEMINIT,
873 2,
874 0, 0x1010400 + i);
875 mdelay(1);
876 }
877 }
878 mdelay(30);
879
880 /* Clear MAC table */
881 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0,
882 VSC73XX_MACACCESS,
883 VSC73XX_MACACCESS_CMD_CLEAR_TABLE);
884
885 /* Set VLAN table to default values */
886 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0,
887 VSC73XX_VLANACCESS,
888 VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE);
889
890 msleep(40);
891
892 /* Use 20KiB buffers on all ports on VSC7395
893 * The VSC7385 has 16KiB buffers and that is the
894 * default if we don't set this up explicitly.
895 * Port "31" is "all ports".
896 */
897 if (IS_739X(vsc))
898 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 0x1f,
899 VSC73XX_Q_MISC_CONF,
900 VSC73XX_Q_MISC_CONF_EXTENT_MEM);
901
902 /* Put all ports into reset until enabled */
903 for (i = 0; i < 7; i++) {
904 if (i == 5)
905 continue;
906 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 4,
907 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET);
908 }
909
910 /* Configure RGMII delay */
911 ret = vsc73xx_configure_rgmii_port_delay(ds);
912 if (ret)
913 return ret;
914
915 /* Ingess VLAN reception mask (table 145) */
916 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANMASK,
917 0xff);
918 /* IP multicast flood mask (table 144) */
919 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_IFLODMSK,
920 0xff);
921
922 mdelay(50);
923
924 /* Disable preamble and use maximum allowed clock for the internal
925 * mdio bus, used for communication with internal PHYs only.
926 */
927 val = VSC73XX_MII_MPRES_NOPREAMBLE |
928 FIELD_PREP(VSC73XX_MII_MPRES_PRESCALEVAL,
929 VSC73XX_MII_PRESCALEVAL_MIN);
930 vsc73xx_write(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL,
931 VSC73XX_MII_MPRES, val);
932
933 /* Release reset from the internal PHYs */
934 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET,
935 VSC73XX_GLORESET_PHY_RESET);
936
937 udelay(4);
938
939 /* Clear VLAN table */
940 for (i = 0; i < VLAN_N_VID; i++)
941 vsc73xx_write_vlan_table_entry(vsc, i, 0);
942
943 INIT_LIST_HEAD(&vsc->vlans);
944
945 rtnl_lock();
946 ret = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q));
947 rtnl_unlock();
948
949 return ret;
950 }
951
vsc73xx_teardown(struct dsa_switch * ds)952 static void vsc73xx_teardown(struct dsa_switch *ds)
953 {
954 rtnl_lock();
955 dsa_tag_8021q_unregister(ds);
956 rtnl_unlock();
957 }
958
vsc73xx_init_port(struct vsc73xx * vsc,int port)959 static void vsc73xx_init_port(struct vsc73xx *vsc, int port)
960 {
961 u32 val;
962
963 /* MAC configure, first reset the port and then write defaults */
964 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
965 port,
966 VSC73XX_MAC_CFG,
967 VSC73XX_MAC_CFG_RESET);
968
969 /* Take up the port in 1Gbit mode by default, this will be
970 * augmented after auto-negotiation on the PHY-facing
971 * ports.
972 */
973 if (port == CPU_PORT)
974 val = VSC73XX_MAC_CFG_1000M_F_RGMII;
975 else
976 val = VSC73XX_MAC_CFG_1000M_F_PHY;
977
978 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
979 port,
980 VSC73XX_MAC_CFG,
981 val |
982 VSC73XX_MAC_CFG_TX_EN |
983 VSC73XX_MAC_CFG_RX_EN);
984
985 /* Flow control for the CPU port:
986 * Use a zero delay pause frame when pause condition is left
987 * Obey pause control frames
988 */
989 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
990 port,
991 VSC73XX_FCCONF,
992 VSC73XX_FCCONF_ZERO_PAUSE_EN |
993 VSC73XX_FCCONF_FLOW_CTRL_OBEY);
994
995 /* Issue pause control frames on PHY facing ports.
996 * Allow early initiation of MAC transmission if the amount
997 * of egress data is below 512 bytes on CPU port.
998 * FIXME: enable 20KiB buffers?
999 */
1000 if (port == CPU_PORT)
1001 val = VSC73XX_Q_MISC_CONF_EARLY_TX_512;
1002 else
1003 val = VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE;
1004 val |= VSC73XX_Q_MISC_CONF_EXTENT_MEM;
1005 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
1006 port,
1007 VSC73XX_Q_MISC_CONF,
1008 val);
1009
1010 /* Flow control MAC: a MAC address used in flow control frames */
1011 val = (vsc->addr[5] << 16) | (vsc->addr[4] << 8) | (vsc->addr[3]);
1012 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
1013 port,
1014 VSC73XX_FCMACHI,
1015 val);
1016 val = (vsc->addr[2] << 16) | (vsc->addr[1] << 8) | (vsc->addr[0]);
1017 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
1018 port,
1019 VSC73XX_FCMACLO,
1020 val);
1021
1022 /* Tell the categorizer to forward pause frames, not control
1023 * frame. Do not drop anything.
1024 */
1025 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
1026 port,
1027 VSC73XX_CAT_DROP,
1028 VSC73XX_CAT_DROP_FWD_PAUSE_ENA);
1029
1030 /* Clear all counters */
1031 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
1032 port, VSC73XX_C_RX0, 0);
1033 }
1034
vsc73xx_reset_port(struct vsc73xx * vsc,int port,u32 initval)1035 static void vsc73xx_reset_port(struct vsc73xx *vsc, int port, u32 initval)
1036 {
1037 int ret, err;
1038 u32 val;
1039
1040 /* Disable RX on this port */
1041 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,
1042 VSC73XX_MAC_CFG,
1043 VSC73XX_MAC_CFG_RX_EN, 0);
1044
1045 /* Discard packets */
1046 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,
1047 VSC73XX_ARBDISC, BIT(port), BIT(port));
1048
1049 /* Wait until queue is empty */
1050 ret = read_poll_timeout(vsc73xx_read, err,
1051 err < 0 || (val & BIT(port)),
1052 VSC73XX_POLL_SLEEP_US,
1053 VSC73XX_POLL_TIMEOUT_US, false,
1054 vsc, VSC73XX_BLOCK_ARBITER, 0,
1055 VSC73XX_ARBEMPTY, &val);
1056 if (ret)
1057 dev_err(vsc->dev,
1058 "timeout waiting for block arbiter\n");
1059 else if (err < 0)
1060 dev_err(vsc->dev, "error reading arbiter\n");
1061
1062 /* Put this port into reset */
1063 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG,
1064 VSC73XX_MAC_CFG_RESET | initval);
1065 }
1066
vsc73xx_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)1067 static void vsc73xx_mac_config(struct phylink_config *config, unsigned int mode,
1068 const struct phylink_link_state *state)
1069 {
1070 struct dsa_port *dp = dsa_phylink_to_port(config);
1071 struct vsc73xx *vsc = dp->ds->priv;
1072 int port = dp->index;
1073
1074 /* Special handling of the CPU-facing port */
1075 if (port == CPU_PORT) {
1076 /* Other ports are already initialized but not this one */
1077 vsc73xx_init_port(vsc, CPU_PORT);
1078 /* Select the external port for this interface (EXT_PORT)
1079 * Enable the GMII GTX external clock
1080 * Use double data rate (DDR mode)
1081 */
1082 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
1083 CPU_PORT,
1084 VSC73XX_ADVPORTM,
1085 VSC73XX_ADVPORTM_EXT_PORT |
1086 VSC73XX_ADVPORTM_ENA_GTX |
1087 VSC73XX_ADVPORTM_DDR_MODE);
1088 }
1089 }
1090
vsc73xx_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)1091 static void vsc73xx_mac_link_down(struct phylink_config *config,
1092 unsigned int mode, phy_interface_t interface)
1093 {
1094 struct dsa_port *dp = dsa_phylink_to_port(config);
1095 struct vsc73xx *vsc = dp->ds->priv;
1096 int port = dp->index;
1097
1098 /* This routine is described in the datasheet (below ARBDISC register
1099 * description)
1100 */
1101 vsc73xx_reset_port(vsc, port, 0);
1102
1103 /* Allow backward dropping of frames from this port */
1104 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,
1105 VSC73XX_SBACKWDROP, BIT(port), BIT(port));
1106 }
1107
vsc73xx_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)1108 static void vsc73xx_mac_link_up(struct phylink_config *config,
1109 struct phy_device *phy, unsigned int mode,
1110 phy_interface_t interface, int speed,
1111 int duplex, bool tx_pause, bool rx_pause)
1112 {
1113 struct dsa_port *dp = dsa_phylink_to_port(config);
1114 struct vsc73xx *vsc = dp->ds->priv;
1115 int port = dp->index;
1116 u32 val;
1117 u8 seed;
1118
1119 if (speed == SPEED_1000)
1120 val = VSC73XX_MAC_CFG_GIGA_MODE | VSC73XX_MAC_CFG_TX_IPG_1000M;
1121 else
1122 val = VSC73XX_MAC_CFG_TX_IPG_100_10M;
1123
1124 if (phy_interface_mode_is_rgmii(interface))
1125 val |= VSC73XX_MAC_CFG_CLK_SEL_1000M;
1126 else
1127 val |= VSC73XX_MAC_CFG_CLK_SEL_EXT;
1128
1129 if (duplex == DUPLEX_FULL)
1130 val |= VSC73XX_MAC_CFG_FDX;
1131 else
1132 /* In datasheet description ("Port Mode Procedure" in 5.6.2)
1133 * this bit is configured only for half duplex.
1134 */
1135 val |= VSC73XX_MAC_CFG_WEXC_DIS;
1136
1137 /* This routine is described in the datasheet (below ARBDISC register
1138 * description)
1139 */
1140 vsc73xx_reset_port(vsc, port, val);
1141
1142 /* Seed the port randomness with randomness */
1143 get_random_bytes(&seed, 1);
1144 val |= seed << VSC73XX_MAC_CFG_SEED_OFFSET;
1145 val |= VSC73XX_MAC_CFG_SEED_LOAD;
1146
1147 /* Those bits are responsible for MTU only. Kernel takes care about MTU,
1148 * let's enable +8 bytes frame length unconditionally.
1149 */
1150 val |= VSC73XX_MAC_CFG_VLAN_AWR | VSC73XX_MAC_CFG_VLAN_DBLAWR;
1151
1152 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val);
1153
1154 /* Flow control for the PHY facing ports:
1155 * Use a zero delay pause frame when pause condition is left
1156 * Obey pause control frames
1157 * When generating pause frames, use 0xff as pause value
1158 */
1159 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_FCCONF,
1160 VSC73XX_FCCONF_ZERO_PAUSE_EN |
1161 VSC73XX_FCCONF_FLOW_CTRL_OBEY |
1162 0xff);
1163
1164 /* Accept packets again */
1165 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,
1166 VSC73XX_ARBDISC, BIT(port), 0);
1167
1168 /* Disallow backward dropping of frames from this port */
1169 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,
1170 VSC73XX_SBACKWDROP, BIT(port), 0);
1171
1172 /* Enable TX, RX, deassert reset, stop loading seed */
1173 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,
1174 VSC73XX_MAC_CFG,
1175 VSC73XX_MAC_CFG_RESET | VSC73XX_MAC_CFG_SEED_LOAD |
1176 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN,
1177 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN);
1178 }
1179
vsc73xx_tag_8021q_active(struct dsa_port * dp)1180 static bool vsc73xx_tag_8021q_active(struct dsa_port *dp)
1181 {
1182 return !dsa_port_is_vlan_filtering(dp);
1183 }
1184
1185 static struct vsc73xx_bridge_vlan *
vsc73xx_bridge_vlan_find(struct vsc73xx * vsc,u16 vid)1186 vsc73xx_bridge_vlan_find(struct vsc73xx *vsc, u16 vid)
1187 {
1188 struct vsc73xx_bridge_vlan *vlan;
1189
1190 list_for_each_entry(vlan, &vsc->vlans, list)
1191 if (vlan->vid == vid)
1192 return vlan;
1193
1194 return NULL;
1195 }
1196
1197 static void
vsc73xx_bridge_vlan_remove_port(struct vsc73xx_bridge_vlan * vsc73xx_vlan,int port)1198 vsc73xx_bridge_vlan_remove_port(struct vsc73xx_bridge_vlan *vsc73xx_vlan,
1199 int port)
1200 {
1201 vsc73xx_vlan->portmask &= ~BIT(port);
1202
1203 if (vsc73xx_vlan->portmask)
1204 return;
1205
1206 list_del(&vsc73xx_vlan->list);
1207 kfree(vsc73xx_vlan);
1208 }
1209
vsc73xx_bridge_vlan_summary(struct vsc73xx * vsc,int port,struct vsc73xx_vlan_summary * summary,u16 ignored_vid)1210 static void vsc73xx_bridge_vlan_summary(struct vsc73xx *vsc, int port,
1211 struct vsc73xx_vlan_summary *summary,
1212 u16 ignored_vid)
1213 {
1214 size_t num_tagged = 0, num_untagged = 0;
1215 struct vsc73xx_bridge_vlan *vlan;
1216
1217 list_for_each_entry(vlan, &vsc->vlans, list) {
1218 if (!(vlan->portmask & BIT(port)) || vlan->vid == ignored_vid)
1219 continue;
1220
1221 if (vlan->untagged & BIT(port))
1222 num_untagged++;
1223 else
1224 num_tagged++;
1225 }
1226
1227 summary->num_untagged = num_untagged;
1228 summary->num_tagged = num_tagged;
1229 }
1230
vsc73xx_find_first_vlan_untagged(struct vsc73xx * vsc,int port)1231 static u16 vsc73xx_find_first_vlan_untagged(struct vsc73xx *vsc, int port)
1232 {
1233 struct vsc73xx_bridge_vlan *vlan;
1234
1235 list_for_each_entry(vlan, &vsc->vlans, list)
1236 if ((vlan->portmask & BIT(port)) &&
1237 (vlan->untagged & BIT(port)))
1238 return vlan->vid;
1239
1240 return VLAN_N_VID;
1241 }
1242
vsc73xx_set_vlan_conf(struct vsc73xx * vsc,int port,enum vsc73xx_port_vlan_conf port_vlan_conf)1243 static int vsc73xx_set_vlan_conf(struct vsc73xx *vsc, int port,
1244 enum vsc73xx_port_vlan_conf port_vlan_conf)
1245 {
1246 u32 val = 0;
1247 int ret;
1248
1249 if (port_vlan_conf == VSC73XX_VLAN_IGNORE)
1250 val = VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA |
1251 VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA;
1252
1253 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,
1254 VSC73XX_CAT_VLAN_MISC,
1255 VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA |
1256 VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA, val);
1257 if (ret)
1258 return ret;
1259
1260 val = (port_vlan_conf == VSC73XX_VLAN_FILTER) ?
1261 VSC73XX_TXUPDCFG_TX_INSERT_TAG : 0;
1262
1263 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,
1264 VSC73XX_TXUPDCFG,
1265 VSC73XX_TXUPDCFG_TX_INSERT_TAG, val);
1266 }
1267
1268 /**
1269 * vsc73xx_vlan_commit_conf - Update VLAN configuration of a port
1270 * @vsc: Switch private data structure
1271 * @port: Port index on which to operate
1272 *
1273 * Update the VLAN behavior of a port to make sure that when it is under
1274 * a VLAN filtering bridge, the port is either filtering with tag
1275 * preservation, or filtering with all VLANs egress-untagged. Otherwise,
1276 * the port ignores VLAN tags from packets and applies the port-based
1277 * VID.
1278 *
1279 * Must be called when changes are made to:
1280 * - the bridge VLAN filtering state of the port
1281 * - the number or attributes of VLANs from the bridge VLAN table,
1282 * while the port is currently VLAN-aware
1283 *
1284 * Return: 0 on success, or negative errno on error.
1285 */
vsc73xx_vlan_commit_conf(struct vsc73xx * vsc,int port)1286 static int vsc73xx_vlan_commit_conf(struct vsc73xx *vsc, int port)
1287 {
1288 enum vsc73xx_port_vlan_conf port_vlan_conf = VSC73XX_VLAN_IGNORE;
1289 struct dsa_port *dp = dsa_to_port(vsc->ds, port);
1290
1291 if (port == CPU_PORT) {
1292 port_vlan_conf = VSC73XX_VLAN_FILTER;
1293 } else if (dsa_port_is_vlan_filtering(dp)) {
1294 struct vsc73xx_vlan_summary summary;
1295
1296 port_vlan_conf = VSC73XX_VLAN_FILTER;
1297
1298 vsc73xx_bridge_vlan_summary(vsc, port, &summary, VLAN_N_VID);
1299 if (summary.num_tagged == 0)
1300 port_vlan_conf = VSC73XX_VLAN_FILTER_UNTAG_ALL;
1301 }
1302
1303 return vsc73xx_set_vlan_conf(vsc, port, port_vlan_conf);
1304 }
1305
1306 static int
vsc73xx_vlan_change_untagged(struct vsc73xx * vsc,int port,u16 vid,bool set)1307 vsc73xx_vlan_change_untagged(struct vsc73xx *vsc, int port, u16 vid, bool set)
1308 {
1309 u32 val = 0;
1310
1311 if (set)
1312 val = VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA |
1313 ((vid << VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_SHIFT) &
1314 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID);
1315
1316 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,
1317 VSC73XX_TXUPDCFG,
1318 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA |
1319 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID, val);
1320 }
1321
1322 /**
1323 * vsc73xx_vlan_commit_untagged - Update native VLAN of a port
1324 * @vsc: Switch private data structure
1325 * @port: Port index on which to operate
1326 *
1327 * Update the native VLAN of a port (the one VLAN which is transmitted
1328 * as egress-tagged on a trunk port) when port is in VLAN filtering mode and
1329 * only one untagged vid is configured.
1330 * In other cases no need to configure it because switch can untag all vlans on
1331 * the port.
1332 *
1333 * Return: 0 on success, or negative errno on error.
1334 */
vsc73xx_vlan_commit_untagged(struct vsc73xx * vsc,int port)1335 static int vsc73xx_vlan_commit_untagged(struct vsc73xx *vsc, int port)
1336 {
1337 struct dsa_port *dp = dsa_to_port(vsc->ds, port);
1338 struct vsc73xx_vlan_summary summary;
1339 u16 vid = 0;
1340 bool valid;
1341
1342 if (!dsa_port_is_vlan_filtering(dp))
1343 /* Port is configured to untag all vlans in that case.
1344 * No need to commit untagged config change.
1345 */
1346 return 0;
1347
1348 vsc73xx_bridge_vlan_summary(vsc, port, &summary, VLAN_N_VID);
1349
1350 if (summary.num_untagged > 1)
1351 /* Port must untag all vlans in that case.
1352 * No need to commit untagged config change.
1353 */
1354 return 0;
1355
1356 valid = (summary.num_untagged == 1);
1357 if (valid)
1358 vid = vsc73xx_find_first_vlan_untagged(vsc, port);
1359
1360 return vsc73xx_vlan_change_untagged(vsc, port, vid, valid);
1361 }
1362
1363 static int
vsc73xx_vlan_change_pvid(struct vsc73xx * vsc,int port,u16 vid,bool set)1364 vsc73xx_vlan_change_pvid(struct vsc73xx *vsc, int port, u16 vid, bool set)
1365 {
1366 u32 val = 0;
1367 int ret;
1368
1369 val = set ? 0 : VSC73XX_CAT_DROP_UNTAGGED_ENA;
1370
1371 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,
1372 VSC73XX_CAT_DROP,
1373 VSC73XX_CAT_DROP_UNTAGGED_ENA, val);
1374 if (!set || ret)
1375 return ret;
1376
1377 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,
1378 VSC73XX_CAT_PORT_VLAN,
1379 VSC73XX_CAT_PORT_VLAN_VLAN_VID,
1380 vid & VSC73XX_CAT_PORT_VLAN_VLAN_VID);
1381 }
1382
1383 /**
1384 * vsc73xx_vlan_commit_pvid - Update port-based default VLAN of a port
1385 * @vsc: Switch private data structure
1386 * @port: Port index on which to operate
1387 *
1388 * Update the PVID of a port so that it follows either the bridge PVID
1389 * configuration, when the bridge is currently VLAN-aware, or the PVID
1390 * from tag_8021q, when the port is standalone or under a VLAN-unaware
1391 * bridge. A port with no PVID drops all untagged and VID 0 tagged
1392 * traffic.
1393 *
1394 * Must be called when changes are made to:
1395 * - the bridge VLAN filtering state of the port
1396 * - the number or attributes of VLANs from the bridge VLAN table,
1397 * while the port is currently VLAN-aware
1398 *
1399 * Return: 0 on success, or negative errno on error.
1400 */
vsc73xx_vlan_commit_pvid(struct vsc73xx * vsc,int port)1401 static int vsc73xx_vlan_commit_pvid(struct vsc73xx *vsc, int port)
1402 {
1403 struct vsc73xx_portinfo *portinfo = &vsc->portinfo[port];
1404 bool valid = portinfo->pvid_tag_8021q_configured;
1405 struct dsa_port *dp = dsa_to_port(vsc->ds, port);
1406 u16 vid = portinfo->pvid_tag_8021q;
1407
1408 if (dsa_port_is_vlan_filtering(dp)) {
1409 vid = portinfo->pvid_vlan_filtering;
1410 valid = portinfo->pvid_vlan_filtering_configured;
1411 }
1412
1413 return vsc73xx_vlan_change_pvid(vsc, port, vid, valid);
1414 }
1415
vsc73xx_vlan_commit_settings(struct vsc73xx * vsc,int port)1416 static int vsc73xx_vlan_commit_settings(struct vsc73xx *vsc, int port)
1417 {
1418 int ret;
1419
1420 ret = vsc73xx_vlan_commit_untagged(vsc, port);
1421 if (ret)
1422 return ret;
1423
1424 ret = vsc73xx_vlan_commit_pvid(vsc, port);
1425 if (ret)
1426 return ret;
1427
1428 return vsc73xx_vlan_commit_conf(vsc, port);
1429 }
1430
vsc73xx_port_enable(struct dsa_switch * ds,int port,struct phy_device * phy)1431 static int vsc73xx_port_enable(struct dsa_switch *ds, int port,
1432 struct phy_device *phy)
1433 {
1434 struct vsc73xx *vsc = ds->priv;
1435
1436 dev_info(vsc->dev, "enable port %d\n", port);
1437 vsc73xx_init_port(vsc, port);
1438
1439 return vsc73xx_vlan_commit_settings(vsc, port);
1440 }
1441
vsc73xx_port_disable(struct dsa_switch * ds,int port)1442 static void vsc73xx_port_disable(struct dsa_switch *ds, int port)
1443 {
1444 struct vsc73xx *vsc = ds->priv;
1445
1446 /* Just put the port into reset */
1447 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port,
1448 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET);
1449 }
1450
1451 static const struct vsc73xx_counter *
vsc73xx_find_counter(struct vsc73xx * vsc,u8 counter,bool tx)1452 vsc73xx_find_counter(struct vsc73xx *vsc,
1453 u8 counter,
1454 bool tx)
1455 {
1456 const struct vsc73xx_counter *cnts;
1457 int num_cnts;
1458 int i;
1459
1460 if (tx) {
1461 cnts = vsc73xx_tx_counters;
1462 num_cnts = ARRAY_SIZE(vsc73xx_tx_counters);
1463 } else {
1464 cnts = vsc73xx_rx_counters;
1465 num_cnts = ARRAY_SIZE(vsc73xx_rx_counters);
1466 }
1467
1468 for (i = 0; i < num_cnts; i++) {
1469 const struct vsc73xx_counter *cnt;
1470
1471 cnt = &cnts[i];
1472 if (cnt->counter == counter)
1473 return cnt;
1474 }
1475
1476 return NULL;
1477 }
1478
vsc73xx_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)1479 static void vsc73xx_get_strings(struct dsa_switch *ds, int port, u32 stringset,
1480 uint8_t *data)
1481 {
1482 const struct vsc73xx_counter *cnt;
1483 struct vsc73xx *vsc = ds->priv;
1484 u8 indices[6];
1485 u8 *buf = data;
1486 int i;
1487 u32 val;
1488 int ret;
1489
1490 if (stringset != ETH_SS_STATS)
1491 return;
1492
1493 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port,
1494 VSC73XX_C_CFG, &val);
1495 if (ret)
1496 return;
1497
1498 indices[0] = (val & 0x1f); /* RX counter 0 */
1499 indices[1] = ((val >> 5) & 0x1f); /* RX counter 1 */
1500 indices[2] = ((val >> 10) & 0x1f); /* RX counter 2 */
1501 indices[3] = ((val >> 16) & 0x1f); /* TX counter 0 */
1502 indices[4] = ((val >> 21) & 0x1f); /* TX counter 1 */
1503 indices[5] = ((val >> 26) & 0x1f); /* TX counter 2 */
1504
1505 /* The first counters is the RX octets */
1506 ethtool_puts(&buf, "RxEtherStatsOctets");
1507
1508 /* Each port supports recording 3 RX counters and 3 TX counters,
1509 * figure out what counters we use in this set-up and return the
1510 * names of them. The hardware default counters will be number of
1511 * packets on RX/TX, combined broadcast+multicast packets RX/TX and
1512 * total error packets RX/TX.
1513 */
1514 for (i = 0; i < 3; i++) {
1515 cnt = vsc73xx_find_counter(vsc, indices[i], false);
1516 ethtool_puts(&buf, cnt ? cnt->name : "");
1517 }
1518
1519 /* TX stats begins with the number of TX octets */
1520 ethtool_puts(&buf, "TxEtherStatsOctets");
1521
1522 for (i = 3; i < 6; i++) {
1523 cnt = vsc73xx_find_counter(vsc, indices[i], true);
1524 ethtool_puts(&buf, cnt ? cnt->name : "");
1525
1526 }
1527 }
1528
vsc73xx_get_sset_count(struct dsa_switch * ds,int port,int sset)1529 static int vsc73xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1530 {
1531 /* We only support SS_STATS */
1532 if (sset != ETH_SS_STATS)
1533 return 0;
1534 /* RX and TX packets, then 3 RX counters, 3 TX counters */
1535 return 8;
1536 }
1537
vsc73xx_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1538 static void vsc73xx_get_ethtool_stats(struct dsa_switch *ds, int port,
1539 uint64_t *data)
1540 {
1541 struct vsc73xx *vsc = ds->priv;
1542 u8 regs[] = {
1543 VSC73XX_RXOCT,
1544 VSC73XX_C_RX0,
1545 VSC73XX_C_RX1,
1546 VSC73XX_C_RX2,
1547 VSC73XX_TXOCT,
1548 VSC73XX_C_TX0,
1549 VSC73XX_C_TX1,
1550 VSC73XX_C_TX2,
1551 };
1552 u32 val;
1553 int ret;
1554 int i;
1555
1556 for (i = 0; i < ARRAY_SIZE(regs); i++) {
1557 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port,
1558 regs[i], &val);
1559 if (ret) {
1560 dev_err(vsc->dev, "error reading counter %d\n", i);
1561 return;
1562 }
1563 data[i] = val;
1564 }
1565 }
1566
vsc73xx_change_mtu(struct dsa_switch * ds,int port,int new_mtu)1567 static int vsc73xx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1568 {
1569 struct vsc73xx *vsc = ds->priv;
1570
1571 return vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port,
1572 VSC73XX_MAXLEN, new_mtu + ETH_HLEN + ETH_FCS_LEN);
1573 }
1574
1575 /* According to application not "VSC7398 Jumbo Frames" setting
1576 * up the frame size to 9.6 KB does not affect the performance on standard
1577 * frames. It is clear from the application note that
1578 * "9.6 kilobytes" == 9600 bytes.
1579 */
vsc73xx_get_max_mtu(struct dsa_switch * ds,int port)1580 static int vsc73xx_get_max_mtu(struct dsa_switch *ds, int port)
1581 {
1582 return 9600 - ETH_HLEN - ETH_FCS_LEN;
1583 }
1584
vsc73xx_phylink_get_caps(struct dsa_switch * dsa,int port,struct phylink_config * config)1585 static void vsc73xx_phylink_get_caps(struct dsa_switch *dsa, int port,
1586 struct phylink_config *config)
1587 {
1588 unsigned long *interfaces = config->supported_interfaces;
1589
1590 if (port == 5)
1591 return;
1592
1593 if (port == CPU_PORT) {
1594 __set_bit(PHY_INTERFACE_MODE_MII, interfaces);
1595 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces);
1596 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
1597 __set_bit(PHY_INTERFACE_MODE_RGMII, interfaces);
1598 }
1599
1600 if (port <= 4) {
1601 /* Internal PHYs */
1602 __set_bit(PHY_INTERFACE_MODE_INTERNAL, interfaces);
1603 /* phylib default */
1604 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
1605 }
1606
1607 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000;
1608 }
1609
1610 static int
vsc73xx_port_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)1611 vsc73xx_port_vlan_filtering(struct dsa_switch *ds, int port,
1612 bool vlan_filtering, struct netlink_ext_ack *extack)
1613 {
1614 struct vsc73xx *vsc = ds->priv;
1615
1616 /* The commit to hardware processed below is required because vsc73xx
1617 * is using tag_8021q. When vlan_filtering is disabled, tag_8021q uses
1618 * pvid/untagged vlans for port recognition. The values configured for
1619 * vlans and pvid/untagged states are stored in portinfo structure.
1620 * When vlan_filtering is enabled, we need to restore pvid/untagged from
1621 * portinfo structure. Analogous routine is processed when
1622 * vlan_filtering is disabled, but values used for tag_8021q are
1623 * restored.
1624 */
1625
1626 return vsc73xx_vlan_commit_settings(vsc, port);
1627 }
1628
vsc73xx_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)1629 static int vsc73xx_port_vlan_add(struct dsa_switch *ds, int port,
1630 const struct switchdev_obj_port_vlan *vlan,
1631 struct netlink_ext_ack *extack)
1632 {
1633 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1634 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1635 struct dsa_port *dp = dsa_to_port(ds, port);
1636 struct vsc73xx_bridge_vlan *vsc73xx_vlan;
1637 struct vsc73xx_vlan_summary summary;
1638 struct vsc73xx_portinfo *portinfo;
1639 struct vsc73xx *vsc = ds->priv;
1640 bool commit_to_hardware;
1641 int ret = 0;
1642
1643 /* Be sure to deny alterations to the configuration done by tag_8021q.
1644 */
1645 if (vid_is_dsa_8021q(vlan->vid)) {
1646 NL_SET_ERR_MSG_MOD(extack,
1647 "Range 3072-4095 reserved for dsa_8021q operation");
1648 return -EBUSY;
1649 }
1650
1651 /* The processed vlan->vid is excluded from the search because the VLAN
1652 * can be re-added with a different set of flags, so it's easiest to
1653 * ignore its old flags from the VLAN database software copy.
1654 */
1655 vsc73xx_bridge_vlan_summary(vsc, port, &summary, vlan->vid);
1656
1657 /* VSC73XX allows only three untagged states: none, one or all */
1658 if ((untagged && summary.num_tagged > 0 && summary.num_untagged > 0) ||
1659 (!untagged && summary.num_untagged > 1)) {
1660 NL_SET_ERR_MSG_MOD(extack,
1661 "Port can have only none, one or all untagged vlan");
1662 return -EBUSY;
1663 }
1664
1665 vsc73xx_vlan = vsc73xx_bridge_vlan_find(vsc, vlan->vid);
1666
1667 if (!vsc73xx_vlan) {
1668 vsc73xx_vlan = kzalloc(sizeof(*vsc73xx_vlan), GFP_KERNEL);
1669 if (!vsc73xx_vlan)
1670 return -ENOMEM;
1671
1672 vsc73xx_vlan->vid = vlan->vid;
1673
1674 list_add_tail(&vsc73xx_vlan->list, &vsc->vlans);
1675 }
1676
1677 vsc73xx_vlan->portmask |= BIT(port);
1678
1679 /* CPU port must be always tagged because source port identification is
1680 * based on tag_8021q.
1681 */
1682 if (port == CPU_PORT)
1683 goto update_vlan_table;
1684
1685 if (untagged)
1686 vsc73xx_vlan->untagged |= BIT(port);
1687 else
1688 vsc73xx_vlan->untagged &= ~BIT(port);
1689
1690 portinfo = &vsc->portinfo[port];
1691
1692 if (pvid) {
1693 portinfo->pvid_vlan_filtering_configured = true;
1694 portinfo->pvid_vlan_filtering = vlan->vid;
1695 } else if (portinfo->pvid_vlan_filtering_configured &&
1696 portinfo->pvid_vlan_filtering == vlan->vid) {
1697 portinfo->pvid_vlan_filtering_configured = false;
1698 }
1699
1700 commit_to_hardware = !vsc73xx_tag_8021q_active(dp);
1701 if (commit_to_hardware) {
1702 ret = vsc73xx_vlan_commit_settings(vsc, port);
1703 if (ret)
1704 goto err;
1705 }
1706
1707 update_vlan_table:
1708 ret = vsc73xx_update_vlan_table(vsc, port, vlan->vid, true);
1709 if (!ret)
1710 return 0;
1711 err:
1712 vsc73xx_bridge_vlan_remove_port(vsc73xx_vlan, port);
1713 return ret;
1714 }
1715
vsc73xx_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1716 static int vsc73xx_port_vlan_del(struct dsa_switch *ds, int port,
1717 const struct switchdev_obj_port_vlan *vlan)
1718 {
1719 struct vsc73xx_bridge_vlan *vsc73xx_vlan;
1720 struct vsc73xx_portinfo *portinfo;
1721 struct vsc73xx *vsc = ds->priv;
1722 bool commit_to_hardware;
1723 int ret;
1724
1725 ret = vsc73xx_update_vlan_table(vsc, port, vlan->vid, false);
1726 if (ret)
1727 return ret;
1728
1729 portinfo = &vsc->portinfo[port];
1730
1731 if (portinfo->pvid_vlan_filtering_configured &&
1732 portinfo->pvid_vlan_filtering == vlan->vid)
1733 portinfo->pvid_vlan_filtering_configured = false;
1734
1735 vsc73xx_vlan = vsc73xx_bridge_vlan_find(vsc, vlan->vid);
1736
1737 if (vsc73xx_vlan)
1738 vsc73xx_bridge_vlan_remove_port(vsc73xx_vlan, port);
1739
1740 commit_to_hardware = !vsc73xx_tag_8021q_active(dsa_to_port(ds, port));
1741
1742 if (commit_to_hardware)
1743 return vsc73xx_vlan_commit_settings(vsc, port);
1744
1745 return 0;
1746 }
1747
vsc73xx_tag_8021q_vlan_add(struct dsa_switch * ds,int port,u16 vid,u16 flags)1748 static int vsc73xx_tag_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1749 u16 flags)
1750 {
1751 bool pvid = flags & BRIDGE_VLAN_INFO_PVID;
1752 struct vsc73xx_portinfo *portinfo;
1753 struct vsc73xx *vsc = ds->priv;
1754 bool commit_to_hardware;
1755 int ret;
1756
1757 portinfo = &vsc->portinfo[port];
1758
1759 if (pvid) {
1760 portinfo->pvid_tag_8021q_configured = true;
1761 portinfo->pvid_tag_8021q = vid;
1762 }
1763
1764 commit_to_hardware = vsc73xx_tag_8021q_active(dsa_to_port(ds, port));
1765 if (commit_to_hardware) {
1766 ret = vsc73xx_vlan_commit_settings(vsc, port);
1767 if (ret)
1768 return ret;
1769 }
1770
1771 return vsc73xx_update_vlan_table(vsc, port, vid, true);
1772 }
1773
vsc73xx_tag_8021q_vlan_del(struct dsa_switch * ds,int port,u16 vid)1774 static int vsc73xx_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid)
1775 {
1776 struct vsc73xx_portinfo *portinfo;
1777 struct vsc73xx *vsc = ds->priv;
1778
1779 portinfo = &vsc->portinfo[port];
1780
1781 if (portinfo->pvid_tag_8021q_configured &&
1782 portinfo->pvid_tag_8021q == vid) {
1783 struct dsa_port *dp = dsa_to_port(ds, port);
1784 bool commit_to_hardware;
1785 int err;
1786
1787 portinfo->pvid_tag_8021q_configured = false;
1788
1789 commit_to_hardware = vsc73xx_tag_8021q_active(dp);
1790 if (commit_to_hardware) {
1791 err = vsc73xx_vlan_commit_settings(vsc, port);
1792 if (err)
1793 return err;
1794 }
1795 }
1796
1797 return vsc73xx_update_vlan_table(vsc, port, vid, false);
1798 }
1799
vsc73xx_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)1800 static int vsc73xx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1801 struct switchdev_brport_flags flags,
1802 struct netlink_ext_ack *extack)
1803 {
1804 if (flags.mask & ~BR_LEARNING)
1805 return -EINVAL;
1806
1807 return 0;
1808 }
1809
vsc73xx_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)1810 static int vsc73xx_port_bridge_flags(struct dsa_switch *ds, int port,
1811 struct switchdev_brport_flags flags,
1812 struct netlink_ext_ack *extack)
1813 {
1814 if (flags.mask & BR_LEARNING) {
1815 u32 val = flags.val & BR_LEARNING ? BIT(port) : 0;
1816 struct vsc73xx *vsc = ds->priv;
1817
1818 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,
1819 VSC73XX_LEARNMASK, BIT(port), val);
1820 }
1821
1822 return 0;
1823 }
1824
vsc73xx_refresh_fwd_map(struct dsa_switch * ds,int port,u8 state)1825 static void vsc73xx_refresh_fwd_map(struct dsa_switch *ds, int port, u8 state)
1826 {
1827 struct dsa_port *other_dp, *dp = dsa_to_port(ds, port);
1828 struct vsc73xx *vsc = ds->priv;
1829 u16 mask;
1830
1831 if (state != BR_STATE_FORWARDING) {
1832 /* Ports that aren't in the forwarding state must not
1833 * forward packets anywhere.
1834 */
1835 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,
1836 VSC73XX_SRCMASKS + port,
1837 VSC73XX_SRCMASKS_PORTS_MASK, 0);
1838
1839 dsa_switch_for_each_available_port(other_dp, ds) {
1840 if (other_dp == dp)
1841 continue;
1842 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,
1843 VSC73XX_SRCMASKS + other_dp->index,
1844 BIT(port), 0);
1845 }
1846
1847 return;
1848 }
1849
1850 /* Forwarding ports must forward to the CPU and to other ports
1851 * in the same bridge
1852 */
1853 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,
1854 VSC73XX_SRCMASKS + CPU_PORT, BIT(port), BIT(port));
1855
1856 mask = BIT(CPU_PORT);
1857
1858 dsa_switch_for_each_user_port(other_dp, ds) {
1859 int other_port = other_dp->index;
1860
1861 if (port == other_port || !dsa_port_bridge_same(dp, other_dp) ||
1862 other_dp->stp_state != BR_STATE_FORWARDING)
1863 continue;
1864
1865 mask |= BIT(other_port);
1866
1867 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,
1868 VSC73XX_SRCMASKS + other_port,
1869 BIT(port), BIT(port));
1870 }
1871
1872 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,
1873 VSC73XX_SRCMASKS + port,
1874 VSC73XX_SRCMASKS_PORTS_MASK, mask);
1875 }
1876
1877 /* FIXME: STP frames aren't forwarded at this moment. BPDU frames are
1878 * forwarded only from and to PI/SI interface. For more info see chapter
1879 * 2.7.1 (CPU Forwarding) in datasheet.
1880 * This function is required for tag_8021q operations.
1881 */
vsc73xx_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)1882 static void vsc73xx_port_stp_state_set(struct dsa_switch *ds, int port,
1883 u8 state)
1884 {
1885 struct dsa_port *dp = dsa_to_port(ds, port);
1886 struct vsc73xx *vsc = ds->priv;
1887 u32 val = 0;
1888
1889 if (state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING)
1890 val = dp->learning ? BIT(port) : 0;
1891
1892 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,
1893 VSC73XX_LEARNMASK, BIT(port), val);
1894
1895 val = (state == BR_STATE_BLOCKING || state == BR_STATE_DISABLED) ?
1896 0 : BIT(port);
1897 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,
1898 VSC73XX_RECVMASK, BIT(port), val);
1899
1900 /* CPU Port should always forward packets when user ports are forwarding
1901 * so let's configure it from other ports only.
1902 */
1903 if (port != CPU_PORT)
1904 vsc73xx_refresh_fwd_map(ds, port, state);
1905 }
1906
vsc73xx_calc_hash(const unsigned char * addr,u16 vid)1907 static u16 vsc73xx_calc_hash(const unsigned char *addr, u16 vid)
1908 {
1909 /* VID 5-0, MAC 47-44 */
1910 u16 hash = FIELD_PREP(VSC73XX_HASH0_VID_TO_MASK,
1911 FIELD_GET(VSC73XX_HASH0_VID_FROM_MASK, vid)) |
1912 FIELD_PREP(VSC73XX_HASH0_MAC0_TO_MASK,
1913 FIELD_GET(VSC73XX_HASH0_MAC0_FROM_MASK, addr[0]));
1914 /* MAC 43-33 */
1915 hash ^= FIELD_PREP(VSC73XX_HASH1_MAC0_TO_MASK,
1916 FIELD_GET(VSC73XX_HASH1_MAC0_FROM_MASK, addr[0])) |
1917 FIELD_PREP(VSC73XX_HASH1_MAC1_TO_MASK,
1918 FIELD_GET(VSC73XX_HASH1_MAC1_FROM_MASK, addr[1]));
1919 /* MAC 32-22 */
1920 hash ^= FIELD_PREP(VSC73XX_HASH2_MAC1_TO_MASK,
1921 FIELD_GET(VSC73XX_HASH2_MAC1_FROM_MASK, addr[1])) |
1922 FIELD_PREP(VSC73XX_HASH2_MAC2_TO_MASK,
1923 FIELD_GET(VSC73XX_HASH2_MAC2_FROM_MASK, addr[2])) |
1924 FIELD_PREP(VSC73XX_HASH2_MAC3_TO_MASK,
1925 FIELD_GET(VSC73XX_HASH2_MAC3_FROM_MASK, addr[3]));
1926 /* MAC 21-11 */
1927 hash ^= FIELD_PREP(VSC73XX_HASH3_MAC3_TO_MASK,
1928 FIELD_GET(VSC73XX_HASH3_MAC3_FROM_MASK, addr[3])) |
1929 FIELD_PREP(VSC73XX_HASH3_MAC4_TO_MASK,
1930 FIELD_GET(VSC73XX_HASH3_MAC4_FROM_MASK, addr[4]));
1931 /* MAC 10-0 */
1932 hash ^= FIELD_PREP(VSC73XX_HASH4_MAC4_TO_MASK,
1933 FIELD_GET(VSC73XX_HASH4_MAC4_FROM_MASK, addr[4])) |
1934 addr[5];
1935
1936 return hash;
1937 }
1938
1939 static int
vsc73xx_port_wait_for_mac_table_cmd(struct vsc73xx * vsc)1940 vsc73xx_port_wait_for_mac_table_cmd(struct vsc73xx *vsc)
1941 {
1942 int ret, err;
1943 u32 val;
1944
1945 ret = read_poll_timeout(vsc73xx_read, err,
1946 err < 0 ||
1947 ((val & VSC73XX_MACACCESS_CMD_MASK) ==
1948 VSC73XX_MACACCESS_CMD_IDLE),
1949 VSC73XX_POLL_SLEEP_US, VSC73XX_POLL_TIMEOUT_US,
1950 false, vsc, VSC73XX_BLOCK_ANALYZER,
1951 0, VSC73XX_MACACCESS, &val);
1952 if (ret)
1953 return ret;
1954 return err;
1955 }
1956
vsc73xx_port_read_mac_table_row(struct vsc73xx * vsc,u16 index,struct vsc73xx_fdb * fdb)1957 static int vsc73xx_port_read_mac_table_row(struct vsc73xx *vsc, u16 index,
1958 struct vsc73xx_fdb *fdb)
1959 {
1960 int ret, i;
1961 u32 val;
1962
1963 if (!fdb)
1964 return -EINVAL;
1965 if (index >= VSC73XX_NUM_FDB_ROWS)
1966 return -EINVAL;
1967
1968 for (i = 0; i < VSC73XX_NUM_BUCKETS; i++) {
1969 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0,
1970 VSC73XX_MACTINDX,
1971 (i ? 0 : VSC73XX_MACTINDX_SHADOW) |
1972 FIELD_PREP(VSC73XX_MACTINDX_BUCKET_MSK, i) |
1973 index);
1974 if (ret)
1975 return ret;
1976
1977 ret = vsc73xx_port_wait_for_mac_table_cmd(vsc);
1978 if (ret)
1979 return ret;
1980
1981 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,
1982 VSC73XX_MACACCESS,
1983 VSC73XX_MACACCESS_CMD_MASK,
1984 VSC73XX_MACACCESS_CMD_READ_ENTRY);
1985 if (ret)
1986 return ret;
1987
1988 ret = vsc73xx_port_wait_for_mac_table_cmd(vsc);
1989 if (ret)
1990 return ret;
1991
1992 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_ANALYZER, 0,
1993 VSC73XX_MACACCESS, &val);
1994 if (ret)
1995 return ret;
1996
1997 fdb[i].valid = FIELD_GET(VSC73XX_MACACCESS_VALID, val);
1998 if (!fdb[i].valid)
1999 continue;
2000
2001 fdb[i].port = FIELD_GET(VSC73XX_MACACCESS_DEST_IDX_MASK, val);
2002
2003 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_ANALYZER, 0,
2004 VSC73XX_MACHDATA, &val);
2005 if (ret)
2006 return ret;
2007
2008 fdb[i].vid = FIELD_GET(VSC73XX_MACHDATA_VID, val);
2009 fdb[i].mac[0] = FIELD_GET(VSC73XX_MACHDATA_MAC0, val);
2010 fdb[i].mac[1] = FIELD_GET(VSC73XX_MACHDATA_MAC1, val);
2011
2012 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_ANALYZER, 0,
2013 VSC73XX_MACLDATA, &val);
2014 if (ret)
2015 return ret;
2016
2017 fdb[i].mac[2] = FIELD_GET(VSC73XX_MACLDATA_MAC2, val);
2018 fdb[i].mac[3] = FIELD_GET(VSC73XX_MACLDATA_MAC3, val);
2019 fdb[i].mac[4] = FIELD_GET(VSC73XX_MACLDATA_MAC4, val);
2020 fdb[i].mac[5] = FIELD_GET(VSC73XX_MACLDATA_MAC5, val);
2021 }
2022
2023 return ret;
2024 }
2025
2026 static int
vsc73xx_fdb_operation(struct vsc73xx * vsc,const unsigned char * addr,u16 vid,u16 hash,u16 cmd_mask,u16 cmd_val)2027 vsc73xx_fdb_operation(struct vsc73xx *vsc, const unsigned char *addr, u16 vid,
2028 u16 hash, u16 cmd_mask, u16 cmd_val)
2029 {
2030 int ret;
2031 u32 val;
2032
2033 val = FIELD_PREP(VSC73XX_MACHDATA_VID, vid) |
2034 FIELD_PREP(VSC73XX_MACHDATA_MAC0, addr[0]) |
2035 FIELD_PREP(VSC73XX_MACHDATA_MAC1, addr[1]);
2036 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_MACHDATA,
2037 val);
2038 if (ret)
2039 return ret;
2040
2041 val = FIELD_PREP(VSC73XX_MACLDATA_MAC2, addr[2]) |
2042 FIELD_PREP(VSC73XX_MACLDATA_MAC3, addr[3]) |
2043 FIELD_PREP(VSC73XX_MACLDATA_MAC4, addr[4]) |
2044 FIELD_PREP(VSC73XX_MACLDATA_MAC5, addr[5]);
2045 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_MACLDATA,
2046 val);
2047 if (ret)
2048 return ret;
2049
2050 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_MACTINDX,
2051 hash);
2052 if (ret)
2053 return ret;
2054
2055 ret = vsc73xx_port_wait_for_mac_table_cmd(vsc);
2056 if (ret)
2057 return ret;
2058
2059 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,
2060 VSC73XX_MACACCESS, cmd_mask, cmd_val);
2061 if (ret)
2062 return ret;
2063
2064 return vsc73xx_port_wait_for_mac_table_cmd(vsc);
2065 }
2066
vsc73xx_fdb_del_entry(struct vsc73xx * vsc,int port,const unsigned char * addr,u16 vid)2067 static int vsc73xx_fdb_del_entry(struct vsc73xx *vsc, int port,
2068 const unsigned char *addr, u16 vid)
2069 {
2070 struct vsc73xx_fdb fdb[VSC73XX_NUM_BUCKETS];
2071 u16 hash = vsc73xx_calc_hash(addr, vid);
2072 int bucket, ret;
2073
2074 mutex_lock(&vsc->fdb_lock);
2075
2076 ret = vsc73xx_port_read_mac_table_row(vsc, hash, fdb);
2077 if (ret)
2078 goto err;
2079
2080 for (bucket = 0; bucket < VSC73XX_NUM_BUCKETS; bucket++) {
2081 if (fdb[bucket].valid && fdb[bucket].port == port &&
2082 ether_addr_equal(addr, fdb[bucket].mac))
2083 break;
2084 }
2085
2086 if (bucket == VSC73XX_NUM_BUCKETS) {
2087 /* Can't find MAC in MAC table */
2088 ret = -ENODATA;
2089 goto err;
2090 }
2091
2092 ret = vsc73xx_fdb_operation(vsc, addr, vid, hash,
2093 VSC73XX_MACACCESS_CMD_MASK,
2094 VSC73XX_MACACCESS_CMD_FORGET);
2095 err:
2096 mutex_unlock(&vsc->fdb_lock);
2097 return ret;
2098 }
2099
vsc73xx_fdb_add_entry(struct vsc73xx * vsc,int port,const unsigned char * addr,u16 vid)2100 static int vsc73xx_fdb_add_entry(struct vsc73xx *vsc, int port,
2101 const unsigned char *addr, u16 vid)
2102 {
2103 struct vsc73xx_fdb fdb[VSC73XX_NUM_BUCKETS];
2104 u16 hash = vsc73xx_calc_hash(addr, vid);
2105 int bucket, ret;
2106 u32 val;
2107
2108 mutex_lock(&vsc->fdb_lock);
2109
2110 ret = vsc73xx_port_read_mac_table_row(vsc, hash, fdb);
2111 if (ret)
2112 goto err;
2113
2114 for (bucket = 0; bucket < VSC73XX_NUM_BUCKETS; bucket++) {
2115 if (!fdb[bucket].valid)
2116 break;
2117 }
2118
2119 if (bucket == VSC73XX_NUM_BUCKETS) {
2120 /* Bucket is full */
2121 ret = -EOVERFLOW;
2122 goto err;
2123 }
2124
2125 val = VSC73XX_MACACCESS_VALID | VSC73XX_MACACCESS_LOCKED |
2126 FIELD_PREP(VSC73XX_MACACCESS_DEST_IDX_MASK, port) |
2127 VSC73XX_MACACCESS_CMD_LEARN;
2128 ret = vsc73xx_fdb_operation(vsc, addr, vid, hash,
2129 VSC73XX_MACACCESS_VALID |
2130 VSC73XX_MACACCESS_LOCKED |
2131 VSC73XX_MACACCESS_DEST_IDX_MASK |
2132 VSC73XX_MACACCESS_CMD_MASK, val);
2133 err:
2134 mutex_unlock(&vsc->fdb_lock);
2135 return ret;
2136 }
2137
vsc73xx_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2138 static int vsc73xx_fdb_add(struct dsa_switch *ds, int port,
2139 const unsigned char *addr, u16 vid, struct dsa_db db)
2140 {
2141 struct vsc73xx *vsc = ds->priv;
2142
2143 if (!vid) {
2144 switch (db.type) {
2145 case DSA_DB_PORT:
2146 vid = dsa_tag_8021q_standalone_vid(db.dp);
2147 break;
2148 case DSA_DB_BRIDGE:
2149 vid = dsa_tag_8021q_bridge_vid(db.bridge.num);
2150 break;
2151 default:
2152 return -EOPNOTSUPP;
2153 }
2154 }
2155
2156 return vsc73xx_fdb_add_entry(vsc, port, addr, vid);
2157 }
2158
vsc73xx_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2159 static int vsc73xx_fdb_del(struct dsa_switch *ds, int port,
2160 const unsigned char *addr, u16 vid, struct dsa_db db)
2161 {
2162 struct vsc73xx *vsc = ds->priv;
2163
2164 if (!vid) {
2165 switch (db.type) {
2166 case DSA_DB_PORT:
2167 vid = dsa_tag_8021q_standalone_vid(db.dp);
2168 break;
2169 case DSA_DB_BRIDGE:
2170 vid = dsa_tag_8021q_bridge_vid(db.bridge.num);
2171 break;
2172 default:
2173 return -EOPNOTSUPP;
2174 }
2175 }
2176
2177 return vsc73xx_fdb_del_entry(vsc, port, addr, vid);
2178 }
2179
vsc73xx_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)2180 static int vsc73xx_port_fdb_dump(struct dsa_switch *ds,
2181 int port, dsa_fdb_dump_cb_t *cb, void *data)
2182 {
2183 struct vsc73xx_fdb fdb[VSC73XX_NUM_BUCKETS];
2184 struct vsc73xx *vsc = ds->priv;
2185 u16 i, bucket;
2186 int err = 0;
2187
2188 mutex_lock(&vsc->fdb_lock);
2189
2190 for (i = 0; i < VSC73XX_NUM_FDB_ROWS; i++) {
2191 err = vsc73xx_port_read_mac_table_row(vsc, i, fdb);
2192 if (err)
2193 goto unlock;
2194
2195 for (bucket = 0; bucket < VSC73XX_NUM_BUCKETS; bucket++) {
2196 if (!fdb[bucket].valid || fdb[bucket].port != port)
2197 continue;
2198
2199 /* We need to hide dsa_8021q VLANs from the user */
2200 if (vid_is_dsa_8021q(fdb[bucket].vid))
2201 fdb[bucket].vid = 0;
2202
2203 err = cb(fdb[bucket].mac, fdb[bucket].vid, false, data);
2204 if (err)
2205 goto unlock;
2206 }
2207 }
2208 unlock:
2209 mutex_unlock(&vsc->fdb_lock);
2210 return err;
2211 }
2212
2213 static const struct phylink_mac_ops vsc73xx_phylink_mac_ops = {
2214 .mac_config = vsc73xx_mac_config,
2215 .mac_link_down = vsc73xx_mac_link_down,
2216 .mac_link_up = vsc73xx_mac_link_up,
2217 };
2218
2219 static const struct dsa_switch_ops vsc73xx_ds_ops = {
2220 .get_tag_protocol = vsc73xx_get_tag_protocol,
2221 .setup = vsc73xx_setup,
2222 .teardown = vsc73xx_teardown,
2223 .phy_read = vsc73xx_phy_read,
2224 .phy_write = vsc73xx_phy_write,
2225 .get_strings = vsc73xx_get_strings,
2226 .get_ethtool_stats = vsc73xx_get_ethtool_stats,
2227 .get_sset_count = vsc73xx_get_sset_count,
2228 .port_enable = vsc73xx_port_enable,
2229 .port_disable = vsc73xx_port_disable,
2230 .port_pre_bridge_flags = vsc73xx_port_pre_bridge_flags,
2231 .port_bridge_flags = vsc73xx_port_bridge_flags,
2232 .port_bridge_join = dsa_tag_8021q_bridge_join,
2233 .port_bridge_leave = dsa_tag_8021q_bridge_leave,
2234 .port_change_mtu = vsc73xx_change_mtu,
2235 .port_fdb_add = vsc73xx_fdb_add,
2236 .port_fdb_del = vsc73xx_fdb_del,
2237 .port_fdb_dump = vsc73xx_port_fdb_dump,
2238 .port_max_mtu = vsc73xx_get_max_mtu,
2239 .port_stp_state_set = vsc73xx_port_stp_state_set,
2240 .port_vlan_filtering = vsc73xx_port_vlan_filtering,
2241 .port_vlan_add = vsc73xx_port_vlan_add,
2242 .port_vlan_del = vsc73xx_port_vlan_del,
2243 .phylink_get_caps = vsc73xx_phylink_get_caps,
2244 .tag_8021q_vlan_add = vsc73xx_tag_8021q_vlan_add,
2245 .tag_8021q_vlan_del = vsc73xx_tag_8021q_vlan_del,
2246 };
2247
vsc73xx_gpio_get(struct gpio_chip * chip,unsigned int offset)2248 static int vsc73xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
2249 {
2250 struct vsc73xx *vsc = gpiochip_get_data(chip);
2251 u32 val;
2252 int ret;
2253
2254 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
2255 VSC73XX_GPIO, &val);
2256 if (ret)
2257 return ret;
2258
2259 return !!(val & BIT(offset));
2260 }
2261
vsc73xx_gpio_set(struct gpio_chip * chip,unsigned int offset,int val)2262 static void vsc73xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
2263 int val)
2264 {
2265 struct vsc73xx *vsc = gpiochip_get_data(chip);
2266 u32 tmp = val ? BIT(offset) : 0;
2267
2268 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0,
2269 VSC73XX_GPIO, BIT(offset), tmp);
2270 }
2271
vsc73xx_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int val)2272 static int vsc73xx_gpio_direction_output(struct gpio_chip *chip,
2273 unsigned int offset, int val)
2274 {
2275 struct vsc73xx *vsc = gpiochip_get_data(chip);
2276 u32 tmp = val ? BIT(offset) : 0;
2277
2278 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0,
2279 VSC73XX_GPIO, BIT(offset + 4) | BIT(offset),
2280 BIT(offset + 4) | tmp);
2281 }
2282
vsc73xx_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)2283 static int vsc73xx_gpio_direction_input(struct gpio_chip *chip,
2284 unsigned int offset)
2285 {
2286 struct vsc73xx *vsc = gpiochip_get_data(chip);
2287
2288 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0,
2289 VSC73XX_GPIO, BIT(offset + 4),
2290 0);
2291 }
2292
vsc73xx_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)2293 static int vsc73xx_gpio_get_direction(struct gpio_chip *chip,
2294 unsigned int offset)
2295 {
2296 struct vsc73xx *vsc = gpiochip_get_data(chip);
2297 u32 val;
2298 int ret;
2299
2300 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
2301 VSC73XX_GPIO, &val);
2302 if (ret)
2303 return ret;
2304
2305 return !(val & BIT(offset + 4));
2306 }
2307
vsc73xx_gpio_probe(struct vsc73xx * vsc)2308 static int vsc73xx_gpio_probe(struct vsc73xx *vsc)
2309 {
2310 int ret;
2311
2312 vsc->gc.label = devm_kasprintf(vsc->dev, GFP_KERNEL, "VSC%04x",
2313 vsc->chipid);
2314 if (!vsc->gc.label)
2315 return -ENOMEM;
2316 vsc->gc.ngpio = 4;
2317 vsc->gc.owner = THIS_MODULE;
2318 vsc->gc.parent = vsc->dev;
2319 vsc->gc.base = -1;
2320 vsc->gc.get = vsc73xx_gpio_get;
2321 vsc->gc.set = vsc73xx_gpio_set;
2322 vsc->gc.direction_input = vsc73xx_gpio_direction_input;
2323 vsc->gc.direction_output = vsc73xx_gpio_direction_output;
2324 vsc->gc.get_direction = vsc73xx_gpio_get_direction;
2325 vsc->gc.can_sleep = true;
2326 ret = devm_gpiochip_add_data(vsc->dev, &vsc->gc, vsc);
2327 if (ret) {
2328 dev_err(vsc->dev, "unable to register GPIO chip\n");
2329 return ret;
2330 }
2331 return 0;
2332 }
2333
vsc73xx_probe(struct vsc73xx * vsc)2334 int vsc73xx_probe(struct vsc73xx *vsc)
2335 {
2336 struct device *dev = vsc->dev;
2337 int ret;
2338
2339 /* Release reset, if any */
2340 vsc->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
2341 if (IS_ERR(vsc->reset)) {
2342 dev_err(dev, "failed to get RESET GPIO\n");
2343 return PTR_ERR(vsc->reset);
2344 }
2345 if (vsc->reset)
2346 /* Wait 20ms according to datasheet table 245 */
2347 msleep(20);
2348
2349 ret = vsc73xx_detect(vsc);
2350 if (ret == -EAGAIN) {
2351 dev_err(vsc->dev,
2352 "Chip seems to be out of control. Assert reset and try again.\n");
2353 gpiod_set_value_cansleep(vsc->reset, 1);
2354 /* Reset pulse should be 20ns minimum, according to datasheet
2355 * table 245, so 10us should be fine
2356 */
2357 usleep_range(10, 100);
2358 gpiod_set_value_cansleep(vsc->reset, 0);
2359 /* Wait 20ms according to datasheet table 245 */
2360 msleep(20);
2361 ret = vsc73xx_detect(vsc);
2362 }
2363 if (ret) {
2364 dev_err(dev, "no chip found (%d)\n", ret);
2365 return -ENODEV;
2366 }
2367
2368 mutex_init(&vsc->fdb_lock);
2369
2370 eth_random_addr(vsc->addr);
2371 dev_info(vsc->dev,
2372 "MAC for control frames: %02X:%02X:%02X:%02X:%02X:%02X\n",
2373 vsc->addr[0], vsc->addr[1], vsc->addr[2],
2374 vsc->addr[3], vsc->addr[4], vsc->addr[5]);
2375
2376 vsc->ds = devm_kzalloc(dev, sizeof(*vsc->ds), GFP_KERNEL);
2377 if (!vsc->ds)
2378 return -ENOMEM;
2379
2380 vsc->ds->dev = dev;
2381 vsc->ds->num_ports = VSC73XX_MAX_NUM_PORTS;
2382 vsc->ds->priv = vsc;
2383
2384 vsc->ds->ops = &vsc73xx_ds_ops;
2385 vsc->ds->phylink_mac_ops = &vsc73xx_phylink_mac_ops;
2386 ret = dsa_register_switch(vsc->ds);
2387 if (ret) {
2388 dev_err(dev, "unable to register switch (%d)\n", ret);
2389 return ret;
2390 }
2391
2392 ret = vsc73xx_gpio_probe(vsc);
2393 if (ret) {
2394 dsa_unregister_switch(vsc->ds);
2395 return ret;
2396 }
2397
2398 return 0;
2399 }
2400 EXPORT_SYMBOL(vsc73xx_probe);
2401
vsc73xx_remove(struct vsc73xx * vsc)2402 void vsc73xx_remove(struct vsc73xx *vsc)
2403 {
2404 dsa_unregister_switch(vsc->ds);
2405 gpiod_set_value(vsc->reset, 1);
2406 }
2407 EXPORT_SYMBOL(vsc73xx_remove);
2408
vsc73xx_shutdown(struct vsc73xx * vsc)2409 void vsc73xx_shutdown(struct vsc73xx *vsc)
2410 {
2411 dsa_switch_shutdown(vsc->ds);
2412 }
2413 EXPORT_SYMBOL(vsc73xx_shutdown);
2414
2415 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
2416 MODULE_DESCRIPTION("Vitesse VSC7385/7388/7395/7398 driver");
2417 MODULE_LICENSE("GPL v2");
2418