1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _vpe_6_1_0_SH_MASK_HEADER 24 #define _vpe_6_1_0_SH_MASK_HEADER 25 26 27 // addressBlock: vpe_vpedec 28 //VPEC_DEC_START 29 #define VPEC_DEC_START__START__SHIFT 0x0 30 #define VPEC_DEC_START__START_MASK 0xFFFFFFFFL 31 //VPEC_UCODE_ADDR 32 #define VPEC_UCODE_ADDR__VALUE__SHIFT 0x0 33 #define VPEC_UCODE_ADDR__THID__SHIFT 0xf 34 #define VPEC_UCODE_ADDR__VALUE_MASK 0x00001FFFL 35 #define VPEC_UCODE_ADDR__THID_MASK 0x00008000L 36 //VPEC_UCODE_DATA 37 #define VPEC_UCODE_DATA__VALUE__SHIFT 0x0 38 #define VPEC_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 39 //VPEC_F32_CNTL 40 #define VPEC_F32_CNTL__HALT__SHIFT 0x0 41 #define VPEC_F32_CNTL__TH0_CHECKSUM_CLR__SHIFT 0x8 42 #define VPEC_F32_CNTL__TH0_RESET__SHIFT 0x9 43 #define VPEC_F32_CNTL__TH0_ENABLE__SHIFT 0xa 44 #define VPEC_F32_CNTL__TH1_CHECKSUM_CLR__SHIFT 0xc 45 #define VPEC_F32_CNTL__TH1_RESET__SHIFT 0xd 46 #define VPEC_F32_CNTL__TH1_ENABLE__SHIFT 0xe 47 #define VPEC_F32_CNTL__TH0_PRIORITY__SHIFT 0x10 48 #define VPEC_F32_CNTL__TH1_PRIORITY__SHIFT 0x18 49 #define VPEC_F32_CNTL__HALT_MASK 0x00000001L 50 #define VPEC_F32_CNTL__TH0_CHECKSUM_CLR_MASK 0x00000100L 51 #define VPEC_F32_CNTL__TH0_RESET_MASK 0x00000200L 52 #define VPEC_F32_CNTL__TH0_ENABLE_MASK 0x00000400L 53 #define VPEC_F32_CNTL__TH1_CHECKSUM_CLR_MASK 0x00001000L 54 #define VPEC_F32_CNTL__TH1_RESET_MASK 0x00002000L 55 #define VPEC_F32_CNTL__TH1_ENABLE_MASK 0x00004000L 56 #define VPEC_F32_CNTL__TH0_PRIORITY_MASK 0x00FF0000L 57 #define VPEC_F32_CNTL__TH1_PRIORITY_MASK 0xFF000000L 58 //VPEC_VPEP_CTRL 59 #define VPEC_VPEP_CTRL__VPEP_SOCCLK_EN__SHIFT 0x0 60 #define VPEC_VPEP_CTRL__VPEP_SW_RESETB__SHIFT 0x1 61 #define VPEC_VPEP_CTRL__RESERVED__SHIFT 0x2 62 #define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEP_SOCCLK__SHIFT 0x1e 63 #define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPECLK__SHIFT 0x1f 64 #define VPEC_VPEP_CTRL__VPEP_SOCCLK_EN_MASK 0x00000001L 65 #define VPEC_VPEP_CTRL__VPEP_SW_RESETB_MASK 0x00000002L 66 #define VPEC_VPEP_CTRL__RESERVED_MASK 0x3FFFFFFCL 67 #define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEP_SOCCLK_MASK 0x40000000L 68 #define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPECLK_MASK 0x80000000L 69 //VPEC_CLK_CTRL 70 #define VPEC_CLK_CTRL__VPECLK_EN__SHIFT 0x1 71 #define VPEC_CLK_CTRL__RESERVED__SHIFT 0x2 72 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE0_CLK__SHIFT 0x18 73 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE1_CLK__SHIFT 0x19 74 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE0_CLK__SHIFT 0x1a 75 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_PERF_CLK__SHIFT 0x1b 76 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_CE_CLK__SHIFT 0x1c 77 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_F32_CLK__SHIFT 0x1d 78 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_DYN_CLK__SHIFT 0x1e 79 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_REG_CLK__SHIFT 0x1f 80 #define VPEC_CLK_CTRL__VPECLK_EN_MASK 0x00000002L 81 #define VPEC_CLK_CTRL__RESERVED_MASK 0x00FFFFFCL 82 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE0_CLK_MASK 0x01000000L 83 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE1_CLK_MASK 0x02000000L 84 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE0_CLK_MASK 0x04000000L 85 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_PERF_CLK_MASK 0x08000000L 86 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_CE_CLK_MASK 0x10000000L 87 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_F32_CLK_MASK 0x20000000L 88 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_DYN_CLK_MASK 0x40000000L 89 #define VPEC_CLK_CTRL__SOFT_OVERRIDE_REG_CLK_MASK 0x80000000L 90 //VPEC_PG_CNTL 91 #define VPEC_PG_CNTL__PG_EN__SHIFT 0x0 92 #define VPEC_PG_CNTL__PG_HYSTERESIS__SHIFT 0x1 93 #define VPEC_PG_CNTL__PG_EN_MASK 0x00000001L 94 #define VPEC_PG_CNTL__PG_HYSTERESIS_MASK 0x0000003EL 95 //VPEC_POWER_CNTL 96 #define VPEC_POWER_CNTL__LS_ENABLE__SHIFT 0x8 97 #define VPEC_POWER_CNTL__LS_ENABLE_MASK 0x00000100L 98 //VPEC_CNTL 99 #define VPEC_CNTL__TRAP_ENABLE__SHIFT 0x0 100 #define VPEC_CNTL__RESERVED_2_2__SHIFT 0x2 101 #define VPEC_CNTL__DATA_SWAP__SHIFT 0x3 102 #define VPEC_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x5 103 #define VPEC_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x6 104 #define VPEC_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE__SHIFT 0x8 105 #define VPEC_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x9 106 #define VPEC_CNTL__UMSCH_INT_ENABLE__SHIFT 0xa 107 #define VPEC_CNTL__RESERVED_13_11__SHIFT 0xb 108 #define VPEC_CNTL__NACK_GEN_ERR_INT_ENABLE__SHIFT 0xe 109 #define VPEC_CNTL__NACK_PRT_INT_ENABLE__SHIFT 0xf 110 #define VPEC_CNTL__RESERVED_16_16__SHIFT 0x10 111 #define VPEC_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 112 #define VPEC_CNTL__RESERVED_19_19__SHIFT 0x13 113 #define VPEC_CNTL__ZSTATES_ENABLE__SHIFT 0x14 114 #define VPEC_CNTL__ZSTATES_HYSTERESIS__SHIFT 0x15 115 #define VPEC_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 116 #define VPEC_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 117 #define VPEC_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 118 #define VPEC_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT 0x1f 119 #define VPEC_CNTL__TRAP_ENABLE_MASK 0x00000001L 120 #define VPEC_CNTL__RESERVED_2_2_MASK 0x00000004L 121 #define VPEC_CNTL__DATA_SWAP_MASK 0x00000018L 122 #define VPEC_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000020L 123 #define VPEC_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000040L 124 #define VPEC_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE_MASK 0x00000100L 125 #define VPEC_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000200L 126 #define VPEC_CNTL__UMSCH_INT_ENABLE_MASK 0x00000400L 127 #define VPEC_CNTL__RESERVED_13_11_MASK 0x00003800L 128 #define VPEC_CNTL__NACK_GEN_ERR_INT_ENABLE_MASK 0x00004000L 129 #define VPEC_CNTL__NACK_PRT_INT_ENABLE_MASK 0x00008000L 130 #define VPEC_CNTL__RESERVED_16_16_MASK 0x00010000L 131 #define VPEC_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 132 #define VPEC_CNTL__RESERVED_19_19_MASK 0x00080000L 133 #define VPEC_CNTL__ZSTATES_ENABLE_MASK 0x00100000L 134 #define VPEC_CNTL__ZSTATES_HYSTERESIS_MASK 0x03E00000L 135 #define VPEC_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 136 #define VPEC_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 137 #define VPEC_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 138 #define VPEC_CNTL__RB_PREEMPT_INT_ENABLE_MASK 0x80000000L 139 //VPEC_CNTL1 140 #define VPEC_CNTL1__RESERVED_3_1__SHIFT 0x1 141 #define VPEC_CNTL1__SRBM_POLL_RETRYING__SHIFT 0x5 142 #define VPEC_CNTL1__RESERVED_23_10__SHIFT 0xa 143 #define VPEC_CNTL1__CG_STATUS_OUTPUT__SHIFT 0x18 144 #define VPEC_CNTL1__SW_FREEZE_ENABLE__SHIFT 0x19 145 #define VPEC_CNTL1__VPEP_CONFIG_INVALID_CHECK_ENABLE__SHIFT 0x1a 146 #define VPEC_CNTL1__RESERVED__SHIFT 0x1b 147 #define VPEC_CNTL1__RESERVED_3_1_MASK 0x0000000EL 148 #define VPEC_CNTL1__SRBM_POLL_RETRYING_MASK 0x00000020L 149 #define VPEC_CNTL1__RESERVED_23_10_MASK 0x00FFFC00L 150 #define VPEC_CNTL1__CG_STATUS_OUTPUT_MASK 0x01000000L 151 #define VPEC_CNTL1__SW_FREEZE_ENABLE_MASK 0x02000000L 152 #define VPEC_CNTL1__VPEP_CONFIG_INVALID_CHECK_ENABLE_MASK 0x04000000L 153 #define VPEC_CNTL1__RESERVED_MASK 0xF8000000L 154 //VPEC_CNTL2 155 #define VPEC_CNTL2__F32_CMD_PROC_DELAY__SHIFT 0x0 156 #define VPEC_CNTL2__F32_SEND_POSTCODE_EN__SHIFT 0x4 157 #define VPEC_CNTL2__UCODE_BUF_DS_EN__SHIFT 0x6 158 #define VPEC_CNTL2__UCODE_SELFLOAD_THREAD_OVERLAP__SHIFT 0x7 159 #define VPEC_CNTL2__RESERVED_11_8__SHIFT 0x8 160 #define VPEC_CNTL2__RESERVED_14_12__SHIFT 0xc 161 #define VPEC_CNTL2__RESERVED_15__SHIFT 0xf 162 #define VPEC_CNTL2__RB_FIFO_WATERMARK__SHIFT 0x10 163 #define VPEC_CNTL2__IB_FIFO_WATERMARK__SHIFT 0x12 164 #define VPEC_CNTL2__RESERVED_22_20__SHIFT 0x14 165 #define VPEC_CNTL2__CH_RD_WATERMARK__SHIFT 0x17 166 #define VPEC_CNTL2__CH_WR_WATERMARK__SHIFT 0x19 167 #define VPEC_CNTL2__CH_WR_WATERMARK_LSB__SHIFT 0x1e 168 #define VPEC_CNTL2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 169 #define VPEC_CNTL2__F32_SEND_POSTCODE_EN_MASK 0x00000010L 170 #define VPEC_CNTL2__UCODE_BUF_DS_EN_MASK 0x00000040L 171 #define VPEC_CNTL2__UCODE_SELFLOAD_THREAD_OVERLAP_MASK 0x00000080L 172 #define VPEC_CNTL2__RESERVED_11_8_MASK 0x00000F00L 173 #define VPEC_CNTL2__RESERVED_14_12_MASK 0x00007000L 174 #define VPEC_CNTL2__RESERVED_15_MASK 0x00008000L 175 #define VPEC_CNTL2__RB_FIFO_WATERMARK_MASK 0x00030000L 176 #define VPEC_CNTL2__IB_FIFO_WATERMARK_MASK 0x000C0000L 177 #define VPEC_CNTL2__RESERVED_22_20_MASK 0x00700000L 178 #define VPEC_CNTL2__CH_RD_WATERMARK_MASK 0x01800000L 179 #define VPEC_CNTL2__CH_WR_WATERMARK_MASK 0x3E000000L 180 #define VPEC_CNTL2__CH_WR_WATERMARK_LSB_MASK 0x40000000L 181 //VPEC_GB_ADDR_CONFIG 182 #define VPEC_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 183 #define VPEC_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 184 #define VPEC_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 185 #define VPEC_GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 186 #define VPEC_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 187 #define VPEC_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a 188 #define VPEC_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 189 #define VPEC_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 190 #define VPEC_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 191 #define VPEC_GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 192 #define VPEC_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 193 #define VPEC_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L 194 //VPEC_GB_ADDR_CONFIG_READ 195 #define VPEC_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 196 #define VPEC_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 197 #define VPEC_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 198 #define VPEC_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8 199 #define VPEC_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 200 #define VPEC_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a 201 #define VPEC_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 202 #define VPEC_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 203 #define VPEC_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 204 #define VPEC_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L 205 #define VPEC_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 206 #define VPEC_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L 207 //VPEC_PROCESS_QUANTUM0 208 #define VPEC_PROCESS_QUANTUM0__PROCESS0_QUANTUM__SHIFT 0x0 209 #define VPEC_PROCESS_QUANTUM0__PROCESS1_QUANTUM__SHIFT 0x8 210 #define VPEC_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT 0x10 211 #define VPEC_PROCESS_QUANTUM0__PROCESS3_QUANTUM__SHIFT 0x18 212 #define VPEC_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK 0x000000FFL 213 #define VPEC_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK 0x0000FF00L 214 #define VPEC_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK 0x00FF0000L 215 #define VPEC_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK 0xFF000000L 216 //VPEC_PROCESS_QUANTUM1 217 #define VPEC_PROCESS_QUANTUM1__PROCESS4_QUANTUM__SHIFT 0x0 218 #define VPEC_PROCESS_QUANTUM1__PROCESS5_QUANTUM__SHIFT 0x8 219 #define VPEC_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT 0x10 220 #define VPEC_PROCESS_QUANTUM1__PROCESS7_QUANTUM__SHIFT 0x18 221 #define VPEC_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK 0x000000FFL 222 #define VPEC_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK 0x0000FF00L 223 #define VPEC_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK 0x00FF0000L 224 #define VPEC_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK 0xFF000000L 225 //VPEC_CONTEXT_SWITCH_THRESHOLD 226 #define VPEC_CONTEXT_SWITCH_THRESHOLD__REALTIME_THRESHOLD__SHIFT 0x0 227 #define VPEC_CONTEXT_SWITCH_THRESHOLD__FOCUS_THRESHOLD__SHIFT 0x2 228 #define VPEC_CONTEXT_SWITCH_THRESHOLD__NORMAL_THRESHOLD__SHIFT 0x4 229 #define VPEC_CONTEXT_SWITCH_THRESHOLD__IDLE_THRESHOLD__SHIFT 0x6 230 #define VPEC_CONTEXT_SWITCH_THRESHOLD__REALTIME_THRESHOLD_MASK 0x00000003L 231 #define VPEC_CONTEXT_SWITCH_THRESHOLD__FOCUS_THRESHOLD_MASK 0x0000000CL 232 #define VPEC_CONTEXT_SWITCH_THRESHOLD__NORMAL_THRESHOLD_MASK 0x00000030L 233 #define VPEC_CONTEXT_SWITCH_THRESHOLD__IDLE_THRESHOLD_MASK 0x000000C0L 234 //VPEC_GLOBAL_QUANTUM 235 #define VPEC_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM__SHIFT 0x0 236 #define VPEC_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM__SHIFT 0x8 237 #define VPEC_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK 0x000000FFL 238 #define VPEC_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK 0x0000FF00L 239 //VPEC_WATCHDOG_CNTL 240 #define VPEC_WATCHDOG_CNTL__QUEUE_HANG_COUNT__SHIFT 0x0 241 #define VPEC_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT__SHIFT 0x8 242 #define VPEC_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK 0x000000FFL 243 #define VPEC_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK 0x0000FF00L 244 //VPEC_ATOMIC_CNTL 245 #define VPEC_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 246 #define VPEC_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 247 #define VPEC_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 248 #define VPEC_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 249 //VPEC_UCODE_VERSION 250 #define VPEC_UCODE_VERSION__T0_UCODE_VERSION__SHIFT 0x0 251 #define VPEC_UCODE_VERSION__T1_UCODE_VERSION__SHIFT 0x10 252 #define VPEC_UCODE_VERSION__T0_UCODE_VERSION_MASK 0x0000FFFFL 253 #define VPEC_UCODE_VERSION__T1_UCODE_VERSION_MASK 0xFFFF0000L 254 //VPEC_MEMREQ_BURST_CNTL 255 #define VPEC_MEMREQ_BURST_CNTL__DATA_RD_BURST__SHIFT 0x0 256 #define VPEC_MEMREQ_BURST_CNTL__DATA_WR_BURST__SHIFT 0x2 257 #define VPEC_MEMREQ_BURST_CNTL__RB_RD_BURST__SHIFT 0x4 258 #define VPEC_MEMREQ_BURST_CNTL__IB_RD_BURST__SHIFT 0x6 259 #define VPEC_MEMREQ_BURST_CNTL__WR_BURST_WAIT_CYCLE__SHIFT 0x8 260 #define VPEC_MEMREQ_BURST_CNTL__DATA_RD_BURST_MASK 0x00000003L 261 #define VPEC_MEMREQ_BURST_CNTL__DATA_WR_BURST_MASK 0x0000000CL 262 #define VPEC_MEMREQ_BURST_CNTL__RB_RD_BURST_MASK 0x00000030L 263 #define VPEC_MEMREQ_BURST_CNTL__IB_RD_BURST_MASK 0x000000C0L 264 #define VPEC_MEMREQ_BURST_CNTL__WR_BURST_WAIT_CYCLE_MASK 0x00000700L 265 //VPEC_TIMESTAMP_CNTL 266 #define VPEC_TIMESTAMP_CNTL__CAPTURE__SHIFT 0x0 267 #define VPEC_TIMESTAMP_CNTL__CAPTURE_MASK 0x00000001L 268 //VPEC_GLOBAL_TIMESTAMP_LO 269 #define VPEC_GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0 270 #define VPEC_GLOBAL_TIMESTAMP_LO__DATA_MASK 0xFFFFFFFFL 271 //VPEC_GLOBAL_TIMESTAMP_HI 272 #define VPEC_GLOBAL_TIMESTAMP_HI__DATA__SHIFT 0x0 273 #define VPEC_GLOBAL_TIMESTAMP_HI__DATA_MASK 0xFFFFFFFFL 274 //VPEC_FREEZE 275 #define VPEC_FREEZE__PREEMPT__SHIFT 0x0 276 #define VPEC_FREEZE__FREEZE__SHIFT 0x4 277 #define VPEC_FREEZE__FROZEN__SHIFT 0x5 278 #define VPEC_FREEZE__F32_FREEZE__SHIFT 0x6 279 #define VPEC_FREEZE__PREEMPT_MASK 0x00000001L 280 #define VPEC_FREEZE__FREEZE_MASK 0x00000010L 281 #define VPEC_FREEZE__FROZEN_MASK 0x00000020L 282 #define VPEC_FREEZE__F32_FREEZE_MASK 0x00000040L 283 //VPEC_CE_CTRL 284 #define VPEC_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 285 #define VPEC_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 286 #define VPEC_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 287 #define VPEC_CE_CTRL__RESERVED__SHIFT 0x8 288 #define VPEC_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L 289 #define VPEC_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L 290 #define VPEC_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L 291 #define VPEC_CE_CTRL__RESERVED_MASK 0xFFFFFF00L 292 //VPEC_RELAX_ORDERING_LUT 293 #define VPEC_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 294 #define VPEC_RELAX_ORDERING_LUT__VPE__SHIFT 0x1 295 #define VPEC_RELAX_ORDERING_LUT__RESERVED_2_2__SHIFT 0x2 296 #define VPEC_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 297 #define VPEC_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 298 #define VPEC_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 299 #define VPEC_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 300 #define VPEC_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 301 #define VPEC_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 302 #define VPEC_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 303 #define VPEC_RELAX_ORDERING_LUT__RESERVED_11_11__SHIFT 0xb 304 #define VPEC_RELAX_ORDERING_LUT__RESERVED_12_12__SHIFT 0xc 305 #define VPEC_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 306 #define VPEC_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 307 #define VPEC_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 308 #define VPEC_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 309 #define VPEC_RELAX_ORDERING_LUT__RESERVED_29_29__SHIFT 0x1d 310 #define VPEC_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 311 #define VPEC_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 312 #define VPEC_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 313 #define VPEC_RELAX_ORDERING_LUT__VPE_MASK 0x00000002L 314 #define VPEC_RELAX_ORDERING_LUT__RESERVED_2_2_MASK 0x00000004L 315 #define VPEC_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 316 #define VPEC_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 317 #define VPEC_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 318 #define VPEC_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 319 #define VPEC_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 320 #define VPEC_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 321 #define VPEC_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 322 #define VPEC_RELAX_ORDERING_LUT__RESERVED_11_11_MASK 0x00000800L 323 #define VPEC_RELAX_ORDERING_LUT__RESERVED_12_12_MASK 0x00001000L 324 #define VPEC_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 325 #define VPEC_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 326 #define VPEC_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 327 #define VPEC_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 328 #define VPEC_RELAX_ORDERING_LUT__RESERVED_29_29_MASK 0x20000000L 329 #define VPEC_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 330 #define VPEC_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 331 //VPEC_CREDIT_CNTL 332 #define VPEC_CREDIT_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 333 #define VPEC_CREDIT_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 334 #define VPEC_CREDIT_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 335 #define VPEC_CREDIT_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 336 //VPEC_SCRATCH_RAM_DATA 337 #define VPEC_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 338 #define VPEC_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL 339 //VPEC_SCRATCH_RAM_ADDR 340 #define VPEC_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 341 #define VPEC_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL 342 //VPEC_QUEUE_RESET_REQ 343 #define VPEC_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT 0x0 344 #define VPEC_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT 0x1 345 #define VPEC_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT 0x2 346 #define VPEC_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT 0x3 347 #define VPEC_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT 0x4 348 #define VPEC_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT 0x5 349 #define VPEC_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT 0x6 350 #define VPEC_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT 0x7 351 #define VPEC_QUEUE_RESET_REQ__RESERVED__SHIFT 0x8 352 #define VPEC_QUEUE_RESET_REQ__QUEUE0_RESET_MASK 0x00000001L 353 #define VPEC_QUEUE_RESET_REQ__QUEUE1_RESET_MASK 0x00000002L 354 #define VPEC_QUEUE_RESET_REQ__QUEUE2_RESET_MASK 0x00000004L 355 #define VPEC_QUEUE_RESET_REQ__QUEUE3_RESET_MASK 0x00000008L 356 #define VPEC_QUEUE_RESET_REQ__QUEUE4_RESET_MASK 0x00000010L 357 #define VPEC_QUEUE_RESET_REQ__QUEUE5_RESET_MASK 0x00000020L 358 #define VPEC_QUEUE_RESET_REQ__QUEUE6_RESET_MASK 0x00000040L 359 #define VPEC_QUEUE_RESET_REQ__QUEUE7_RESET_MASK 0x00000080L 360 #define VPEC_QUEUE_RESET_REQ__RESERVED_MASK 0xFFFFFF00L 361 //VPEC_PERFCNT_PERFCOUNTER0_CFG 362 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 363 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 364 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 365 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 366 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 367 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 368 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 369 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 370 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 371 #define VPEC_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 372 //VPEC_PERFCNT_PERFCOUNTER1_CFG 373 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 374 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 375 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 376 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 377 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 378 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 379 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 380 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 381 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 382 #define VPEC_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 383 //VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL 384 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 385 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 386 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 387 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 388 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 389 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 390 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 391 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 392 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 393 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 394 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 395 #define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 396 //VPEC_PERFCNT_MISC_CNTL 397 #define VPEC_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 398 #define VPEC_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT__SHIFT 0x10 399 #define VPEC_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL 400 #define VPEC_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT_MASK 0x00010000L 401 //VPEC_PERFCNT_PERFCOUNTER_LO 402 #define VPEC_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 403 #define VPEC_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 404 //VPEC_PERFCNT_PERFCOUNTER_HI 405 #define VPEC_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 406 #define VPEC_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 407 #define VPEC_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 408 #define VPEC_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 409 //VPEC_CRC_CTRL 410 #define VPEC_CRC_CTRL__INDEX__SHIFT 0x0 411 #define VPEC_CRC_CTRL__START__SHIFT 0x1f 412 #define VPEC_CRC_CTRL__INDEX_MASK 0x0000FFFFL 413 #define VPEC_CRC_CTRL__START_MASK 0x80000000L 414 //VPEC_CRC_DATA 415 #define VPEC_CRC_DATA__DATA__SHIFT 0x0 416 #define VPEC_CRC_DATA__DATA_MASK 0xFFFFFFFFL 417 //VPEC_PUB_DUMMY0 418 #define VPEC_PUB_DUMMY0__VALUE__SHIFT 0x0 419 #define VPEC_PUB_DUMMY0__VALUE_MASK 0xFFFFFFFFL 420 //VPEC_PUB_DUMMY1 421 #define VPEC_PUB_DUMMY1__VALUE__SHIFT 0x0 422 #define VPEC_PUB_DUMMY1__VALUE_MASK 0xFFFFFFFFL 423 //VPEC_PUB_DUMMY2 424 #define VPEC_PUB_DUMMY2__VALUE__SHIFT 0x0 425 #define VPEC_PUB_DUMMY2__VALUE_MASK 0xFFFFFFFFL 426 //VPEC_PUB_DUMMY3 427 #define VPEC_PUB_DUMMY3__VALUE__SHIFT 0x0 428 #define VPEC_PUB_DUMMY3__VALUE_MASK 0xFFFFFFFFL 429 //VPEC_PUB_DUMMY4 430 #define VPEC_PUB_DUMMY4__VALUE__SHIFT 0x0 431 #define VPEC_PUB_DUMMY4__VALUE_MASK 0xFFFFFFFFL 432 //VPEC_PUB_DUMMY5 433 #define VPEC_PUB_DUMMY5__VALUE__SHIFT 0x0 434 #define VPEC_PUB_DUMMY5__VALUE_MASK 0xFFFFFFFFL 435 //VPEC_PUB_DUMMY6 436 #define VPEC_PUB_DUMMY6__VALUE__SHIFT 0x0 437 #define VPEC_PUB_DUMMY6__VALUE_MASK 0xFFFFFFFFL 438 //VPEC_PUB_DUMMY7 439 #define VPEC_PUB_DUMMY7__VALUE__SHIFT 0x0 440 #define VPEC_PUB_DUMMY7__VALUE_MASK 0xFFFFFFFFL 441 //VPEC_UCODE1_CHECKSUM 442 #define VPEC_UCODE1_CHECKSUM__DATA__SHIFT 0x0 443 #define VPEC_UCODE1_CHECKSUM__DATA_MASK 0xFFFFFFFFL 444 //VPEC_VERSION 445 #define VPEC_VERSION__MINVER__SHIFT 0x0 446 #define VPEC_VERSION__MAJVER__SHIFT 0x8 447 #define VPEC_VERSION__REV__SHIFT 0x10 448 #define VPEC_VERSION__MINVER_MASK 0x0000007FL 449 #define VPEC_VERSION__MAJVER_MASK 0x00007F00L 450 #define VPEC_VERSION__REV_MASK 0x003F0000L 451 //VPEC_UCODE_CHECKSUM 452 #define VPEC_UCODE_CHECKSUM__DATA__SHIFT 0x0 453 #define VPEC_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 454 //VPEC_CLOCK_GATING_STATUS 455 #define VPEC_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS__SHIFT 0x0 456 #define VPEC_CLOCK_GATING_STATUS__IP_PIPE0_CLK_GATE_STATUS__SHIFT 0x2 457 #define VPEC_CLOCK_GATING_STATUS__IP_PIPE1_CLK_GATE_STATUS__SHIFT 0x3 458 #define VPEC_CLOCK_GATING_STATUS__OP_PIPE0_CLK_GATE_STATUS__SHIFT 0x4 459 #define VPEC_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS__SHIFT 0x5 460 #define VPEC_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS__SHIFT 0x6 461 #define VPEC_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS_MASK 0x00000001L 462 #define VPEC_CLOCK_GATING_STATUS__IP_PIPE0_CLK_GATE_STATUS_MASK 0x00000004L 463 #define VPEC_CLOCK_GATING_STATUS__IP_PIPE1_CLK_GATE_STATUS_MASK 0x00000008L 464 #define VPEC_CLOCK_GATING_STATUS__OP_PIPE0_CLK_GATE_STATUS_MASK 0x00000010L 465 #define VPEC_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS_MASK 0x00000020L 466 #define VPEC_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS_MASK 0x00000040L 467 //VPEC_RB_RPTR_FETCH 468 #define VPEC_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 469 #define VPEC_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 470 //VPEC_RB_RPTR_FETCH_HI 471 #define VPEC_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 472 #define VPEC_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 473 //VPEC_IB_OFFSET_FETCH 474 #define VPEC_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 475 #define VPEC_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 476 //VPEC_CMDIB_OFFSET_FETCH 477 #define VPEC_CMDIB_OFFSET_FETCH__OFFSET__SHIFT 0x2 478 #define VPEC_CMDIB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 479 //VPEC_ATOMIC_PREOP_LO 480 #define VPEC_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 481 #define VPEC_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 482 //VPEC_ATOMIC_PREOP_HI 483 #define VPEC_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 484 #define VPEC_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 485 //VPEC_CE_BUSY 486 #define VPEC_CE_BUSY__CE_IP_PIPE0_BUSY__SHIFT 0x0 487 #define VPEC_CE_BUSY__CE_IP_PIPE1_BUSY__SHIFT 0x1 488 #define VPEC_CE_BUSY__CE_OP_PIPE0_BUSY__SHIFT 0x10 489 #define VPEC_CE_BUSY__CE_IP_PIPE0_BUSY_MASK 0x00000001L 490 #define VPEC_CE_BUSY__CE_IP_PIPE1_BUSY_MASK 0x00000002L 491 #define VPEC_CE_BUSY__CE_OP_PIPE0_BUSY_MASK 0x00010000L 492 //VPEC_F32_COUNTER 493 #define VPEC_F32_COUNTER__VALUE__SHIFT 0x0 494 #define VPEC_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 495 //VPEC_HOLE_ADDR_LO 496 #define VPEC_HOLE_ADDR_LO__VALUE__SHIFT 0x0 497 #define VPEC_HOLE_ADDR_LO__VALUE_MASK 0xFFFFFFFFL 498 //VPEC_HOLE_ADDR_HI 499 #define VPEC_HOLE_ADDR_HI__VALUE__SHIFT 0x0 500 #define VPEC_HOLE_ADDR_HI__VALUE_MASK 0xFFFFFFFFL 501 //VPEC_ERROR_LOG 502 //VPEC_INT_STATUS 503 #define VPEC_INT_STATUS__DATA__SHIFT 0x0 504 #define VPEC_INT_STATUS__DATA_MASK 0xFFFFFFFFL 505 //VPEC_STATUS 506 #define VPEC_STATUS__IDLE__SHIFT 0x0 507 #define VPEC_STATUS__REG_IDLE__SHIFT 0x1 508 #define VPEC_STATUS__RB_EMPTY__SHIFT 0x2 509 #define VPEC_STATUS__RB_FULL__SHIFT 0x3 510 #define VPEC_STATUS__RB_CMD_IDLE__SHIFT 0x4 511 #define VPEC_STATUS__RB_CMD_FULL__SHIFT 0x5 512 #define VPEC_STATUS__IB_CMD_IDLE__SHIFT 0x6 513 #define VPEC_STATUS__IB_CMD_FULL__SHIFT 0x7 514 #define VPEC_STATUS__BLOCK_IDLE__SHIFT 0x8 515 #define VPEC_STATUS__INSIDE_VPEP_CONFIG__SHIFT 0x9 516 #define VPEC_STATUS__EX_IDLE__SHIFT 0xa 517 #define VPEC_STATUS__RESERVED_11_11__SHIFT 0xb 518 #define VPEC_STATUS__PACKET_READY__SHIFT 0xc 519 #define VPEC_STATUS__MC_WR_IDLE__SHIFT 0xd 520 #define VPEC_STATUS__SRBM_IDLE__SHIFT 0xe 521 #define VPEC_STATUS__CONTEXT_EMPTY__SHIFT 0xf 522 #define VPEC_STATUS__INSIDE_IB__SHIFT 0x10 523 #define VPEC_STATUS__RB_MC_RREQ_IDLE__SHIFT 0x11 524 #define VPEC_STATUS__IB_MC_RREQ_IDLE__SHIFT 0x12 525 #define VPEC_STATUS__MC_RD_IDLE__SHIFT 0x13 526 #define VPEC_STATUS__DELTA_RPTR_EMPTY__SHIFT 0x14 527 #define VPEC_STATUS__MC_RD_RET_STALL__SHIFT 0x15 528 #define VPEC_STATUS__RESERVED_22_22__SHIFT 0x16 529 #define VPEC_STATUS__RESERVED_23_23__SHIFT 0x17 530 #define VPEC_STATUS__RESERVED_24_24__SHIFT 0x18 531 #define VPEC_STATUS__PREV_CMD_IDLE__SHIFT 0x19 532 #define VPEC_STATUS__RESERVED_26_26__SHIFT 0x1a 533 #define VPEC_STATUS__RESERVED_27_27__SHIFT 0x1b 534 #define VPEC_STATUS__RESERVED_29_28__SHIFT 0x1c 535 #define VPEC_STATUS__INT_IDLE__SHIFT 0x1e 536 #define VPEC_STATUS__INT_REQ_STALL__SHIFT 0x1f 537 #define VPEC_STATUS__IDLE_MASK 0x00000001L 538 #define VPEC_STATUS__REG_IDLE_MASK 0x00000002L 539 #define VPEC_STATUS__RB_EMPTY_MASK 0x00000004L 540 #define VPEC_STATUS__RB_FULL_MASK 0x00000008L 541 #define VPEC_STATUS__RB_CMD_IDLE_MASK 0x00000010L 542 #define VPEC_STATUS__RB_CMD_FULL_MASK 0x00000020L 543 #define VPEC_STATUS__IB_CMD_IDLE_MASK 0x00000040L 544 #define VPEC_STATUS__IB_CMD_FULL_MASK 0x00000080L 545 #define VPEC_STATUS__BLOCK_IDLE_MASK 0x00000100L 546 #define VPEC_STATUS__INSIDE_VPEP_CONFIG_MASK 0x00000200L 547 #define VPEC_STATUS__EX_IDLE_MASK 0x00000400L 548 #define VPEC_STATUS__RESERVED_11_11_MASK 0x00000800L 549 #define VPEC_STATUS__PACKET_READY_MASK 0x00001000L 550 #define VPEC_STATUS__MC_WR_IDLE_MASK 0x00002000L 551 #define VPEC_STATUS__SRBM_IDLE_MASK 0x00004000L 552 #define VPEC_STATUS__CONTEXT_EMPTY_MASK 0x00008000L 553 #define VPEC_STATUS__INSIDE_IB_MASK 0x00010000L 554 #define VPEC_STATUS__RB_MC_RREQ_IDLE_MASK 0x00020000L 555 #define VPEC_STATUS__IB_MC_RREQ_IDLE_MASK 0x00040000L 556 #define VPEC_STATUS__MC_RD_IDLE_MASK 0x00080000L 557 #define VPEC_STATUS__DELTA_RPTR_EMPTY_MASK 0x00100000L 558 #define VPEC_STATUS__MC_RD_RET_STALL_MASK 0x00200000L 559 #define VPEC_STATUS__RESERVED_22_22_MASK 0x00400000L 560 #define VPEC_STATUS__RESERVED_23_23_MASK 0x00800000L 561 #define VPEC_STATUS__RESERVED_24_24_MASK 0x01000000L 562 #define VPEC_STATUS__PREV_CMD_IDLE_MASK 0x02000000L 563 #define VPEC_STATUS__RESERVED_26_26_MASK 0x04000000L 564 #define VPEC_STATUS__RESERVED_27_27_MASK 0x08000000L 565 #define VPEC_STATUS__RESERVED_29_28_MASK 0x30000000L 566 #define VPEC_STATUS__INT_IDLE_MASK 0x40000000L 567 #define VPEC_STATUS__INT_REQ_STALL_MASK 0x80000000L 568 //VPEC_STATUS1 569 #define VPEC_STATUS1__CE_IP0_WREQ_IDLE__SHIFT 0x0 570 #define VPEC_STATUS1__CE_IP0_WR_IDLE__SHIFT 0x1 571 #define VPEC_STATUS1__CE_IP0_SPLIT_IDLE__SHIFT 0x2 572 #define VPEC_STATUS1__CE_IP0_RREQ_IDLE__SHIFT 0x3 573 #define VPEC_STATUS1__CE_IP0_OUT_IDLE__SHIFT 0x4 574 #define VPEC_STATUS1__CE_IP0_IN_IDLE__SHIFT 0x5 575 #define VPEC_STATUS1__CE_IP0_DST_IDLE__SHIFT 0x6 576 #define VPEC_STATUS1__CE_IP0_CMD_IDLE__SHIFT 0x7 577 #define VPEC_STATUS1__CE_IP1_WREQ_IDLE__SHIFT 0x8 578 #define VPEC_STATUS1__CE_IP1_WR_IDLE__SHIFT 0x9 579 #define VPEC_STATUS1__CE_IP1_SPLIT_IDLE__SHIFT 0xa 580 #define VPEC_STATUS1__CE_IP1_RREQ_IDLE__SHIFT 0xb 581 #define VPEC_STATUS1__CE_IP1_OUT_IDLE__SHIFT 0xc 582 #define VPEC_STATUS1__CE_IP1_IN_IDLE__SHIFT 0xd 583 #define VPEC_STATUS1__CE_IP1_DST_IDLE__SHIFT 0xe 584 #define VPEC_STATUS1__CE_IP1_CMD_IDLE__SHIFT 0xf 585 #define VPEC_STATUS1__CE_OP0_WR_IDLE__SHIFT 0x10 586 #define VPEC_STATUS1__CE_OP0_CMD_IDLE__SHIFT 0x11 587 #define VPEC_STATUS1__CE_IP0_AFIFO_FULL__SHIFT 0x12 588 #define VPEC_STATUS1__CE_IP0_CMD_INFO_FULL__SHIFT 0x13 589 #define VPEC_STATUS1__CE_IP0_CMD_INFO1_FULL__SHIFT 0x14 590 #define VPEC_STATUS1__CE_IP1_AFIFO_FULL__SHIFT 0x15 591 #define VPEC_STATUS1__CE_IP1_CMD_INFO_FULL__SHIFT 0x16 592 #define VPEC_STATUS1__CE_IP1_CMD_INFO1_FULL__SHIFT 0x17 593 #define VPEC_STATUS1__EX_START__SHIFT 0x18 594 #define VPEC_STATUS1__CE_RD_STALL__SHIFT 0x19 595 #define VPEC_STATUS1__CE_IP0_WR_STALL__SHIFT 0x1a 596 #define VPEC_STATUS1__CE_IP1_WR_STALL__SHIFT 0x1b 597 #define VPEC_STATUS1__RESERVED_28_28__SHIFT 0x1c 598 #define VPEC_STATUS1__VPEC_IDLE__SHIFT 0x1d 599 #define VPEC_STATUS1__PG_STATUS__SHIFT 0x1e 600 #define VPEC_STATUS1__CE_IP0_WREQ_IDLE_MASK 0x00000001L 601 #define VPEC_STATUS1__CE_IP0_WR_IDLE_MASK 0x00000002L 602 #define VPEC_STATUS1__CE_IP0_SPLIT_IDLE_MASK 0x00000004L 603 #define VPEC_STATUS1__CE_IP0_RREQ_IDLE_MASK 0x00000008L 604 #define VPEC_STATUS1__CE_IP0_OUT_IDLE_MASK 0x00000010L 605 #define VPEC_STATUS1__CE_IP0_IN_IDLE_MASK 0x00000020L 606 #define VPEC_STATUS1__CE_IP0_DST_IDLE_MASK 0x00000040L 607 #define VPEC_STATUS1__CE_IP0_CMD_IDLE_MASK 0x00000080L 608 #define VPEC_STATUS1__CE_IP1_WREQ_IDLE_MASK 0x00000100L 609 #define VPEC_STATUS1__CE_IP1_WR_IDLE_MASK 0x00000200L 610 #define VPEC_STATUS1__CE_IP1_SPLIT_IDLE_MASK 0x00000400L 611 #define VPEC_STATUS1__CE_IP1_RREQ_IDLE_MASK 0x00000800L 612 #define VPEC_STATUS1__CE_IP1_OUT_IDLE_MASK 0x00001000L 613 #define VPEC_STATUS1__CE_IP1_IN_IDLE_MASK 0x00002000L 614 #define VPEC_STATUS1__CE_IP1_DST_IDLE_MASK 0x00004000L 615 #define VPEC_STATUS1__CE_IP1_CMD_IDLE_MASK 0x00008000L 616 #define VPEC_STATUS1__CE_OP0_WR_IDLE_MASK 0x00010000L 617 #define VPEC_STATUS1__CE_OP0_CMD_IDLE_MASK 0x00020000L 618 #define VPEC_STATUS1__CE_IP0_AFIFO_FULL_MASK 0x00040000L 619 #define VPEC_STATUS1__CE_IP0_CMD_INFO_FULL_MASK 0x00080000L 620 #define VPEC_STATUS1__CE_IP0_CMD_INFO1_FULL_MASK 0x00100000L 621 #define VPEC_STATUS1__CE_IP1_AFIFO_FULL_MASK 0x00200000L 622 #define VPEC_STATUS1__CE_IP1_CMD_INFO_FULL_MASK 0x00400000L 623 #define VPEC_STATUS1__CE_IP1_CMD_INFO1_FULL_MASK 0x00800000L 624 #define VPEC_STATUS1__EX_START_MASK 0x01000000L 625 #define VPEC_STATUS1__CE_RD_STALL_MASK 0x02000000L 626 #define VPEC_STATUS1__CE_IP0_WR_STALL_MASK 0x04000000L 627 #define VPEC_STATUS1__CE_IP1_WR_STALL_MASK 0x08000000L 628 #define VPEC_STATUS1__RESERVED_28_28_MASK 0x10000000L 629 #define VPEC_STATUS1__VPEC_IDLE_MASK 0x20000000L 630 #define VPEC_STATUS1__PG_STATUS_MASK 0xC0000000L 631 //VPEC_STATUS2 632 #define VPEC_STATUS2__ID__SHIFT 0x0 633 #define VPEC_STATUS2__TH0F32_INSTR_PTR__SHIFT 0x2 634 #define VPEC_STATUS2__CMD_OP__SHIFT 0x10 635 #define VPEC_STATUS2__ID_MASK 0x00000003L 636 #define VPEC_STATUS2__TH0F32_INSTR_PTR_MASK 0x0000FFFCL 637 #define VPEC_STATUS2__CMD_OP_MASK 0xFFFF0000L 638 //VPEC_STATUS3 639 #define VPEC_STATUS3__CMD_OP_STATUS__SHIFT 0x0 640 #define VPEC_STATUS3__RESERVED_19_16__SHIFT 0x10 641 #define VPEC_STATUS3__EXCEPTION_IDLE__SHIFT 0x14 642 #define VPEC_STATUS3__RESERVED_21_21__SHIFT 0x15 643 #define VPEC_STATUS3__RESERVED_22_22__SHIFT 0x16 644 #define VPEC_STATUS3__RESERVED_23_23__SHIFT 0x17 645 #define VPEC_STATUS3__RESERVED_24_24__SHIFT 0x18 646 #define VPEC_STATUS3__RESERVED_25_25__SHIFT 0x19 647 #define VPEC_STATUS3__INT_QUEUE_ID__SHIFT 0x1a 648 #define VPEC_STATUS3__RESERVED_31_30__SHIFT 0x1e 649 #define VPEC_STATUS3__CMD_OP_STATUS_MASK 0x0000FFFFL 650 #define VPEC_STATUS3__RESERVED_19_16_MASK 0x000F0000L 651 #define VPEC_STATUS3__EXCEPTION_IDLE_MASK 0x00100000L 652 #define VPEC_STATUS3__RESERVED_21_21_MASK 0x00200000L 653 #define VPEC_STATUS3__RESERVED_22_22_MASK 0x00400000L 654 #define VPEC_STATUS3__RESERVED_23_23_MASK 0x00800000L 655 #define VPEC_STATUS3__RESERVED_24_24_MASK 0x01000000L 656 #define VPEC_STATUS3__RESERVED_25_25_MASK 0x02000000L 657 #define VPEC_STATUS3__INT_QUEUE_ID_MASK 0x3C000000L 658 #define VPEC_STATUS3__RESERVED_31_30_MASK 0xC0000000L 659 //VPEC_STATUS4 660 #define VPEC_STATUS4__IDLE__SHIFT 0x0 661 #define VPEC_STATUS4__IH_OUTSTANDING__SHIFT 0x2 662 #define VPEC_STATUS4__RESERVED_3_3__SHIFT 0x3 663 #define VPEC_STATUS4__CH_RD_OUTSTANDING__SHIFT 0x4 664 #define VPEC_STATUS4__CH_WR_OUTSTANDING__SHIFT 0x5 665 #define VPEC_STATUS4__RESERVED_6_6__SHIFT 0x6 666 #define VPEC_STATUS4__RESERVED_7_7__SHIFT 0x7 667 #define VPEC_STATUS4__RESERVED_8_8__SHIFT 0x8 668 #define VPEC_STATUS4__RESERVED_9_9__SHIFT 0x9 669 #define VPEC_STATUS4__REG_POLLING__SHIFT 0xa 670 #define VPEC_STATUS4__MEM_POLLING__SHIFT 0xb 671 #define VPEC_STATUS4__VPEP_REG_RD_OUTSTANDING__SHIFT 0xc 672 #define VPEC_STATUS4__VPEP_REG_WR_OUTSTANDING__SHIFT 0xd 673 #define VPEC_STATUS4__RESERVED_15_14__SHIFT 0xe 674 #define VPEC_STATUS4__ACTIVE_QUEUE_ID__SHIFT 0x10 675 #define VPEC_STATUS4__RESERVED_27_20__SHIFT 0x14 676 #define VPEC_STATUS4__IDLE_MASK 0x00000001L 677 #define VPEC_STATUS4__IH_OUTSTANDING_MASK 0x00000004L 678 #define VPEC_STATUS4__RESERVED_3_3_MASK 0x00000008L 679 #define VPEC_STATUS4__CH_RD_OUTSTANDING_MASK 0x00000010L 680 #define VPEC_STATUS4__CH_WR_OUTSTANDING_MASK 0x00000020L 681 #define VPEC_STATUS4__RESERVED_6_6_MASK 0x00000040L 682 #define VPEC_STATUS4__RESERVED_7_7_MASK 0x00000080L 683 #define VPEC_STATUS4__RESERVED_8_8_MASK 0x00000100L 684 #define VPEC_STATUS4__RESERVED_9_9_MASK 0x00000200L 685 #define VPEC_STATUS4__REG_POLLING_MASK 0x00000400L 686 #define VPEC_STATUS4__MEM_POLLING_MASK 0x00000800L 687 #define VPEC_STATUS4__VPEP_REG_RD_OUTSTANDING_MASK 0x00001000L 688 #define VPEC_STATUS4__VPEP_REG_WR_OUTSTANDING_MASK 0x00002000L 689 #define VPEC_STATUS4__RESERVED_15_14_MASK 0x0000C000L 690 #define VPEC_STATUS4__ACTIVE_QUEUE_ID_MASK 0x000F0000L 691 #define VPEC_STATUS4__RESERVED_27_20_MASK 0x0FF00000L 692 //VPEC_STATUS5 693 #define VPEC_STATUS5__QUEUE0_RB_ENABLE_STATUS__SHIFT 0x0 694 #define VPEC_STATUS5__QUEUE1_RB_ENABLE_STATUS__SHIFT 0x1 695 #define VPEC_STATUS5__QUEUE2_RB_ENABLE_STATUS__SHIFT 0x2 696 #define VPEC_STATUS5__QUEUE3_RB_ENABLE_STATUS__SHIFT 0x3 697 #define VPEC_STATUS5__QUEUE4_RB_ENABLE_STATUS__SHIFT 0x4 698 #define VPEC_STATUS5__QUEUE5_RB_ENABLE_STATUS__SHIFT 0x5 699 #define VPEC_STATUS5__QUEUE6_RB_ENABLE_STATUS__SHIFT 0x6 700 #define VPEC_STATUS5__QUEUE7_RB_ENABLE_STATUS__SHIFT 0x7 701 #define VPEC_STATUS5__RESERVED_27_16__SHIFT 0x10 702 #define VPEC_STATUS5__QUEUE0_RB_ENABLE_STATUS_MASK 0x00000001L 703 #define VPEC_STATUS5__QUEUE1_RB_ENABLE_STATUS_MASK 0x00000002L 704 #define VPEC_STATUS5__QUEUE2_RB_ENABLE_STATUS_MASK 0x00000004L 705 #define VPEC_STATUS5__QUEUE3_RB_ENABLE_STATUS_MASK 0x00000008L 706 #define VPEC_STATUS5__QUEUE4_RB_ENABLE_STATUS_MASK 0x00000010L 707 #define VPEC_STATUS5__QUEUE5_RB_ENABLE_STATUS_MASK 0x00000020L 708 #define VPEC_STATUS5__QUEUE6_RB_ENABLE_STATUS_MASK 0x00000040L 709 #define VPEC_STATUS5__QUEUE7_RB_ENABLE_STATUS_MASK 0x00000080L 710 #define VPEC_STATUS5__RESERVED_27_16_MASK 0x000F0000L 711 //VPEC_STATUS6 712 #define VPEC_STATUS6__ID__SHIFT 0x0 713 #define VPEC_STATUS6__TH1F32_INSTR_PTR__SHIFT 0x2 714 #define VPEC_STATUS6__TH1_EXCEPTION__SHIFT 0x10 715 #define VPEC_STATUS6__ID_MASK 0x00000003L 716 #define VPEC_STATUS6__TH1F32_INSTR_PTR_MASK 0x0000FFFCL 717 #define VPEC_STATUS6__TH1_EXCEPTION_MASK 0xFFFF0000L 718 //VPEC_STATUS7 719 //VPEC_INST 720 #define VPEC_INST__ID__SHIFT 0x0 721 #define VPEC_INST__RESERVED__SHIFT 0x1 722 #define VPEC_INST__ID_MASK 0x00000001L 723 #define VPEC_INST__RESERVED_MASK 0xFFFFFFFEL 724 //VPEC_QUEUE_STATUS0 725 #define VPEC_QUEUE_STATUS0__QUEUE0_STATUS__SHIFT 0x0 726 #define VPEC_QUEUE_STATUS0__QUEUE1_STATUS__SHIFT 0x4 727 #define VPEC_QUEUE_STATUS0__QUEUE2_STATUS__SHIFT 0x8 728 #define VPEC_QUEUE_STATUS0__QUEUE3_STATUS__SHIFT 0xc 729 #define VPEC_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT 0x10 730 #define VPEC_QUEUE_STATUS0__QUEUE5_STATUS__SHIFT 0x14 731 #define VPEC_QUEUE_STATUS0__QUEUE6_STATUS__SHIFT 0x18 732 #define VPEC_QUEUE_STATUS0__QUEUE7_STATUS__SHIFT 0x1c 733 #define VPEC_QUEUE_STATUS0__QUEUE0_STATUS_MASK 0x0000000FL 734 #define VPEC_QUEUE_STATUS0__QUEUE1_STATUS_MASK 0x000000F0L 735 #define VPEC_QUEUE_STATUS0__QUEUE2_STATUS_MASK 0x00000F00L 736 #define VPEC_QUEUE_STATUS0__QUEUE3_STATUS_MASK 0x0000F000L 737 #define VPEC_QUEUE_STATUS0__QUEUE4_STATUS_MASK 0x000F0000L 738 #define VPEC_QUEUE_STATUS0__QUEUE5_STATUS_MASK 0x00F00000L 739 #define VPEC_QUEUE_STATUS0__QUEUE6_STATUS_MASK 0x0F000000L 740 #define VPEC_QUEUE_STATUS0__QUEUE7_STATUS_MASK 0xF0000000L 741 //VPEC_QUEUE_HANG_STATUS 742 #define VPEC_QUEUE_HANG_STATUS__F30T0_HANG__SHIFT 0x0 743 #define VPEC_QUEUE_HANG_STATUS__CE_HANG__SHIFT 0x1 744 #define VPEC_QUEUE_HANG_STATUS__EOF_MISMATCH__SHIFT 0x2 745 #define VPEC_QUEUE_HANG_STATUS__INVALID_OPCODE__SHIFT 0x3 746 #define VPEC_QUEUE_HANG_STATUS__INVALID_VPEP_CONFIG_ADDR__SHIFT 0x4 747 #define VPEC_QUEUE_HANG_STATUS__F30T0_HANG_MASK 0x00000001L 748 #define VPEC_QUEUE_HANG_STATUS__CE_HANG_MASK 0x00000002L 749 #define VPEC_QUEUE_HANG_STATUS__EOF_MISMATCH_MASK 0x00000004L 750 #define VPEC_QUEUE_HANG_STATUS__INVALID_OPCODE_MASK 0x00000008L 751 #define VPEC_QUEUE_HANG_STATUS__INVALID_VPEP_CONFIG_ADDR_MASK 0x00000010L 752 //VPEC_QUEUE0_RB_CNTL 753 #define VPEC_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT 0x0 754 #define VPEC_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1 755 #define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 756 #define VPEC_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 757 #define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa 758 #define VPEC_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb 759 #define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 760 #define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 761 #define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 762 #define VPEC_QUEUE0_RB_CNTL__RB_PRIV__SHIFT 0x17 763 #define VPEC_QUEUE0_RB_CNTL__RB_VMID__SHIFT 0x18 764 #define VPEC_QUEUE0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 765 #define VPEC_QUEUE0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 766 #define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L 767 #define VPEC_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 768 #define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L 769 #define VPEC_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L 770 #define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 771 #define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 772 #define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 773 #define VPEC_QUEUE0_RB_CNTL__RB_PRIV_MASK 0x00800000L 774 #define VPEC_QUEUE0_RB_CNTL__RB_VMID_MASK 0x0F000000L 775 //VPEC_QUEUE0_SCHEDULE_CNTL 776 #define VPEC_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 777 #define VPEC_QUEUE0_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 778 #define VPEC_QUEUE0_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 779 #define VPEC_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 780 #define VPEC_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L 781 #define VPEC_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL 782 #define VPEC_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L 783 #define VPEC_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L 784 //VPEC_QUEUE0_RB_BASE 785 #define VPEC_QUEUE0_RB_BASE__ADDR__SHIFT 0x0 786 #define VPEC_QUEUE0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 787 //VPEC_QUEUE0_RB_BASE_HI 788 #define VPEC_QUEUE0_RB_BASE_HI__ADDR__SHIFT 0x0 789 #define VPEC_QUEUE0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 790 //VPEC_QUEUE0_RB_RPTR 791 #define VPEC_QUEUE0_RB_RPTR__OFFSET__SHIFT 0x0 792 #define VPEC_QUEUE0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 793 //VPEC_QUEUE0_RB_RPTR_HI 794 #define VPEC_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT 0x0 795 #define VPEC_QUEUE0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 796 //VPEC_QUEUE0_RB_WPTR 797 #define VPEC_QUEUE0_RB_WPTR__OFFSET__SHIFT 0x0 798 #define VPEC_QUEUE0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 799 //VPEC_QUEUE0_RB_WPTR_HI 800 #define VPEC_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT 0x0 801 #define VPEC_QUEUE0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 802 //VPEC_QUEUE0_RB_RPTR_ADDR_HI 803 #define VPEC_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 804 #define VPEC_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 805 //VPEC_QUEUE0_RB_RPTR_ADDR_LO 806 #define VPEC_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 807 #define VPEC_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 808 //VPEC_QUEUE0_RB_AQL_CNTL 809 #define VPEC_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 810 #define VPEC_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 811 #define VPEC_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 812 #define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 813 #define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 814 #define VPEC_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 815 #define VPEC_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 816 #define VPEC_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 817 #define VPEC_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 818 #define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L 819 #define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L 820 #define VPEC_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L 821 //VPEC_QUEUE0_MINOR_PTR_UPDATE 822 #define VPEC_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 823 #define VPEC_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 824 //VPEC_QUEUE0_CD_INFO 825 #define VPEC_QUEUE0_CD_INFO__CD_INFO__SHIFT 0x0 826 #define VPEC_QUEUE0_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL 827 //VPEC_QUEUE0_RB_PREEMPT 828 #define VPEC_QUEUE0_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 829 #define VPEC_QUEUE0_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 830 //VPEC_QUEUE0_SKIP_CNTL 831 #define VPEC_QUEUE0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 832 #define VPEC_QUEUE0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 833 //VPEC_QUEUE0_DOORBELL 834 #define VPEC_QUEUE0_DOORBELL__ENABLE__SHIFT 0x1c 835 #define VPEC_QUEUE0_DOORBELL__CAPTURED__SHIFT 0x1e 836 #define VPEC_QUEUE0_DOORBELL__ENABLE_MASK 0x10000000L 837 #define VPEC_QUEUE0_DOORBELL__CAPTURED_MASK 0x40000000L 838 //VPEC_QUEUE0_DOORBELL_OFFSET 839 #define VPEC_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 840 #define VPEC_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 841 //VPEC_QUEUE0_DUMMY0 842 #define VPEC_QUEUE0_DUMMY0__DUMMY__SHIFT 0x0 843 #define VPEC_QUEUE0_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 844 //VPEC_QUEUE0_DUMMY1 845 #define VPEC_QUEUE0_DUMMY1__VALUE__SHIFT 0x0 846 #define VPEC_QUEUE0_DUMMY1__VALUE_MASK 0xFFFFFFFFL 847 //VPEC_QUEUE0_DUMMY2 848 #define VPEC_QUEUE0_DUMMY2__VALUE__SHIFT 0x0 849 #define VPEC_QUEUE0_DUMMY2__VALUE_MASK 0xFFFFFFFFL 850 //VPEC_QUEUE0_DUMMY3 851 #define VPEC_QUEUE0_DUMMY3__VALUE__SHIFT 0x0 852 #define VPEC_QUEUE0_DUMMY3__VALUE_MASK 0xFFFFFFFFL 853 //VPEC_QUEUE0_DUMMY4 854 #define VPEC_QUEUE0_DUMMY4__VALUE__SHIFT 0x0 855 #define VPEC_QUEUE0_DUMMY4__VALUE_MASK 0xFFFFFFFFL 856 //VPEC_QUEUE0_IB_CNTL 857 #define VPEC_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT 0x0 858 #define VPEC_QUEUE0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 859 #define VPEC_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 860 #define VPEC_QUEUE0_IB_CNTL__CMD_VMID__SHIFT 0x10 861 #define VPEC_QUEUE0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 862 #define VPEC_QUEUE0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 863 #define VPEC_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 864 #define VPEC_QUEUE0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 865 //VPEC_QUEUE0_IB_RPTR 866 #define VPEC_QUEUE0_IB_RPTR__OFFSET__SHIFT 0x2 867 #define VPEC_QUEUE0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 868 //VPEC_QUEUE0_IB_OFFSET 869 #define VPEC_QUEUE0_IB_OFFSET__OFFSET__SHIFT 0x2 870 #define VPEC_QUEUE0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 871 //VPEC_QUEUE0_IB_BASE_LO 872 #define VPEC_QUEUE0_IB_BASE_LO__ADDR__SHIFT 0x5 873 #define VPEC_QUEUE0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 874 //VPEC_QUEUE0_IB_BASE_HI 875 #define VPEC_QUEUE0_IB_BASE_HI__ADDR__SHIFT 0x0 876 #define VPEC_QUEUE0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 877 //VPEC_QUEUE0_IB_SIZE 878 #define VPEC_QUEUE0_IB_SIZE__SIZE__SHIFT 0x0 879 #define VPEC_QUEUE0_IB_SIZE__SIZE_MASK 0x000FFFFFL 880 //VPEC_QUEUE0_CMDIB_CNTL 881 #define VPEC_QUEUE0_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 882 #define VPEC_QUEUE0_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 883 #define VPEC_QUEUE0_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 884 #define VPEC_QUEUE0_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 885 #define VPEC_QUEUE0_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L 886 #define VPEC_QUEUE0_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 887 #define VPEC_QUEUE0_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 888 #define VPEC_QUEUE0_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L 889 //VPEC_QUEUE0_CMDIB_RPTR 890 #define VPEC_QUEUE0_CMDIB_RPTR__OFFSET__SHIFT 0x2 891 #define VPEC_QUEUE0_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL 892 //VPEC_QUEUE0_CMDIB_OFFSET 893 #define VPEC_QUEUE0_CMDIB_OFFSET__OFFSET__SHIFT 0x2 894 #define VPEC_QUEUE0_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL 895 //VPEC_QUEUE0_CMDIB_BASE_LO 896 #define VPEC_QUEUE0_CMDIB_BASE_LO__ADDR__SHIFT 0x5 897 #define VPEC_QUEUE0_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 898 //VPEC_QUEUE0_CMDIB_BASE_HI 899 #define VPEC_QUEUE0_CMDIB_BASE_HI__ADDR__SHIFT 0x0 900 #define VPEC_QUEUE0_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 901 //VPEC_QUEUE0_CMDIB_SIZE 902 #define VPEC_QUEUE0_CMDIB_SIZE__SIZE__SHIFT 0x0 903 #define VPEC_QUEUE0_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL 904 //VPEC_QUEUE0_CSA_ADDR_LO 905 #define VPEC_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT 0x0 906 #define VPEC_QUEUE0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL 907 //VPEC_QUEUE0_CSA_ADDR_HI 908 #define VPEC_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT 0x0 909 #define VPEC_QUEUE0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 910 //VPEC_QUEUE0_CONTEXT_STATUS 911 #define VPEC_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 912 #define VPEC_QUEUE0_CONTEXT_STATUS__USE_IB__SHIFT 0x1 913 #define VPEC_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT 0x2 914 #define VPEC_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 915 #define VPEC_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 916 #define VPEC_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 917 #define VPEC_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 918 #define VPEC_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb 919 #define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc 920 #define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 921 #define VPEC_QUEUE0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 922 #define VPEC_QUEUE0_CONTEXT_STATUS__USE_IB_MASK 0x00000002L 923 #define VPEC_QUEUE0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 924 #define VPEC_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 925 #define VPEC_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 926 #define VPEC_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 927 #define VPEC_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 928 #define VPEC_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L 929 #define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L 930 #define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L 931 //VPEC_QUEUE0_DOORBELL_LOG 932 //VPEC_QUEUE0_IB_SUB_REMAIN 933 #define VPEC_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 934 #define VPEC_QUEUE0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 935 //VPEC_QUEUE0_PREEMPT 936 #define VPEC_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT 0x0 937 #define VPEC_QUEUE0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 938 //VPEC_QUEUE1_RB_CNTL 939 #define VPEC_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT 0x0 940 #define VPEC_QUEUE1_RB_CNTL__RB_SIZE__SHIFT 0x1 941 #define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 942 #define VPEC_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 943 #define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa 944 #define VPEC_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb 945 #define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 946 #define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 947 #define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 948 #define VPEC_QUEUE1_RB_CNTL__RB_PRIV__SHIFT 0x17 949 #define VPEC_QUEUE1_RB_CNTL__RB_VMID__SHIFT 0x18 950 #define VPEC_QUEUE1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 951 #define VPEC_QUEUE1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 952 #define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L 953 #define VPEC_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 954 #define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L 955 #define VPEC_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L 956 #define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 957 #define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 958 #define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 959 #define VPEC_QUEUE1_RB_CNTL__RB_PRIV_MASK 0x00800000L 960 #define VPEC_QUEUE1_RB_CNTL__RB_VMID_MASK 0x0F000000L 961 //VPEC_QUEUE1_SCHEDULE_CNTL 962 #define VPEC_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 963 #define VPEC_QUEUE1_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 964 #define VPEC_QUEUE1_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 965 #define VPEC_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 966 #define VPEC_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L 967 #define VPEC_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL 968 #define VPEC_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L 969 #define VPEC_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L 970 //VPEC_QUEUE1_RB_BASE 971 #define VPEC_QUEUE1_RB_BASE__ADDR__SHIFT 0x0 972 #define VPEC_QUEUE1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 973 //VPEC_QUEUE1_RB_BASE_HI 974 #define VPEC_QUEUE1_RB_BASE_HI__ADDR__SHIFT 0x0 975 #define VPEC_QUEUE1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 976 //VPEC_QUEUE1_RB_RPTR 977 #define VPEC_QUEUE1_RB_RPTR__OFFSET__SHIFT 0x0 978 #define VPEC_QUEUE1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 979 //VPEC_QUEUE1_RB_RPTR_HI 980 #define VPEC_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT 0x0 981 #define VPEC_QUEUE1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 982 //VPEC_QUEUE1_RB_WPTR 983 #define VPEC_QUEUE1_RB_WPTR__OFFSET__SHIFT 0x0 984 #define VPEC_QUEUE1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 985 //VPEC_QUEUE1_RB_WPTR_HI 986 #define VPEC_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT 0x0 987 #define VPEC_QUEUE1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 988 //VPEC_QUEUE1_RB_RPTR_ADDR_HI 989 #define VPEC_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 990 #define VPEC_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 991 //VPEC_QUEUE1_RB_RPTR_ADDR_LO 992 #define VPEC_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 993 #define VPEC_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 994 //VPEC_QUEUE1_RB_AQL_CNTL 995 #define VPEC_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 996 #define VPEC_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 997 #define VPEC_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 998 #define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 999 #define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 1000 #define VPEC_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 1001 #define VPEC_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1002 #define VPEC_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1003 #define VPEC_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1004 #define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L 1005 #define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L 1006 #define VPEC_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L 1007 //VPEC_QUEUE1_MINOR_PTR_UPDATE 1008 #define VPEC_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1009 #define VPEC_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1010 //VPEC_QUEUE1_CD_INFO 1011 #define VPEC_QUEUE1_CD_INFO__CD_INFO__SHIFT 0x0 1012 #define VPEC_QUEUE1_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL 1013 //VPEC_QUEUE1_RB_PREEMPT 1014 #define VPEC_QUEUE1_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 1015 #define VPEC_QUEUE1_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 1016 //VPEC_QUEUE1_SKIP_CNTL 1017 #define VPEC_QUEUE1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1018 #define VPEC_QUEUE1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1019 //VPEC_QUEUE1_DOORBELL 1020 #define VPEC_QUEUE1_DOORBELL__ENABLE__SHIFT 0x1c 1021 #define VPEC_QUEUE1_DOORBELL__CAPTURED__SHIFT 0x1e 1022 #define VPEC_QUEUE1_DOORBELL__ENABLE_MASK 0x10000000L 1023 #define VPEC_QUEUE1_DOORBELL__CAPTURED_MASK 0x40000000L 1024 //VPEC_QUEUE1_DOORBELL_OFFSET 1025 #define VPEC_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1026 #define VPEC_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1027 //VPEC_QUEUE1_DUMMY0 1028 #define VPEC_QUEUE1_DUMMY0__DUMMY__SHIFT 0x0 1029 #define VPEC_QUEUE1_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 1030 //VPEC_QUEUE1_DUMMY1 1031 #define VPEC_QUEUE1_DUMMY1__VALUE__SHIFT 0x0 1032 #define VPEC_QUEUE1_DUMMY1__VALUE_MASK 0xFFFFFFFFL 1033 //VPEC_QUEUE1_DUMMY2 1034 #define VPEC_QUEUE1_DUMMY2__VALUE__SHIFT 0x0 1035 #define VPEC_QUEUE1_DUMMY2__VALUE_MASK 0xFFFFFFFFL 1036 //VPEC_QUEUE1_DUMMY3 1037 #define VPEC_QUEUE1_DUMMY3__VALUE__SHIFT 0x0 1038 #define VPEC_QUEUE1_DUMMY3__VALUE_MASK 0xFFFFFFFFL 1039 //VPEC_QUEUE1_DUMMY4 1040 #define VPEC_QUEUE1_DUMMY4__VALUE__SHIFT 0x0 1041 #define VPEC_QUEUE1_DUMMY4__VALUE_MASK 0xFFFFFFFFL 1042 //VPEC_QUEUE1_IB_CNTL 1043 #define VPEC_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1044 #define VPEC_QUEUE1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1045 #define VPEC_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1046 #define VPEC_QUEUE1_IB_CNTL__CMD_VMID__SHIFT 0x10 1047 #define VPEC_QUEUE1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1048 #define VPEC_QUEUE1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1049 #define VPEC_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1050 #define VPEC_QUEUE1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1051 //VPEC_QUEUE1_IB_RPTR 1052 #define VPEC_QUEUE1_IB_RPTR__OFFSET__SHIFT 0x2 1053 #define VPEC_QUEUE1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1054 //VPEC_QUEUE1_IB_OFFSET 1055 #define VPEC_QUEUE1_IB_OFFSET__OFFSET__SHIFT 0x2 1056 #define VPEC_QUEUE1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1057 //VPEC_QUEUE1_IB_BASE_LO 1058 #define VPEC_QUEUE1_IB_BASE_LO__ADDR__SHIFT 0x5 1059 #define VPEC_QUEUE1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1060 //VPEC_QUEUE1_IB_BASE_HI 1061 #define VPEC_QUEUE1_IB_BASE_HI__ADDR__SHIFT 0x0 1062 #define VPEC_QUEUE1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1063 //VPEC_QUEUE1_IB_SIZE 1064 #define VPEC_QUEUE1_IB_SIZE__SIZE__SHIFT 0x0 1065 #define VPEC_QUEUE1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1066 //VPEC_QUEUE1_CMDIB_CNTL 1067 #define VPEC_QUEUE1_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 1068 #define VPEC_QUEUE1_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1069 #define VPEC_QUEUE1_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1070 #define VPEC_QUEUE1_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 1071 #define VPEC_QUEUE1_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L 1072 #define VPEC_QUEUE1_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1073 #define VPEC_QUEUE1_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1074 #define VPEC_QUEUE1_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L 1075 //VPEC_QUEUE1_CMDIB_RPTR 1076 #define VPEC_QUEUE1_CMDIB_RPTR__OFFSET__SHIFT 0x2 1077 #define VPEC_QUEUE1_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL 1078 //VPEC_QUEUE1_CMDIB_OFFSET 1079 #define VPEC_QUEUE1_CMDIB_OFFSET__OFFSET__SHIFT 0x2 1080 #define VPEC_QUEUE1_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL 1081 //VPEC_QUEUE1_CMDIB_BASE_LO 1082 #define VPEC_QUEUE1_CMDIB_BASE_LO__ADDR__SHIFT 0x5 1083 #define VPEC_QUEUE1_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1084 //VPEC_QUEUE1_CMDIB_BASE_HI 1085 #define VPEC_QUEUE1_CMDIB_BASE_HI__ADDR__SHIFT 0x0 1086 #define VPEC_QUEUE1_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1087 //VPEC_QUEUE1_CMDIB_SIZE 1088 #define VPEC_QUEUE1_CMDIB_SIZE__SIZE__SHIFT 0x0 1089 #define VPEC_QUEUE1_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL 1090 //VPEC_QUEUE1_CSA_ADDR_LO 1091 #define VPEC_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT 0x0 1092 #define VPEC_QUEUE1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL 1093 //VPEC_QUEUE1_CSA_ADDR_HI 1094 #define VPEC_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1095 #define VPEC_QUEUE1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1096 //VPEC_QUEUE1_CONTEXT_STATUS 1097 #define VPEC_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1098 #define VPEC_QUEUE1_CONTEXT_STATUS__USE_IB__SHIFT 0x1 1099 #define VPEC_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1100 #define VPEC_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1101 #define VPEC_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1102 #define VPEC_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1103 #define VPEC_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1104 #define VPEC_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb 1105 #define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc 1106 #define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 1107 #define VPEC_QUEUE1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1108 #define VPEC_QUEUE1_CONTEXT_STATUS__USE_IB_MASK 0x00000002L 1109 #define VPEC_QUEUE1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1110 #define VPEC_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1111 #define VPEC_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1112 #define VPEC_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1113 #define VPEC_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1114 #define VPEC_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L 1115 #define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L 1116 #define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L 1117 //VPEC_QUEUE1_DOORBELL_LOG 1118 //VPEC_QUEUE1_IB_SUB_REMAIN 1119 #define VPEC_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1120 #define VPEC_QUEUE1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1121 //VPEC_QUEUE1_PREEMPT 1122 #define VPEC_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1123 #define VPEC_QUEUE1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1124 //VPEC_QUEUE2_RB_CNTL 1125 #define VPEC_QUEUE2_RB_CNTL__RB_ENABLE__SHIFT 0x0 1126 #define VPEC_QUEUE2_RB_CNTL__RB_SIZE__SHIFT 0x1 1127 #define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 1128 #define VPEC_QUEUE2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1129 #define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa 1130 #define VPEC_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb 1131 #define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1132 #define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1133 #define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1134 #define VPEC_QUEUE2_RB_CNTL__RB_PRIV__SHIFT 0x17 1135 #define VPEC_QUEUE2_RB_CNTL__RB_VMID__SHIFT 0x18 1136 #define VPEC_QUEUE2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1137 #define VPEC_QUEUE2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1138 #define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L 1139 #define VPEC_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1140 #define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L 1141 #define VPEC_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L 1142 #define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1143 #define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1144 #define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1145 #define VPEC_QUEUE2_RB_CNTL__RB_PRIV_MASK 0x00800000L 1146 #define VPEC_QUEUE2_RB_CNTL__RB_VMID_MASK 0x0F000000L 1147 //VPEC_QUEUE2_SCHEDULE_CNTL 1148 #define VPEC_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 1149 #define VPEC_QUEUE2_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 1150 #define VPEC_QUEUE2_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 1151 #define VPEC_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 1152 #define VPEC_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L 1153 #define VPEC_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL 1154 #define VPEC_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L 1155 #define VPEC_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L 1156 //VPEC_QUEUE2_RB_BASE 1157 #define VPEC_QUEUE2_RB_BASE__ADDR__SHIFT 0x0 1158 #define VPEC_QUEUE2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1159 //VPEC_QUEUE2_RB_BASE_HI 1160 #define VPEC_QUEUE2_RB_BASE_HI__ADDR__SHIFT 0x0 1161 #define VPEC_QUEUE2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1162 //VPEC_QUEUE2_RB_RPTR 1163 #define VPEC_QUEUE2_RB_RPTR__OFFSET__SHIFT 0x0 1164 #define VPEC_QUEUE2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1165 //VPEC_QUEUE2_RB_RPTR_HI 1166 #define VPEC_QUEUE2_RB_RPTR_HI__OFFSET__SHIFT 0x0 1167 #define VPEC_QUEUE2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1168 //VPEC_QUEUE2_RB_WPTR 1169 #define VPEC_QUEUE2_RB_WPTR__OFFSET__SHIFT 0x0 1170 #define VPEC_QUEUE2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1171 //VPEC_QUEUE2_RB_WPTR_HI 1172 #define VPEC_QUEUE2_RB_WPTR_HI__OFFSET__SHIFT 0x0 1173 #define VPEC_QUEUE2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1174 //VPEC_QUEUE2_RB_RPTR_ADDR_HI 1175 #define VPEC_QUEUE2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1176 #define VPEC_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1177 //VPEC_QUEUE2_RB_RPTR_ADDR_LO 1178 #define VPEC_QUEUE2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1179 #define VPEC_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1180 //VPEC_QUEUE2_RB_AQL_CNTL 1181 #define VPEC_QUEUE2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1182 #define VPEC_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1183 #define VPEC_QUEUE2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1184 #define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 1185 #define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 1186 #define VPEC_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 1187 #define VPEC_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1188 #define VPEC_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1189 #define VPEC_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1190 #define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L 1191 #define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L 1192 #define VPEC_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L 1193 //VPEC_QUEUE2_MINOR_PTR_UPDATE 1194 #define VPEC_QUEUE2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1195 #define VPEC_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1196 //VPEC_QUEUE2_CD_INFO 1197 #define VPEC_QUEUE2_CD_INFO__CD_INFO__SHIFT 0x0 1198 #define VPEC_QUEUE2_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL 1199 //VPEC_QUEUE2_RB_PREEMPT 1200 #define VPEC_QUEUE2_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 1201 #define VPEC_QUEUE2_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 1202 //VPEC_QUEUE2_SKIP_CNTL 1203 #define VPEC_QUEUE2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1204 #define VPEC_QUEUE2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1205 //VPEC_QUEUE2_DOORBELL 1206 #define VPEC_QUEUE2_DOORBELL__ENABLE__SHIFT 0x1c 1207 #define VPEC_QUEUE2_DOORBELL__CAPTURED__SHIFT 0x1e 1208 #define VPEC_QUEUE2_DOORBELL__ENABLE_MASK 0x10000000L 1209 #define VPEC_QUEUE2_DOORBELL__CAPTURED_MASK 0x40000000L 1210 //VPEC_QUEUE2_DOORBELL_OFFSET 1211 #define VPEC_QUEUE2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1212 #define VPEC_QUEUE2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1213 //VPEC_QUEUE2_DUMMY0 1214 #define VPEC_QUEUE2_DUMMY0__DUMMY__SHIFT 0x0 1215 #define VPEC_QUEUE2_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 1216 //VPEC_QUEUE2_DUMMY1 1217 #define VPEC_QUEUE2_DUMMY1__VALUE__SHIFT 0x0 1218 #define VPEC_QUEUE2_DUMMY1__VALUE_MASK 0xFFFFFFFFL 1219 //VPEC_QUEUE2_DUMMY2 1220 #define VPEC_QUEUE2_DUMMY2__VALUE__SHIFT 0x0 1221 #define VPEC_QUEUE2_DUMMY2__VALUE_MASK 0xFFFFFFFFL 1222 //VPEC_QUEUE2_DUMMY3 1223 #define VPEC_QUEUE2_DUMMY3__VALUE__SHIFT 0x0 1224 #define VPEC_QUEUE2_DUMMY3__VALUE_MASK 0xFFFFFFFFL 1225 //VPEC_QUEUE2_DUMMY4 1226 #define VPEC_QUEUE2_DUMMY4__VALUE__SHIFT 0x0 1227 #define VPEC_QUEUE2_DUMMY4__VALUE_MASK 0xFFFFFFFFL 1228 //VPEC_QUEUE2_IB_CNTL 1229 #define VPEC_QUEUE2_IB_CNTL__IB_ENABLE__SHIFT 0x0 1230 #define VPEC_QUEUE2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1231 #define VPEC_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1232 #define VPEC_QUEUE2_IB_CNTL__CMD_VMID__SHIFT 0x10 1233 #define VPEC_QUEUE2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1234 #define VPEC_QUEUE2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1235 #define VPEC_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1236 #define VPEC_QUEUE2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1237 //VPEC_QUEUE2_IB_RPTR 1238 #define VPEC_QUEUE2_IB_RPTR__OFFSET__SHIFT 0x2 1239 #define VPEC_QUEUE2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1240 //VPEC_QUEUE2_IB_OFFSET 1241 #define VPEC_QUEUE2_IB_OFFSET__OFFSET__SHIFT 0x2 1242 #define VPEC_QUEUE2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1243 //VPEC_QUEUE2_IB_BASE_LO 1244 #define VPEC_QUEUE2_IB_BASE_LO__ADDR__SHIFT 0x5 1245 #define VPEC_QUEUE2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1246 //VPEC_QUEUE2_IB_BASE_HI 1247 #define VPEC_QUEUE2_IB_BASE_HI__ADDR__SHIFT 0x0 1248 #define VPEC_QUEUE2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1249 //VPEC_QUEUE2_IB_SIZE 1250 #define VPEC_QUEUE2_IB_SIZE__SIZE__SHIFT 0x0 1251 #define VPEC_QUEUE2_IB_SIZE__SIZE_MASK 0x000FFFFFL 1252 //VPEC_QUEUE2_CMDIB_CNTL 1253 #define VPEC_QUEUE2_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 1254 #define VPEC_QUEUE2_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1255 #define VPEC_QUEUE2_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1256 #define VPEC_QUEUE2_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 1257 #define VPEC_QUEUE2_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L 1258 #define VPEC_QUEUE2_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1259 #define VPEC_QUEUE2_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1260 #define VPEC_QUEUE2_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L 1261 //VPEC_QUEUE2_CMDIB_RPTR 1262 #define VPEC_QUEUE2_CMDIB_RPTR__OFFSET__SHIFT 0x2 1263 #define VPEC_QUEUE2_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL 1264 //VPEC_QUEUE2_CMDIB_OFFSET 1265 #define VPEC_QUEUE2_CMDIB_OFFSET__OFFSET__SHIFT 0x2 1266 #define VPEC_QUEUE2_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL 1267 //VPEC_QUEUE2_CMDIB_BASE_LO 1268 #define VPEC_QUEUE2_CMDIB_BASE_LO__ADDR__SHIFT 0x5 1269 #define VPEC_QUEUE2_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1270 //VPEC_QUEUE2_CMDIB_BASE_HI 1271 #define VPEC_QUEUE2_CMDIB_BASE_HI__ADDR__SHIFT 0x0 1272 #define VPEC_QUEUE2_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1273 //VPEC_QUEUE2_CMDIB_SIZE 1274 #define VPEC_QUEUE2_CMDIB_SIZE__SIZE__SHIFT 0x0 1275 #define VPEC_QUEUE2_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL 1276 //VPEC_QUEUE2_CSA_ADDR_LO 1277 #define VPEC_QUEUE2_CSA_ADDR_LO__ADDR__SHIFT 0x0 1278 #define VPEC_QUEUE2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL 1279 //VPEC_QUEUE2_CSA_ADDR_HI 1280 #define VPEC_QUEUE2_CSA_ADDR_HI__ADDR__SHIFT 0x0 1281 #define VPEC_QUEUE2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1282 //VPEC_QUEUE2_CONTEXT_STATUS 1283 #define VPEC_QUEUE2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1284 #define VPEC_QUEUE2_CONTEXT_STATUS__USE_IB__SHIFT 0x1 1285 #define VPEC_QUEUE2_CONTEXT_STATUS__IDLE__SHIFT 0x2 1286 #define VPEC_QUEUE2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1287 #define VPEC_QUEUE2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1288 #define VPEC_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1289 #define VPEC_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1290 #define VPEC_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb 1291 #define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc 1292 #define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 1293 #define VPEC_QUEUE2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1294 #define VPEC_QUEUE2_CONTEXT_STATUS__USE_IB_MASK 0x00000002L 1295 #define VPEC_QUEUE2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1296 #define VPEC_QUEUE2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1297 #define VPEC_QUEUE2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1298 #define VPEC_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1299 #define VPEC_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1300 #define VPEC_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L 1301 #define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L 1302 #define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L 1303 //VPEC_QUEUE2_DOORBELL_LOG 1304 //VPEC_QUEUE2_IB_SUB_REMAIN 1305 #define VPEC_QUEUE2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1306 #define VPEC_QUEUE2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1307 //VPEC_QUEUE2_PREEMPT 1308 #define VPEC_QUEUE2_PREEMPT__IB_PREEMPT__SHIFT 0x0 1309 #define VPEC_QUEUE2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1310 //VPEC_QUEUE3_RB_CNTL 1311 #define VPEC_QUEUE3_RB_CNTL__RB_ENABLE__SHIFT 0x0 1312 #define VPEC_QUEUE3_RB_CNTL__RB_SIZE__SHIFT 0x1 1313 #define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 1314 #define VPEC_QUEUE3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1315 #define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa 1316 #define VPEC_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb 1317 #define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1318 #define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1319 #define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1320 #define VPEC_QUEUE3_RB_CNTL__RB_PRIV__SHIFT 0x17 1321 #define VPEC_QUEUE3_RB_CNTL__RB_VMID__SHIFT 0x18 1322 #define VPEC_QUEUE3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1323 #define VPEC_QUEUE3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1324 #define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L 1325 #define VPEC_QUEUE3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1326 #define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L 1327 #define VPEC_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L 1328 #define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1329 #define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1330 #define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1331 #define VPEC_QUEUE3_RB_CNTL__RB_PRIV_MASK 0x00800000L 1332 #define VPEC_QUEUE3_RB_CNTL__RB_VMID_MASK 0x0F000000L 1333 //VPEC_QUEUE3_SCHEDULE_CNTL 1334 #define VPEC_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 1335 #define VPEC_QUEUE3_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 1336 #define VPEC_QUEUE3_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 1337 #define VPEC_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 1338 #define VPEC_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L 1339 #define VPEC_QUEUE3_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL 1340 #define VPEC_QUEUE3_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L 1341 #define VPEC_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L 1342 //VPEC_QUEUE3_RB_BASE 1343 #define VPEC_QUEUE3_RB_BASE__ADDR__SHIFT 0x0 1344 #define VPEC_QUEUE3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1345 //VPEC_QUEUE3_RB_BASE_HI 1346 #define VPEC_QUEUE3_RB_BASE_HI__ADDR__SHIFT 0x0 1347 #define VPEC_QUEUE3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1348 //VPEC_QUEUE3_RB_RPTR 1349 #define VPEC_QUEUE3_RB_RPTR__OFFSET__SHIFT 0x0 1350 #define VPEC_QUEUE3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1351 //VPEC_QUEUE3_RB_RPTR_HI 1352 #define VPEC_QUEUE3_RB_RPTR_HI__OFFSET__SHIFT 0x0 1353 #define VPEC_QUEUE3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1354 //VPEC_QUEUE3_RB_WPTR 1355 #define VPEC_QUEUE3_RB_WPTR__OFFSET__SHIFT 0x0 1356 #define VPEC_QUEUE3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1357 //VPEC_QUEUE3_RB_WPTR_HI 1358 #define VPEC_QUEUE3_RB_WPTR_HI__OFFSET__SHIFT 0x0 1359 #define VPEC_QUEUE3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1360 //VPEC_QUEUE3_RB_RPTR_ADDR_HI 1361 #define VPEC_QUEUE3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1362 #define VPEC_QUEUE3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1363 //VPEC_QUEUE3_RB_RPTR_ADDR_LO 1364 #define VPEC_QUEUE3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1365 #define VPEC_QUEUE3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1366 //VPEC_QUEUE3_RB_AQL_CNTL 1367 #define VPEC_QUEUE3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1368 #define VPEC_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1369 #define VPEC_QUEUE3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1370 #define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 1371 #define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 1372 #define VPEC_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 1373 #define VPEC_QUEUE3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1374 #define VPEC_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1375 #define VPEC_QUEUE3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1376 #define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L 1377 #define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L 1378 #define VPEC_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L 1379 //VPEC_QUEUE3_MINOR_PTR_UPDATE 1380 #define VPEC_QUEUE3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1381 #define VPEC_QUEUE3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1382 //VPEC_QUEUE3_CD_INFO 1383 #define VPEC_QUEUE3_CD_INFO__CD_INFO__SHIFT 0x0 1384 #define VPEC_QUEUE3_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL 1385 //VPEC_QUEUE3_RB_PREEMPT 1386 #define VPEC_QUEUE3_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 1387 #define VPEC_QUEUE3_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 1388 //VPEC_QUEUE3_SKIP_CNTL 1389 #define VPEC_QUEUE3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1390 #define VPEC_QUEUE3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1391 //VPEC_QUEUE3_DOORBELL 1392 #define VPEC_QUEUE3_DOORBELL__ENABLE__SHIFT 0x1c 1393 #define VPEC_QUEUE3_DOORBELL__CAPTURED__SHIFT 0x1e 1394 #define VPEC_QUEUE3_DOORBELL__ENABLE_MASK 0x10000000L 1395 #define VPEC_QUEUE3_DOORBELL__CAPTURED_MASK 0x40000000L 1396 //VPEC_QUEUE3_DOORBELL_OFFSET 1397 #define VPEC_QUEUE3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1398 #define VPEC_QUEUE3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1399 //VPEC_QUEUE3_DUMMY0 1400 #define VPEC_QUEUE3_DUMMY0__DUMMY__SHIFT 0x0 1401 #define VPEC_QUEUE3_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 1402 //VPEC_QUEUE3_DUMMY1 1403 #define VPEC_QUEUE3_DUMMY1__VALUE__SHIFT 0x0 1404 #define VPEC_QUEUE3_DUMMY1__VALUE_MASK 0xFFFFFFFFL 1405 //VPEC_QUEUE3_DUMMY2 1406 #define VPEC_QUEUE3_DUMMY2__VALUE__SHIFT 0x0 1407 #define VPEC_QUEUE3_DUMMY2__VALUE_MASK 0xFFFFFFFFL 1408 //VPEC_QUEUE3_DUMMY3 1409 #define VPEC_QUEUE3_DUMMY3__VALUE__SHIFT 0x0 1410 #define VPEC_QUEUE3_DUMMY3__VALUE_MASK 0xFFFFFFFFL 1411 //VPEC_QUEUE3_DUMMY4 1412 #define VPEC_QUEUE3_DUMMY4__VALUE__SHIFT 0x0 1413 #define VPEC_QUEUE3_DUMMY4__VALUE_MASK 0xFFFFFFFFL 1414 //VPEC_QUEUE3_IB_CNTL 1415 #define VPEC_QUEUE3_IB_CNTL__IB_ENABLE__SHIFT 0x0 1416 #define VPEC_QUEUE3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1417 #define VPEC_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1418 #define VPEC_QUEUE3_IB_CNTL__CMD_VMID__SHIFT 0x10 1419 #define VPEC_QUEUE3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1420 #define VPEC_QUEUE3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1421 #define VPEC_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1422 #define VPEC_QUEUE3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1423 //VPEC_QUEUE3_IB_RPTR 1424 #define VPEC_QUEUE3_IB_RPTR__OFFSET__SHIFT 0x2 1425 #define VPEC_QUEUE3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1426 //VPEC_QUEUE3_IB_OFFSET 1427 #define VPEC_QUEUE3_IB_OFFSET__OFFSET__SHIFT 0x2 1428 #define VPEC_QUEUE3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1429 //VPEC_QUEUE3_IB_BASE_LO 1430 #define VPEC_QUEUE3_IB_BASE_LO__ADDR__SHIFT 0x5 1431 #define VPEC_QUEUE3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1432 //VPEC_QUEUE3_IB_BASE_HI 1433 #define VPEC_QUEUE3_IB_BASE_HI__ADDR__SHIFT 0x0 1434 #define VPEC_QUEUE3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1435 //VPEC_QUEUE3_IB_SIZE 1436 #define VPEC_QUEUE3_IB_SIZE__SIZE__SHIFT 0x0 1437 #define VPEC_QUEUE3_IB_SIZE__SIZE_MASK 0x000FFFFFL 1438 //VPEC_QUEUE3_CMDIB_CNTL 1439 #define VPEC_QUEUE3_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 1440 #define VPEC_QUEUE3_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1441 #define VPEC_QUEUE3_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1442 #define VPEC_QUEUE3_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 1443 #define VPEC_QUEUE3_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L 1444 #define VPEC_QUEUE3_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1445 #define VPEC_QUEUE3_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1446 #define VPEC_QUEUE3_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L 1447 //VPEC_QUEUE3_CMDIB_RPTR 1448 #define VPEC_QUEUE3_CMDIB_RPTR__OFFSET__SHIFT 0x2 1449 #define VPEC_QUEUE3_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL 1450 //VPEC_QUEUE3_CMDIB_OFFSET 1451 #define VPEC_QUEUE3_CMDIB_OFFSET__OFFSET__SHIFT 0x2 1452 #define VPEC_QUEUE3_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL 1453 //VPEC_QUEUE3_CMDIB_BASE_LO 1454 #define VPEC_QUEUE3_CMDIB_BASE_LO__ADDR__SHIFT 0x5 1455 #define VPEC_QUEUE3_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1456 //VPEC_QUEUE3_CMDIB_BASE_HI 1457 #define VPEC_QUEUE3_CMDIB_BASE_HI__ADDR__SHIFT 0x0 1458 #define VPEC_QUEUE3_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1459 //VPEC_QUEUE3_CMDIB_SIZE 1460 #define VPEC_QUEUE3_CMDIB_SIZE__SIZE__SHIFT 0x0 1461 #define VPEC_QUEUE3_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL 1462 //VPEC_QUEUE3_CSA_ADDR_LO 1463 #define VPEC_QUEUE3_CSA_ADDR_LO__ADDR__SHIFT 0x0 1464 #define VPEC_QUEUE3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL 1465 //VPEC_QUEUE3_CSA_ADDR_HI 1466 #define VPEC_QUEUE3_CSA_ADDR_HI__ADDR__SHIFT 0x0 1467 #define VPEC_QUEUE3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1468 //VPEC_QUEUE3_CONTEXT_STATUS 1469 #define VPEC_QUEUE3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1470 #define VPEC_QUEUE3_CONTEXT_STATUS__USE_IB__SHIFT 0x1 1471 #define VPEC_QUEUE3_CONTEXT_STATUS__IDLE__SHIFT 0x2 1472 #define VPEC_QUEUE3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1473 #define VPEC_QUEUE3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1474 #define VPEC_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1475 #define VPEC_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1476 #define VPEC_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb 1477 #define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc 1478 #define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 1479 #define VPEC_QUEUE3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1480 #define VPEC_QUEUE3_CONTEXT_STATUS__USE_IB_MASK 0x00000002L 1481 #define VPEC_QUEUE3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1482 #define VPEC_QUEUE3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1483 #define VPEC_QUEUE3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1484 #define VPEC_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1485 #define VPEC_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1486 #define VPEC_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L 1487 #define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L 1488 #define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L 1489 //VPEC_QUEUE3_DOORBELL_LOG 1490 //VPEC_QUEUE3_IB_SUB_REMAIN 1491 #define VPEC_QUEUE3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1492 #define VPEC_QUEUE3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1493 //VPEC_QUEUE3_PREEMPT 1494 #define VPEC_QUEUE3_PREEMPT__IB_PREEMPT__SHIFT 0x0 1495 #define VPEC_QUEUE3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1496 //VPEC_QUEUE4_RB_CNTL 1497 #define VPEC_QUEUE4_RB_CNTL__RB_ENABLE__SHIFT 0x0 1498 #define VPEC_QUEUE4_RB_CNTL__RB_SIZE__SHIFT 0x1 1499 #define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 1500 #define VPEC_QUEUE4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1501 #define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa 1502 #define VPEC_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb 1503 #define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1504 #define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1505 #define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1506 #define VPEC_QUEUE4_RB_CNTL__RB_PRIV__SHIFT 0x17 1507 #define VPEC_QUEUE4_RB_CNTL__RB_VMID__SHIFT 0x18 1508 #define VPEC_QUEUE4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1509 #define VPEC_QUEUE4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1510 #define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L 1511 #define VPEC_QUEUE4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1512 #define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L 1513 #define VPEC_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L 1514 #define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1515 #define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1516 #define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1517 #define VPEC_QUEUE4_RB_CNTL__RB_PRIV_MASK 0x00800000L 1518 #define VPEC_QUEUE4_RB_CNTL__RB_VMID_MASK 0x0F000000L 1519 //VPEC_QUEUE4_SCHEDULE_CNTL 1520 #define VPEC_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 1521 #define VPEC_QUEUE4_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 1522 #define VPEC_QUEUE4_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 1523 #define VPEC_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 1524 #define VPEC_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L 1525 #define VPEC_QUEUE4_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL 1526 #define VPEC_QUEUE4_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L 1527 #define VPEC_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L 1528 //VPEC_QUEUE4_RB_BASE 1529 #define VPEC_QUEUE4_RB_BASE__ADDR__SHIFT 0x0 1530 #define VPEC_QUEUE4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1531 //VPEC_QUEUE4_RB_BASE_HI 1532 #define VPEC_QUEUE4_RB_BASE_HI__ADDR__SHIFT 0x0 1533 #define VPEC_QUEUE4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1534 //VPEC_QUEUE4_RB_RPTR 1535 #define VPEC_QUEUE4_RB_RPTR__OFFSET__SHIFT 0x0 1536 #define VPEC_QUEUE4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1537 //VPEC_QUEUE4_RB_RPTR_HI 1538 #define VPEC_QUEUE4_RB_RPTR_HI__OFFSET__SHIFT 0x0 1539 #define VPEC_QUEUE4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1540 //VPEC_QUEUE4_RB_WPTR 1541 #define VPEC_QUEUE4_RB_WPTR__OFFSET__SHIFT 0x0 1542 #define VPEC_QUEUE4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1543 //VPEC_QUEUE4_RB_WPTR_HI 1544 #define VPEC_QUEUE4_RB_WPTR_HI__OFFSET__SHIFT 0x0 1545 #define VPEC_QUEUE4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1546 //VPEC_QUEUE4_RB_RPTR_ADDR_HI 1547 #define VPEC_QUEUE4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1548 #define VPEC_QUEUE4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1549 //VPEC_QUEUE4_RB_RPTR_ADDR_LO 1550 #define VPEC_QUEUE4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1551 #define VPEC_QUEUE4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1552 //VPEC_QUEUE4_RB_AQL_CNTL 1553 #define VPEC_QUEUE4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1554 #define VPEC_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1555 #define VPEC_QUEUE4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1556 #define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 1557 #define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 1558 #define VPEC_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 1559 #define VPEC_QUEUE4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1560 #define VPEC_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1561 #define VPEC_QUEUE4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1562 #define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L 1563 #define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L 1564 #define VPEC_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L 1565 //VPEC_QUEUE4_MINOR_PTR_UPDATE 1566 #define VPEC_QUEUE4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1567 #define VPEC_QUEUE4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1568 //VPEC_QUEUE4_CD_INFO 1569 #define VPEC_QUEUE4_CD_INFO__CD_INFO__SHIFT 0x0 1570 #define VPEC_QUEUE4_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL 1571 //VPEC_QUEUE4_RB_PREEMPT 1572 #define VPEC_QUEUE4_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 1573 #define VPEC_QUEUE4_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 1574 //VPEC_QUEUE4_SKIP_CNTL 1575 #define VPEC_QUEUE4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1576 #define VPEC_QUEUE4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1577 //VPEC_QUEUE4_DOORBELL 1578 #define VPEC_QUEUE4_DOORBELL__ENABLE__SHIFT 0x1c 1579 #define VPEC_QUEUE4_DOORBELL__CAPTURED__SHIFT 0x1e 1580 #define VPEC_QUEUE4_DOORBELL__ENABLE_MASK 0x10000000L 1581 #define VPEC_QUEUE4_DOORBELL__CAPTURED_MASK 0x40000000L 1582 //VPEC_QUEUE4_DOORBELL_OFFSET 1583 #define VPEC_QUEUE4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1584 #define VPEC_QUEUE4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1585 //VPEC_QUEUE4_DUMMY0 1586 #define VPEC_QUEUE4_DUMMY0__DUMMY__SHIFT 0x0 1587 #define VPEC_QUEUE4_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 1588 //VPEC_QUEUE4_DUMMY1 1589 #define VPEC_QUEUE4_DUMMY1__VALUE__SHIFT 0x0 1590 #define VPEC_QUEUE4_DUMMY1__VALUE_MASK 0xFFFFFFFFL 1591 //VPEC_QUEUE4_DUMMY2 1592 #define VPEC_QUEUE4_DUMMY2__VALUE__SHIFT 0x0 1593 #define VPEC_QUEUE4_DUMMY2__VALUE_MASK 0xFFFFFFFFL 1594 //VPEC_QUEUE4_DUMMY3 1595 #define VPEC_QUEUE4_DUMMY3__VALUE__SHIFT 0x0 1596 #define VPEC_QUEUE4_DUMMY3__VALUE_MASK 0xFFFFFFFFL 1597 //VPEC_QUEUE4_DUMMY4 1598 #define VPEC_QUEUE4_DUMMY4__VALUE__SHIFT 0x0 1599 #define VPEC_QUEUE4_DUMMY4__VALUE_MASK 0xFFFFFFFFL 1600 //VPEC_QUEUE4_IB_CNTL 1601 #define VPEC_QUEUE4_IB_CNTL__IB_ENABLE__SHIFT 0x0 1602 #define VPEC_QUEUE4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1603 #define VPEC_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1604 #define VPEC_QUEUE4_IB_CNTL__CMD_VMID__SHIFT 0x10 1605 #define VPEC_QUEUE4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1606 #define VPEC_QUEUE4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1607 #define VPEC_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1608 #define VPEC_QUEUE4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1609 //VPEC_QUEUE4_IB_RPTR 1610 #define VPEC_QUEUE4_IB_RPTR__OFFSET__SHIFT 0x2 1611 #define VPEC_QUEUE4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1612 //VPEC_QUEUE4_IB_OFFSET 1613 #define VPEC_QUEUE4_IB_OFFSET__OFFSET__SHIFT 0x2 1614 #define VPEC_QUEUE4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1615 //VPEC_QUEUE4_IB_BASE_LO 1616 #define VPEC_QUEUE4_IB_BASE_LO__ADDR__SHIFT 0x5 1617 #define VPEC_QUEUE4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1618 //VPEC_QUEUE4_IB_BASE_HI 1619 #define VPEC_QUEUE4_IB_BASE_HI__ADDR__SHIFT 0x0 1620 #define VPEC_QUEUE4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1621 //VPEC_QUEUE4_IB_SIZE 1622 #define VPEC_QUEUE4_IB_SIZE__SIZE__SHIFT 0x0 1623 #define VPEC_QUEUE4_IB_SIZE__SIZE_MASK 0x000FFFFFL 1624 //VPEC_QUEUE4_CMDIB_CNTL 1625 #define VPEC_QUEUE4_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 1626 #define VPEC_QUEUE4_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1627 #define VPEC_QUEUE4_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1628 #define VPEC_QUEUE4_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 1629 #define VPEC_QUEUE4_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L 1630 #define VPEC_QUEUE4_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1631 #define VPEC_QUEUE4_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1632 #define VPEC_QUEUE4_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L 1633 //VPEC_QUEUE4_CMDIB_RPTR 1634 #define VPEC_QUEUE4_CMDIB_RPTR__OFFSET__SHIFT 0x2 1635 #define VPEC_QUEUE4_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL 1636 //VPEC_QUEUE4_CMDIB_OFFSET 1637 #define VPEC_QUEUE4_CMDIB_OFFSET__OFFSET__SHIFT 0x2 1638 #define VPEC_QUEUE4_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL 1639 //VPEC_QUEUE4_CMDIB_BASE_LO 1640 #define VPEC_QUEUE4_CMDIB_BASE_LO__ADDR__SHIFT 0x5 1641 #define VPEC_QUEUE4_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1642 //VPEC_QUEUE4_CMDIB_BASE_HI 1643 #define VPEC_QUEUE4_CMDIB_BASE_HI__ADDR__SHIFT 0x0 1644 #define VPEC_QUEUE4_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1645 //VPEC_QUEUE4_CMDIB_SIZE 1646 #define VPEC_QUEUE4_CMDIB_SIZE__SIZE__SHIFT 0x0 1647 #define VPEC_QUEUE4_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL 1648 //VPEC_QUEUE4_CSA_ADDR_LO 1649 #define VPEC_QUEUE4_CSA_ADDR_LO__ADDR__SHIFT 0x0 1650 #define VPEC_QUEUE4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL 1651 //VPEC_QUEUE4_CSA_ADDR_HI 1652 #define VPEC_QUEUE4_CSA_ADDR_HI__ADDR__SHIFT 0x0 1653 #define VPEC_QUEUE4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1654 //VPEC_QUEUE4_CONTEXT_STATUS 1655 #define VPEC_QUEUE4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1656 #define VPEC_QUEUE4_CONTEXT_STATUS__USE_IB__SHIFT 0x1 1657 #define VPEC_QUEUE4_CONTEXT_STATUS__IDLE__SHIFT 0x2 1658 #define VPEC_QUEUE4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1659 #define VPEC_QUEUE4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1660 #define VPEC_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1661 #define VPEC_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1662 #define VPEC_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb 1663 #define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc 1664 #define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 1665 #define VPEC_QUEUE4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1666 #define VPEC_QUEUE4_CONTEXT_STATUS__USE_IB_MASK 0x00000002L 1667 #define VPEC_QUEUE4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1668 #define VPEC_QUEUE4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1669 #define VPEC_QUEUE4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1670 #define VPEC_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1671 #define VPEC_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1672 #define VPEC_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L 1673 #define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L 1674 #define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L 1675 //VPEC_QUEUE4_DOORBELL_LOG 1676 //VPEC_QUEUE4_IB_SUB_REMAIN 1677 #define VPEC_QUEUE4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1678 #define VPEC_QUEUE4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1679 //VPEC_QUEUE4_PREEMPT 1680 #define VPEC_QUEUE4_PREEMPT__IB_PREEMPT__SHIFT 0x0 1681 #define VPEC_QUEUE4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1682 //VPEC_QUEUE5_RB_CNTL 1683 #define VPEC_QUEUE5_RB_CNTL__RB_ENABLE__SHIFT 0x0 1684 #define VPEC_QUEUE5_RB_CNTL__RB_SIZE__SHIFT 0x1 1685 #define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 1686 #define VPEC_QUEUE5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1687 #define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa 1688 #define VPEC_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb 1689 #define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1690 #define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1691 #define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1692 #define VPEC_QUEUE5_RB_CNTL__RB_PRIV__SHIFT 0x17 1693 #define VPEC_QUEUE5_RB_CNTL__RB_VMID__SHIFT 0x18 1694 #define VPEC_QUEUE5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1695 #define VPEC_QUEUE5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1696 #define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L 1697 #define VPEC_QUEUE5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1698 #define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L 1699 #define VPEC_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L 1700 #define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1701 #define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1702 #define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1703 #define VPEC_QUEUE5_RB_CNTL__RB_PRIV_MASK 0x00800000L 1704 #define VPEC_QUEUE5_RB_CNTL__RB_VMID_MASK 0x0F000000L 1705 //VPEC_QUEUE5_SCHEDULE_CNTL 1706 #define VPEC_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 1707 #define VPEC_QUEUE5_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 1708 #define VPEC_QUEUE5_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 1709 #define VPEC_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 1710 #define VPEC_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L 1711 #define VPEC_QUEUE5_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL 1712 #define VPEC_QUEUE5_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L 1713 #define VPEC_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L 1714 //VPEC_QUEUE5_RB_BASE 1715 #define VPEC_QUEUE5_RB_BASE__ADDR__SHIFT 0x0 1716 #define VPEC_QUEUE5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1717 //VPEC_QUEUE5_RB_BASE_HI 1718 #define VPEC_QUEUE5_RB_BASE_HI__ADDR__SHIFT 0x0 1719 #define VPEC_QUEUE5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1720 //VPEC_QUEUE5_RB_RPTR 1721 #define VPEC_QUEUE5_RB_RPTR__OFFSET__SHIFT 0x0 1722 #define VPEC_QUEUE5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1723 //VPEC_QUEUE5_RB_RPTR_HI 1724 #define VPEC_QUEUE5_RB_RPTR_HI__OFFSET__SHIFT 0x0 1725 #define VPEC_QUEUE5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1726 //VPEC_QUEUE5_RB_WPTR 1727 #define VPEC_QUEUE5_RB_WPTR__OFFSET__SHIFT 0x0 1728 #define VPEC_QUEUE5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1729 //VPEC_QUEUE5_RB_WPTR_HI 1730 #define VPEC_QUEUE5_RB_WPTR_HI__OFFSET__SHIFT 0x0 1731 #define VPEC_QUEUE5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1732 //VPEC_QUEUE5_RB_RPTR_ADDR_HI 1733 #define VPEC_QUEUE5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1734 #define VPEC_QUEUE5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1735 //VPEC_QUEUE5_RB_RPTR_ADDR_LO 1736 #define VPEC_QUEUE5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1737 #define VPEC_QUEUE5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1738 //VPEC_QUEUE5_RB_AQL_CNTL 1739 #define VPEC_QUEUE5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1740 #define VPEC_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1741 #define VPEC_QUEUE5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1742 #define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 1743 #define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 1744 #define VPEC_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 1745 #define VPEC_QUEUE5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1746 #define VPEC_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1747 #define VPEC_QUEUE5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1748 #define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L 1749 #define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L 1750 #define VPEC_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L 1751 //VPEC_QUEUE5_MINOR_PTR_UPDATE 1752 #define VPEC_QUEUE5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1753 #define VPEC_QUEUE5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1754 //VPEC_QUEUE5_CD_INFO 1755 #define VPEC_QUEUE5_CD_INFO__CD_INFO__SHIFT 0x0 1756 #define VPEC_QUEUE5_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL 1757 //VPEC_QUEUE5_RB_PREEMPT 1758 #define VPEC_QUEUE5_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 1759 #define VPEC_QUEUE5_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 1760 //VPEC_QUEUE5_SKIP_CNTL 1761 #define VPEC_QUEUE5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1762 #define VPEC_QUEUE5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1763 //VPEC_QUEUE5_DOORBELL 1764 #define VPEC_QUEUE5_DOORBELL__ENABLE__SHIFT 0x1c 1765 #define VPEC_QUEUE5_DOORBELL__CAPTURED__SHIFT 0x1e 1766 #define VPEC_QUEUE5_DOORBELL__ENABLE_MASK 0x10000000L 1767 #define VPEC_QUEUE5_DOORBELL__CAPTURED_MASK 0x40000000L 1768 //VPEC_QUEUE5_DOORBELL_OFFSET 1769 #define VPEC_QUEUE5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1770 #define VPEC_QUEUE5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1771 //VPEC_QUEUE5_DUMMY0 1772 #define VPEC_QUEUE5_DUMMY0__DUMMY__SHIFT 0x0 1773 #define VPEC_QUEUE5_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 1774 //VPEC_QUEUE5_DUMMY1 1775 #define VPEC_QUEUE5_DUMMY1__VALUE__SHIFT 0x0 1776 #define VPEC_QUEUE5_DUMMY1__VALUE_MASK 0xFFFFFFFFL 1777 //VPEC_QUEUE5_DUMMY2 1778 #define VPEC_QUEUE5_DUMMY2__VALUE__SHIFT 0x0 1779 #define VPEC_QUEUE5_DUMMY2__VALUE_MASK 0xFFFFFFFFL 1780 //VPEC_QUEUE5_DUMMY3 1781 #define VPEC_QUEUE5_DUMMY3__VALUE__SHIFT 0x0 1782 #define VPEC_QUEUE5_DUMMY3__VALUE_MASK 0xFFFFFFFFL 1783 //VPEC_QUEUE5_DUMMY4 1784 #define VPEC_QUEUE5_DUMMY4__VALUE__SHIFT 0x0 1785 #define VPEC_QUEUE5_DUMMY4__VALUE_MASK 0xFFFFFFFFL 1786 //VPEC_QUEUE5_IB_CNTL 1787 #define VPEC_QUEUE5_IB_CNTL__IB_ENABLE__SHIFT 0x0 1788 #define VPEC_QUEUE5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1789 #define VPEC_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1790 #define VPEC_QUEUE5_IB_CNTL__CMD_VMID__SHIFT 0x10 1791 #define VPEC_QUEUE5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1792 #define VPEC_QUEUE5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1793 #define VPEC_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1794 #define VPEC_QUEUE5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1795 //VPEC_QUEUE5_IB_RPTR 1796 #define VPEC_QUEUE5_IB_RPTR__OFFSET__SHIFT 0x2 1797 #define VPEC_QUEUE5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1798 //VPEC_QUEUE5_IB_OFFSET 1799 #define VPEC_QUEUE5_IB_OFFSET__OFFSET__SHIFT 0x2 1800 #define VPEC_QUEUE5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1801 //VPEC_QUEUE5_IB_BASE_LO 1802 #define VPEC_QUEUE5_IB_BASE_LO__ADDR__SHIFT 0x5 1803 #define VPEC_QUEUE5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1804 //VPEC_QUEUE5_IB_BASE_HI 1805 #define VPEC_QUEUE5_IB_BASE_HI__ADDR__SHIFT 0x0 1806 #define VPEC_QUEUE5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1807 //VPEC_QUEUE5_IB_SIZE 1808 #define VPEC_QUEUE5_IB_SIZE__SIZE__SHIFT 0x0 1809 #define VPEC_QUEUE5_IB_SIZE__SIZE_MASK 0x000FFFFFL 1810 //VPEC_QUEUE5_CMDIB_CNTL 1811 #define VPEC_QUEUE5_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 1812 #define VPEC_QUEUE5_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1813 #define VPEC_QUEUE5_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1814 #define VPEC_QUEUE5_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 1815 #define VPEC_QUEUE5_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L 1816 #define VPEC_QUEUE5_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1817 #define VPEC_QUEUE5_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1818 #define VPEC_QUEUE5_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L 1819 //VPEC_QUEUE5_CMDIB_RPTR 1820 #define VPEC_QUEUE5_CMDIB_RPTR__OFFSET__SHIFT 0x2 1821 #define VPEC_QUEUE5_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL 1822 //VPEC_QUEUE5_CMDIB_OFFSET 1823 #define VPEC_QUEUE5_CMDIB_OFFSET__OFFSET__SHIFT 0x2 1824 #define VPEC_QUEUE5_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL 1825 //VPEC_QUEUE5_CMDIB_BASE_LO 1826 #define VPEC_QUEUE5_CMDIB_BASE_LO__ADDR__SHIFT 0x5 1827 #define VPEC_QUEUE5_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1828 //VPEC_QUEUE5_CMDIB_BASE_HI 1829 #define VPEC_QUEUE5_CMDIB_BASE_HI__ADDR__SHIFT 0x0 1830 #define VPEC_QUEUE5_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1831 //VPEC_QUEUE5_CMDIB_SIZE 1832 #define VPEC_QUEUE5_CMDIB_SIZE__SIZE__SHIFT 0x0 1833 #define VPEC_QUEUE5_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL 1834 //VPEC_QUEUE5_CSA_ADDR_LO 1835 #define VPEC_QUEUE5_CSA_ADDR_LO__ADDR__SHIFT 0x0 1836 #define VPEC_QUEUE5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL 1837 //VPEC_QUEUE5_CSA_ADDR_HI 1838 #define VPEC_QUEUE5_CSA_ADDR_HI__ADDR__SHIFT 0x0 1839 #define VPEC_QUEUE5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1840 //VPEC_QUEUE5_CONTEXT_STATUS 1841 #define VPEC_QUEUE5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1842 #define VPEC_QUEUE5_CONTEXT_STATUS__USE_IB__SHIFT 0x1 1843 #define VPEC_QUEUE5_CONTEXT_STATUS__IDLE__SHIFT 0x2 1844 #define VPEC_QUEUE5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1845 #define VPEC_QUEUE5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1846 #define VPEC_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1847 #define VPEC_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1848 #define VPEC_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb 1849 #define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc 1850 #define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 1851 #define VPEC_QUEUE5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1852 #define VPEC_QUEUE5_CONTEXT_STATUS__USE_IB_MASK 0x00000002L 1853 #define VPEC_QUEUE5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1854 #define VPEC_QUEUE5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1855 #define VPEC_QUEUE5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1856 #define VPEC_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1857 #define VPEC_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1858 #define VPEC_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L 1859 #define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L 1860 #define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L 1861 //VPEC_QUEUE5_DOORBELL_LOG 1862 //VPEC_QUEUE5_IB_SUB_REMAIN 1863 #define VPEC_QUEUE5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1864 #define VPEC_QUEUE5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1865 //VPEC_QUEUE5_PREEMPT 1866 #define VPEC_QUEUE5_PREEMPT__IB_PREEMPT__SHIFT 0x0 1867 #define VPEC_QUEUE5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1868 //VPEC_QUEUE6_RB_CNTL 1869 #define VPEC_QUEUE6_RB_CNTL__RB_ENABLE__SHIFT 0x0 1870 #define VPEC_QUEUE6_RB_CNTL__RB_SIZE__SHIFT 0x1 1871 #define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 1872 #define VPEC_QUEUE6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1873 #define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa 1874 #define VPEC_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb 1875 #define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1876 #define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1877 #define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1878 #define VPEC_QUEUE6_RB_CNTL__RB_PRIV__SHIFT 0x17 1879 #define VPEC_QUEUE6_RB_CNTL__RB_VMID__SHIFT 0x18 1880 #define VPEC_QUEUE6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1881 #define VPEC_QUEUE6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1882 #define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L 1883 #define VPEC_QUEUE6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1884 #define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L 1885 #define VPEC_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L 1886 #define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1887 #define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1888 #define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1889 #define VPEC_QUEUE6_RB_CNTL__RB_PRIV_MASK 0x00800000L 1890 #define VPEC_QUEUE6_RB_CNTL__RB_VMID_MASK 0x0F000000L 1891 //VPEC_QUEUE6_SCHEDULE_CNTL 1892 #define VPEC_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 1893 #define VPEC_QUEUE6_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 1894 #define VPEC_QUEUE6_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 1895 #define VPEC_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 1896 #define VPEC_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L 1897 #define VPEC_QUEUE6_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL 1898 #define VPEC_QUEUE6_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L 1899 #define VPEC_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L 1900 //VPEC_QUEUE6_RB_BASE 1901 #define VPEC_QUEUE6_RB_BASE__ADDR__SHIFT 0x0 1902 #define VPEC_QUEUE6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1903 //VPEC_QUEUE6_RB_BASE_HI 1904 #define VPEC_QUEUE6_RB_BASE_HI__ADDR__SHIFT 0x0 1905 #define VPEC_QUEUE6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1906 //VPEC_QUEUE6_RB_RPTR 1907 #define VPEC_QUEUE6_RB_RPTR__OFFSET__SHIFT 0x0 1908 #define VPEC_QUEUE6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1909 //VPEC_QUEUE6_RB_RPTR_HI 1910 #define VPEC_QUEUE6_RB_RPTR_HI__OFFSET__SHIFT 0x0 1911 #define VPEC_QUEUE6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1912 //VPEC_QUEUE6_RB_WPTR 1913 #define VPEC_QUEUE6_RB_WPTR__OFFSET__SHIFT 0x0 1914 #define VPEC_QUEUE6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1915 //VPEC_QUEUE6_RB_WPTR_HI 1916 #define VPEC_QUEUE6_RB_WPTR_HI__OFFSET__SHIFT 0x0 1917 #define VPEC_QUEUE6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1918 //VPEC_QUEUE6_RB_RPTR_ADDR_HI 1919 #define VPEC_QUEUE6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1920 #define VPEC_QUEUE6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1921 //VPEC_QUEUE6_RB_RPTR_ADDR_LO 1922 #define VPEC_QUEUE6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1923 #define VPEC_QUEUE6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1924 //VPEC_QUEUE6_RB_AQL_CNTL 1925 #define VPEC_QUEUE6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1926 #define VPEC_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1927 #define VPEC_QUEUE6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1928 #define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 1929 #define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 1930 #define VPEC_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 1931 #define VPEC_QUEUE6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1932 #define VPEC_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1933 #define VPEC_QUEUE6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1934 #define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L 1935 #define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L 1936 #define VPEC_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L 1937 //VPEC_QUEUE6_MINOR_PTR_UPDATE 1938 #define VPEC_QUEUE6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1939 #define VPEC_QUEUE6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1940 //VPEC_QUEUE6_CD_INFO 1941 #define VPEC_QUEUE6_CD_INFO__CD_INFO__SHIFT 0x0 1942 #define VPEC_QUEUE6_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL 1943 //VPEC_QUEUE6_RB_PREEMPT 1944 #define VPEC_QUEUE6_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 1945 #define VPEC_QUEUE6_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 1946 //VPEC_QUEUE6_SKIP_CNTL 1947 #define VPEC_QUEUE6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1948 #define VPEC_QUEUE6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1949 //VPEC_QUEUE6_DOORBELL 1950 #define VPEC_QUEUE6_DOORBELL__ENABLE__SHIFT 0x1c 1951 #define VPEC_QUEUE6_DOORBELL__CAPTURED__SHIFT 0x1e 1952 #define VPEC_QUEUE6_DOORBELL__ENABLE_MASK 0x10000000L 1953 #define VPEC_QUEUE6_DOORBELL__CAPTURED_MASK 0x40000000L 1954 //VPEC_QUEUE6_DOORBELL_OFFSET 1955 #define VPEC_QUEUE6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1956 #define VPEC_QUEUE6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1957 //VPEC_QUEUE6_DUMMY0 1958 #define VPEC_QUEUE6_DUMMY0__DUMMY__SHIFT 0x0 1959 #define VPEC_QUEUE6_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 1960 //VPEC_QUEUE6_DUMMY1 1961 #define VPEC_QUEUE6_DUMMY1__VALUE__SHIFT 0x0 1962 #define VPEC_QUEUE6_DUMMY1__VALUE_MASK 0xFFFFFFFFL 1963 //VPEC_QUEUE6_DUMMY2 1964 #define VPEC_QUEUE6_DUMMY2__VALUE__SHIFT 0x0 1965 #define VPEC_QUEUE6_DUMMY2__VALUE_MASK 0xFFFFFFFFL 1966 //VPEC_QUEUE6_DUMMY3 1967 #define VPEC_QUEUE6_DUMMY3__VALUE__SHIFT 0x0 1968 #define VPEC_QUEUE6_DUMMY3__VALUE_MASK 0xFFFFFFFFL 1969 //VPEC_QUEUE6_DUMMY4 1970 #define VPEC_QUEUE6_DUMMY4__VALUE__SHIFT 0x0 1971 #define VPEC_QUEUE6_DUMMY4__VALUE_MASK 0xFFFFFFFFL 1972 //VPEC_QUEUE6_IB_CNTL 1973 #define VPEC_QUEUE6_IB_CNTL__IB_ENABLE__SHIFT 0x0 1974 #define VPEC_QUEUE6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1975 #define VPEC_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1976 #define VPEC_QUEUE6_IB_CNTL__CMD_VMID__SHIFT 0x10 1977 #define VPEC_QUEUE6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1978 #define VPEC_QUEUE6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1979 #define VPEC_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1980 #define VPEC_QUEUE6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1981 //VPEC_QUEUE6_IB_RPTR 1982 #define VPEC_QUEUE6_IB_RPTR__OFFSET__SHIFT 0x2 1983 #define VPEC_QUEUE6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1984 //VPEC_QUEUE6_IB_OFFSET 1985 #define VPEC_QUEUE6_IB_OFFSET__OFFSET__SHIFT 0x2 1986 #define VPEC_QUEUE6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1987 //VPEC_QUEUE6_IB_BASE_LO 1988 #define VPEC_QUEUE6_IB_BASE_LO__ADDR__SHIFT 0x5 1989 #define VPEC_QUEUE6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1990 //VPEC_QUEUE6_IB_BASE_HI 1991 #define VPEC_QUEUE6_IB_BASE_HI__ADDR__SHIFT 0x0 1992 #define VPEC_QUEUE6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1993 //VPEC_QUEUE6_IB_SIZE 1994 #define VPEC_QUEUE6_IB_SIZE__SIZE__SHIFT 0x0 1995 #define VPEC_QUEUE6_IB_SIZE__SIZE_MASK 0x000FFFFFL 1996 //VPEC_QUEUE6_CMDIB_CNTL 1997 #define VPEC_QUEUE6_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 1998 #define VPEC_QUEUE6_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1999 #define VPEC_QUEUE6_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2000 #define VPEC_QUEUE6_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 2001 #define VPEC_QUEUE6_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L 2002 #define VPEC_QUEUE6_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2003 #define VPEC_QUEUE6_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2004 #define VPEC_QUEUE6_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L 2005 //VPEC_QUEUE6_CMDIB_RPTR 2006 #define VPEC_QUEUE6_CMDIB_RPTR__OFFSET__SHIFT 0x2 2007 #define VPEC_QUEUE6_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL 2008 //VPEC_QUEUE6_CMDIB_OFFSET 2009 #define VPEC_QUEUE6_CMDIB_OFFSET__OFFSET__SHIFT 0x2 2010 #define VPEC_QUEUE6_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL 2011 //VPEC_QUEUE6_CMDIB_BASE_LO 2012 #define VPEC_QUEUE6_CMDIB_BASE_LO__ADDR__SHIFT 0x5 2013 #define VPEC_QUEUE6_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2014 //VPEC_QUEUE6_CMDIB_BASE_HI 2015 #define VPEC_QUEUE6_CMDIB_BASE_HI__ADDR__SHIFT 0x0 2016 #define VPEC_QUEUE6_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2017 //VPEC_QUEUE6_CMDIB_SIZE 2018 #define VPEC_QUEUE6_CMDIB_SIZE__SIZE__SHIFT 0x0 2019 #define VPEC_QUEUE6_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL 2020 //VPEC_QUEUE6_CSA_ADDR_LO 2021 #define VPEC_QUEUE6_CSA_ADDR_LO__ADDR__SHIFT 0x0 2022 #define VPEC_QUEUE6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL 2023 //VPEC_QUEUE6_CSA_ADDR_HI 2024 #define VPEC_QUEUE6_CSA_ADDR_HI__ADDR__SHIFT 0x0 2025 #define VPEC_QUEUE6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2026 //VPEC_QUEUE6_CONTEXT_STATUS 2027 #define VPEC_QUEUE6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2028 #define VPEC_QUEUE6_CONTEXT_STATUS__USE_IB__SHIFT 0x1 2029 #define VPEC_QUEUE6_CONTEXT_STATUS__IDLE__SHIFT 0x2 2030 #define VPEC_QUEUE6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2031 #define VPEC_QUEUE6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2032 #define VPEC_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2033 #define VPEC_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2034 #define VPEC_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb 2035 #define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc 2036 #define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 2037 #define VPEC_QUEUE6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2038 #define VPEC_QUEUE6_CONTEXT_STATUS__USE_IB_MASK 0x00000002L 2039 #define VPEC_QUEUE6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2040 #define VPEC_QUEUE6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2041 #define VPEC_QUEUE6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2042 #define VPEC_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2043 #define VPEC_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2044 #define VPEC_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L 2045 #define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L 2046 #define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L 2047 //VPEC_QUEUE6_DOORBELL_LOG 2048 //VPEC_QUEUE6_IB_SUB_REMAIN 2049 #define VPEC_QUEUE6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2050 #define VPEC_QUEUE6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 2051 //VPEC_QUEUE6_PREEMPT 2052 #define VPEC_QUEUE6_PREEMPT__IB_PREEMPT__SHIFT 0x0 2053 #define VPEC_QUEUE6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2054 //VPEC_QUEUE7_RB_CNTL 2055 #define VPEC_QUEUE7_RB_CNTL__RB_ENABLE__SHIFT 0x0 2056 #define VPEC_QUEUE7_RB_CNTL__RB_SIZE__SHIFT 0x1 2057 #define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 2058 #define VPEC_QUEUE7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2059 #define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa 2060 #define VPEC_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb 2061 #define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2062 #define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2063 #define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2064 #define VPEC_QUEUE7_RB_CNTL__RB_PRIV__SHIFT 0x17 2065 #define VPEC_QUEUE7_RB_CNTL__RB_VMID__SHIFT 0x18 2066 #define VPEC_QUEUE7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2067 #define VPEC_QUEUE7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2068 #define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L 2069 #define VPEC_QUEUE7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2070 #define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L 2071 #define VPEC_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L 2072 #define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2073 #define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2074 #define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2075 #define VPEC_QUEUE7_RB_CNTL__RB_PRIV_MASK 0x00800000L 2076 #define VPEC_QUEUE7_RB_CNTL__RB_VMID_MASK 0x0F000000L 2077 //VPEC_QUEUE7_SCHEDULE_CNTL 2078 #define VPEC_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 2079 #define VPEC_QUEUE7_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 2080 #define VPEC_QUEUE7_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 2081 #define VPEC_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 2082 #define VPEC_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L 2083 #define VPEC_QUEUE7_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL 2084 #define VPEC_QUEUE7_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L 2085 #define VPEC_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L 2086 //VPEC_QUEUE7_RB_BASE 2087 #define VPEC_QUEUE7_RB_BASE__ADDR__SHIFT 0x0 2088 #define VPEC_QUEUE7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2089 //VPEC_QUEUE7_RB_BASE_HI 2090 #define VPEC_QUEUE7_RB_BASE_HI__ADDR__SHIFT 0x0 2091 #define VPEC_QUEUE7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2092 //VPEC_QUEUE7_RB_RPTR 2093 #define VPEC_QUEUE7_RB_RPTR__OFFSET__SHIFT 0x0 2094 #define VPEC_QUEUE7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2095 //VPEC_QUEUE7_RB_RPTR_HI 2096 #define VPEC_QUEUE7_RB_RPTR_HI__OFFSET__SHIFT 0x0 2097 #define VPEC_QUEUE7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2098 //VPEC_QUEUE7_RB_WPTR 2099 #define VPEC_QUEUE7_RB_WPTR__OFFSET__SHIFT 0x0 2100 #define VPEC_QUEUE7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2101 //VPEC_QUEUE7_RB_WPTR_HI 2102 #define VPEC_QUEUE7_RB_WPTR_HI__OFFSET__SHIFT 0x0 2103 #define VPEC_QUEUE7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2104 //VPEC_QUEUE7_RB_RPTR_ADDR_HI 2105 #define VPEC_QUEUE7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2106 #define VPEC_QUEUE7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2107 //VPEC_QUEUE7_RB_RPTR_ADDR_LO 2108 #define VPEC_QUEUE7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2109 #define VPEC_QUEUE7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2110 //VPEC_QUEUE7_RB_AQL_CNTL 2111 #define VPEC_QUEUE7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2112 #define VPEC_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2113 #define VPEC_QUEUE7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2114 #define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 2115 #define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 2116 #define VPEC_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 2117 #define VPEC_QUEUE7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2118 #define VPEC_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2119 #define VPEC_QUEUE7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2120 #define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L 2121 #define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L 2122 #define VPEC_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L 2123 //VPEC_QUEUE7_MINOR_PTR_UPDATE 2124 #define VPEC_QUEUE7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2125 #define VPEC_QUEUE7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2126 //VPEC_QUEUE7_CD_INFO 2127 #define VPEC_QUEUE7_CD_INFO__CD_INFO__SHIFT 0x0 2128 #define VPEC_QUEUE7_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL 2129 //VPEC_QUEUE7_RB_PREEMPT 2130 #define VPEC_QUEUE7_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 2131 #define VPEC_QUEUE7_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 2132 //VPEC_QUEUE7_SKIP_CNTL 2133 #define VPEC_QUEUE7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2134 #define VPEC_QUEUE7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2135 //VPEC_QUEUE7_DOORBELL 2136 #define VPEC_QUEUE7_DOORBELL__ENABLE__SHIFT 0x1c 2137 #define VPEC_QUEUE7_DOORBELL__CAPTURED__SHIFT 0x1e 2138 #define VPEC_QUEUE7_DOORBELL__ENABLE_MASK 0x10000000L 2139 #define VPEC_QUEUE7_DOORBELL__CAPTURED_MASK 0x40000000L 2140 //VPEC_QUEUE7_DOORBELL_OFFSET 2141 #define VPEC_QUEUE7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2142 #define VPEC_QUEUE7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2143 //VPEC_QUEUE7_DUMMY0 2144 #define VPEC_QUEUE7_DUMMY0__DUMMY__SHIFT 0x0 2145 #define VPEC_QUEUE7_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 2146 //VPEC_QUEUE7_DUMMY1 2147 #define VPEC_QUEUE7_DUMMY1__VALUE__SHIFT 0x0 2148 #define VPEC_QUEUE7_DUMMY1__VALUE_MASK 0xFFFFFFFFL 2149 //VPEC_QUEUE7_DUMMY2 2150 #define VPEC_QUEUE7_DUMMY2__VALUE__SHIFT 0x0 2151 #define VPEC_QUEUE7_DUMMY2__VALUE_MASK 0xFFFFFFFFL 2152 //VPEC_QUEUE7_DUMMY3 2153 #define VPEC_QUEUE7_DUMMY3__VALUE__SHIFT 0x0 2154 #define VPEC_QUEUE7_DUMMY3__VALUE_MASK 0xFFFFFFFFL 2155 //VPEC_QUEUE7_DUMMY4 2156 #define VPEC_QUEUE7_DUMMY4__VALUE__SHIFT 0x0 2157 #define VPEC_QUEUE7_DUMMY4__VALUE_MASK 0xFFFFFFFFL 2158 //VPEC_QUEUE7_IB_CNTL 2159 #define VPEC_QUEUE7_IB_CNTL__IB_ENABLE__SHIFT 0x0 2160 #define VPEC_QUEUE7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2161 #define VPEC_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2162 #define VPEC_QUEUE7_IB_CNTL__CMD_VMID__SHIFT 0x10 2163 #define VPEC_QUEUE7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2164 #define VPEC_QUEUE7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2165 #define VPEC_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2166 #define VPEC_QUEUE7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2167 //VPEC_QUEUE7_IB_RPTR 2168 #define VPEC_QUEUE7_IB_RPTR__OFFSET__SHIFT 0x2 2169 #define VPEC_QUEUE7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2170 //VPEC_QUEUE7_IB_OFFSET 2171 #define VPEC_QUEUE7_IB_OFFSET__OFFSET__SHIFT 0x2 2172 #define VPEC_QUEUE7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2173 //VPEC_QUEUE7_IB_BASE_LO 2174 #define VPEC_QUEUE7_IB_BASE_LO__ADDR__SHIFT 0x5 2175 #define VPEC_QUEUE7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2176 //VPEC_QUEUE7_IB_BASE_HI 2177 #define VPEC_QUEUE7_IB_BASE_HI__ADDR__SHIFT 0x0 2178 #define VPEC_QUEUE7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2179 //VPEC_QUEUE7_IB_SIZE 2180 #define VPEC_QUEUE7_IB_SIZE__SIZE__SHIFT 0x0 2181 #define VPEC_QUEUE7_IB_SIZE__SIZE_MASK 0x000FFFFFL 2182 //VPEC_QUEUE7_CMDIB_CNTL 2183 #define VPEC_QUEUE7_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 2184 #define VPEC_QUEUE7_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2185 #define VPEC_QUEUE7_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2186 #define VPEC_QUEUE7_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 2187 #define VPEC_QUEUE7_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L 2188 #define VPEC_QUEUE7_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2189 #define VPEC_QUEUE7_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2190 #define VPEC_QUEUE7_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L 2191 //VPEC_QUEUE7_CMDIB_RPTR 2192 #define VPEC_QUEUE7_CMDIB_RPTR__OFFSET__SHIFT 0x2 2193 #define VPEC_QUEUE7_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL 2194 //VPEC_QUEUE7_CMDIB_OFFSET 2195 #define VPEC_QUEUE7_CMDIB_OFFSET__OFFSET__SHIFT 0x2 2196 #define VPEC_QUEUE7_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL 2197 //VPEC_QUEUE7_CMDIB_BASE_LO 2198 #define VPEC_QUEUE7_CMDIB_BASE_LO__ADDR__SHIFT 0x5 2199 #define VPEC_QUEUE7_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2200 //VPEC_QUEUE7_CMDIB_BASE_HI 2201 #define VPEC_QUEUE7_CMDIB_BASE_HI__ADDR__SHIFT 0x0 2202 #define VPEC_QUEUE7_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2203 //VPEC_QUEUE7_CMDIB_SIZE 2204 #define VPEC_QUEUE7_CMDIB_SIZE__SIZE__SHIFT 0x0 2205 #define VPEC_QUEUE7_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL 2206 //VPEC_QUEUE7_CSA_ADDR_LO 2207 #define VPEC_QUEUE7_CSA_ADDR_LO__ADDR__SHIFT 0x0 2208 #define VPEC_QUEUE7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL 2209 //VPEC_QUEUE7_CSA_ADDR_HI 2210 #define VPEC_QUEUE7_CSA_ADDR_HI__ADDR__SHIFT 0x0 2211 #define VPEC_QUEUE7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2212 //VPEC_QUEUE7_CONTEXT_STATUS 2213 #define VPEC_QUEUE7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2214 #define VPEC_QUEUE7_CONTEXT_STATUS__USE_IB__SHIFT 0x1 2215 #define VPEC_QUEUE7_CONTEXT_STATUS__IDLE__SHIFT 0x2 2216 #define VPEC_QUEUE7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2217 #define VPEC_QUEUE7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2218 #define VPEC_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2219 #define VPEC_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2220 #define VPEC_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb 2221 #define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc 2222 #define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 2223 #define VPEC_QUEUE7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2224 #define VPEC_QUEUE7_CONTEXT_STATUS__USE_IB_MASK 0x00000002L 2225 #define VPEC_QUEUE7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2226 #define VPEC_QUEUE7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2227 #define VPEC_QUEUE7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2228 #define VPEC_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2229 #define VPEC_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2230 #define VPEC_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L 2231 #define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L 2232 #define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L 2233 //VPEC_QUEUE7_DOORBELL_LOG 2234 //VPEC_QUEUE7_IB_SUB_REMAIN 2235 #define VPEC_QUEUE7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2236 #define VPEC_QUEUE7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 2237 //VPEC_QUEUE7_PREEMPT 2238 #define VPEC_QUEUE7_PREEMPT__IB_PREEMPT__SHIFT 0x0 2239 #define VPEC_QUEUE7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2240 2241 2242 // addressBlock: vpe_vpep_vpdpp0_dispdec_vpcnvc_cfg_dispdec 2243 //VPCNVC_SURFACE_PIXEL_FORMAT 2244 #define VPCNVC_SURFACE_PIXEL_FORMAT__VPCNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 2245 #define VPCNVC_SURFACE_PIXEL_FORMAT__VPCNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL 2246 //VPCNVC_FORMAT_CONTROL 2247 #define VPCNVC_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 2248 #define VPCNVC_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 2249 #define VPCNVC_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 2250 #define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS__SHIFT 0xc 2251 #define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS_MSB_ALIGN__SHIFT 0xd 2252 #define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 2253 #define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 2254 #define VPCNVC_FORMAT_CONTROL__VPCNVC_UPDATE_PENDING__SHIFT 0x14 2255 #define VPCNVC_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L 2256 #define VPCNVC_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L 2257 #define VPCNVC_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L 2258 #define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS_MASK 0x00001000L 2259 #define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L 2260 #define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L 2261 #define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L 2262 #define VPCNVC_FORMAT_CONTROL__VPCNVC_UPDATE_PENDING_MASK 0x00100000L 2263 //VPCNVC_FCNV_FP_BIAS_R 2264 #define VPCNVC_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 2265 #define VPCNVC_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL 2266 //VPCNVC_FCNV_FP_BIAS_G 2267 #define VPCNVC_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 2268 #define VPCNVC_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL 2269 //VPCNVC_FCNV_FP_BIAS_B 2270 #define VPCNVC_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 2271 #define VPCNVC_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL 2272 //VPCNVC_FCNV_FP_SCALE_R 2273 #define VPCNVC_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 2274 #define VPCNVC_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL 2275 //VPCNVC_FCNV_FP_SCALE_G 2276 #define VPCNVC_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 2277 #define VPCNVC_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL 2278 //VPCNVC_FCNV_FP_SCALE_B 2279 #define VPCNVC_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 2280 #define VPCNVC_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL 2281 //VPCNVC_COLOR_KEYER_CONTROL 2282 #define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 2283 #define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 2284 #define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L 2285 #define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L 2286 //VPCNVC_COLOR_KEYER_ALPHA 2287 #define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 2288 #define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 2289 #define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL 2290 #define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L 2291 //VPCNVC_COLOR_KEYER_RED 2292 #define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 2293 #define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 2294 #define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL 2295 #define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L 2296 //VPCNVC_COLOR_KEYER_GREEN 2297 #define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 2298 #define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 2299 #define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL 2300 #define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L 2301 //VPCNVC_COLOR_KEYER_BLUE 2302 #define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 2303 #define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 2304 #define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL 2305 #define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L 2306 //VPCNVC_ALPHA_2BIT_LUT 2307 #define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 2308 #define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 2309 #define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 2310 #define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 2311 #define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL 2312 #define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L 2313 #define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L 2314 #define VPCNVC_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L 2315 //VPCNVC_PRE_DEALPHA 2316 #define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 2317 #define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 2318 #define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L 2319 #define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L 2320 //VPCNVC_PRE_CSC_MODE 2321 #define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 2322 #define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 2323 #define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000001L 2324 #define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x00000004L 2325 //VPCNVC_PRE_CSC_C11_C12 2326 #define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 2327 #define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 2328 #define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL 2329 #define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L 2330 //VPCNVC_PRE_CSC_C13_C14 2331 #define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 2332 #define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 2333 #define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL 2334 #define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L 2335 //VPCNVC_PRE_CSC_C21_C22 2336 #define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 2337 #define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 2338 #define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL 2339 #define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L 2340 //VPCNVC_PRE_CSC_C23_C24 2341 #define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 2342 #define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 2343 #define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL 2344 #define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L 2345 //VPCNVC_PRE_CSC_C31_C32 2346 #define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 2347 #define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 2348 #define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL 2349 #define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L 2350 //VPCNVC_PRE_CSC_C33_C34 2351 #define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 2352 #define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 2353 #define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL 2354 #define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L 2355 //VPCNVC_COEF_FORMAT 2356 #define VPCNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 2357 #define VPCNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L 2358 //VPCNVC_PRE_DEGAM 2359 #define VPCNVC_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 2360 #define VPCNVC_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 2361 #define VPCNVC_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L 2362 #define VPCNVC_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L 2363 //VPCNVC_PRE_REALPHA 2364 #define VPCNVC_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 2365 #define VPCNVC_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 2366 #define VPCNVC_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L 2367 #define VPCNVC_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L 2368 2369 2370 // addressBlock: vpe_vpep_vpdpp0_dispdec_vpdscl_dispdec 2371 //VPDSCL_COEF_RAM_TAP_SELECT 2372 #define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 2373 #define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 2374 #define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 2375 #define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L 2376 #define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L 2377 #define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L 2378 //VPDSCL_COEF_RAM_TAP_DATA 2379 #define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 2380 #define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf 2381 #define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 2382 #define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f 2383 #define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL 2384 #define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L 2385 #define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L 2386 #define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L 2387 //VPDSCL_MODE 2388 #define VPDSCL_MODE__VPDSCL_MODE__SHIFT 0x0 2389 #define VPDSCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc 2390 #define VPDSCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 2391 #define VPDSCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 2392 #define VPDSCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 2393 #define VPDSCL_MODE__VPDSCL_MODE_MASK 0x00000007L 2394 #define VPDSCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L 2395 #define VPDSCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L 2396 #define VPDSCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L 2397 #define VPDSCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L 2398 //VPDSCL_TAP_CONTROL 2399 #define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 2400 #define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 2401 #define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 2402 #define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc 2403 #define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L 2404 #define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L 2405 #define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L 2406 #define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L 2407 //VPDSCL_CONTROL 2408 #define VPDSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 2409 #define VPDSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L 2410 //VPDSCL_2TAP_CONTROL 2411 #define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 2412 #define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 2413 #define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 2414 #define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 2415 #define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 2416 #define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 2417 #define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L 2418 #define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L 2419 #define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L 2420 #define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L 2421 #define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L 2422 #define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L 2423 //VPDSCL_MANUAL_REPLICATE_CONTROL 2424 #define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 2425 #define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 2426 #define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL 2427 #define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L 2428 //VPDSCL_HORZ_FILTER_SCALE_RATIO 2429 #define VPDSCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 2430 #define VPDSCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL 2431 //VPDSCL_HORZ_FILTER_INIT 2432 #define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 2433 #define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 2434 #define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL 2435 #define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L 2436 //VPDSCL_HORZ_FILTER_SCALE_RATIO_C 2437 #define VPDSCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 2438 #define VPDSCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL 2439 //VPDSCL_HORZ_FILTER_INIT_C 2440 #define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 2441 #define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 2442 #define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL 2443 #define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L 2444 //VPDSCL_VERT_FILTER_SCALE_RATIO 2445 #define VPDSCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 2446 #define VPDSCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL 2447 //VPDSCL_VERT_FILTER_INIT 2448 #define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 2449 #define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 2450 #define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL 2451 #define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L 2452 //VPDSCL_VERT_FILTER_INIT_BOT 2453 #define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 2454 #define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 2455 #define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL 2456 #define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L 2457 //VPDSCL_VERT_FILTER_SCALE_RATIO_C 2458 #define VPDSCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 2459 #define VPDSCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL 2460 //VPDSCL_VERT_FILTER_INIT_C 2461 #define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 2462 #define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 2463 #define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL 2464 #define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L 2465 //VPDSCL_VERT_FILTER_INIT_BOT_C 2466 #define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 2467 #define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 2468 #define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL 2469 #define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L 2470 //VPDSCL_BLACK_COLOR 2471 #define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 2472 #define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 2473 #define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL 2474 #define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L 2475 //VPDSCL_UPDATE 2476 #define VPDSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 2477 #define VPDSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L 2478 //VPDSCL_AUTOCAL 2479 #define VPDSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 2480 #define VPDSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L 2481 //VPDSCL_EXT_OVERSCAN_LEFT_RIGHT 2482 #define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 2483 #define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 2484 #define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL 2485 #define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L 2486 //VPDSCL_EXT_OVERSCAN_TOP_BOTTOM 2487 #define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 2488 #define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 2489 #define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL 2490 #define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L 2491 //VPOTG_H_BLANK 2492 #define VPOTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 2493 #define VPOTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 2494 #define VPOTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL 2495 #define VPOTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L 2496 //VPOTG_V_BLANK 2497 #define VPOTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 2498 #define VPOTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 2499 #define VPOTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL 2500 #define VPOTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L 2501 //VPDSCL_RECOUT_START 2502 #define VPDSCL_RECOUT_START__RECOUT_START_X__SHIFT 0x0 2503 #define VPDSCL_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 2504 #define VPDSCL_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL 2505 #define VPDSCL_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L 2506 //VPDSCL_RECOUT_SIZE 2507 #define VPDSCL_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 2508 #define VPDSCL_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 2509 #define VPDSCL_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL 2510 #define VPDSCL_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L 2511 //VPMPC_SIZE 2512 #define VPMPC_SIZE__VPMPC_WIDTH__SHIFT 0x0 2513 #define VPMPC_SIZE__VPMPC_HEIGHT__SHIFT 0x10 2514 #define VPMPC_SIZE__VPMPC_WIDTH_MASK 0x00003FFFL 2515 #define VPMPC_SIZE__VPMPC_HEIGHT_MASK 0x3FFF0000L 2516 //VPLB_DATA_FORMAT 2517 #define VPLB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 2518 #define VPLB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L 2519 //VPLB_MEMORY_CTRL 2520 #define VPLB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 2521 #define VPLB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 2522 #define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 2523 #define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 2524 #define VPLB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L 2525 #define VPLB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L 2526 #define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L 2527 #define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L 2528 //VPLB_V_COUNTER 2529 #define VPLB_V_COUNTER__V_COUNTER__SHIFT 0x0 2530 #define VPLB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 2531 #define VPLB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL 2532 #define VPLB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L 2533 //VPDSCL_MEM_PWR_CTRL 2534 #define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 2535 #define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 2536 #define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 2537 #define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 2538 #define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 2539 #define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa 2540 #define VPDSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c 2541 #define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L 2542 #define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L 2543 #define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L 2544 #define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L 2545 #define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L 2546 #define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L 2547 #define VPDSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L 2548 //VPDSCL_MEM_PWR_STATUS 2549 #define VPDSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 2550 #define VPDSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 2551 #define VPDSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 2552 #define VPDSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L 2553 #define VPDSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL 2554 #define VPDSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L 2555 2556 2557 // addressBlock: vpe_vpep_vpdpp0_dispdec_vpcm_dispdec 2558 //VPCM_CONTROL 2559 #define VPCM_CONTROL__VPCM_BYPASS__SHIFT 0x0 2560 #define VPCM_CONTROL__VPCM_UPDATE_PENDING__SHIFT 0x8 2561 #define VPCM_CONTROL__VPCM_BYPASS_MASK 0x00000001L 2562 #define VPCM_CONTROL__VPCM_UPDATE_PENDING_MASK 0x00000100L 2563 //VPCM_POST_CSC_CONTROL 2564 #define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE__SHIFT 0x0 2565 #define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE_CURRENT__SHIFT 0x2 2566 #define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE_MASK 0x00000001L 2567 #define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE_CURRENT_MASK 0x00000004L 2568 //VPCM_POST_CSC_C11_C12 2569 #define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C11__SHIFT 0x0 2570 #define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C12__SHIFT 0x10 2571 #define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C11_MASK 0x0000FFFFL 2572 #define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C12_MASK 0xFFFF0000L 2573 //VPCM_POST_CSC_C13_C14 2574 #define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C13__SHIFT 0x0 2575 #define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C14__SHIFT 0x10 2576 #define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C13_MASK 0x0000FFFFL 2577 #define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C14_MASK 0xFFFF0000L 2578 //VPCM_POST_CSC_C21_C22 2579 #define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C21__SHIFT 0x0 2580 #define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C22__SHIFT 0x10 2581 #define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C21_MASK 0x0000FFFFL 2582 #define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C22_MASK 0xFFFF0000L 2583 //VPCM_POST_CSC_C23_C24 2584 #define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C23__SHIFT 0x0 2585 #define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C24__SHIFT 0x10 2586 #define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C23_MASK 0x0000FFFFL 2587 #define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C24_MASK 0xFFFF0000L 2588 //VPCM_POST_CSC_C31_C32 2589 #define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C31__SHIFT 0x0 2590 #define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C32__SHIFT 0x10 2591 #define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C31_MASK 0x0000FFFFL 2592 #define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C32_MASK 0xFFFF0000L 2593 //VPCM_POST_CSC_C33_C34 2594 #define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C33__SHIFT 0x0 2595 #define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C34__SHIFT 0x10 2596 #define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C33_MASK 0x0000FFFFL 2597 #define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C34_MASK 0xFFFF0000L 2598 //VPCM_GAMUT_REMAP_CONTROL 2599 #define VPCM_GAMUT_REMAP_CONTROL__VPCM_GAMUT_REMAP_MODE__SHIFT 0x0 2600 #define VPCM_GAMUT_REMAP_CONTROL__VPCM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x2 2601 #define VPCM_GAMUT_REMAP_CONTROL__VPCM_GAMUT_REMAP_MODE_MASK 0x00000001L 2602 #define VPCM_GAMUT_REMAP_CONTROL__VPCM_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000004L 2603 //VPCM_GAMUT_REMAP_C11_C12 2604 #define VPCM_GAMUT_REMAP_C11_C12__VPCM_GAMUT_REMAP_C11__SHIFT 0x0 2605 #define VPCM_GAMUT_REMAP_C11_C12__VPCM_GAMUT_REMAP_C12__SHIFT 0x10 2606 #define VPCM_GAMUT_REMAP_C11_C12__VPCM_GAMUT_REMAP_C11_MASK 0x0000FFFFL 2607 #define VPCM_GAMUT_REMAP_C11_C12__VPCM_GAMUT_REMAP_C12_MASK 0xFFFF0000L 2608 //VPCM_GAMUT_REMAP_C13_C14 2609 #define VPCM_GAMUT_REMAP_C13_C14__VPCM_GAMUT_REMAP_C13__SHIFT 0x0 2610 #define VPCM_GAMUT_REMAP_C13_C14__VPCM_GAMUT_REMAP_C14__SHIFT 0x10 2611 #define VPCM_GAMUT_REMAP_C13_C14__VPCM_GAMUT_REMAP_C13_MASK 0x0000FFFFL 2612 #define VPCM_GAMUT_REMAP_C13_C14__VPCM_GAMUT_REMAP_C14_MASK 0xFFFF0000L 2613 //VPCM_GAMUT_REMAP_C21_C22 2614 #define VPCM_GAMUT_REMAP_C21_C22__VPCM_GAMUT_REMAP_C21__SHIFT 0x0 2615 #define VPCM_GAMUT_REMAP_C21_C22__VPCM_GAMUT_REMAP_C22__SHIFT 0x10 2616 #define VPCM_GAMUT_REMAP_C21_C22__VPCM_GAMUT_REMAP_C21_MASK 0x0000FFFFL 2617 #define VPCM_GAMUT_REMAP_C21_C22__VPCM_GAMUT_REMAP_C22_MASK 0xFFFF0000L 2618 //VPCM_GAMUT_REMAP_C23_C24 2619 #define VPCM_GAMUT_REMAP_C23_C24__VPCM_GAMUT_REMAP_C23__SHIFT 0x0 2620 #define VPCM_GAMUT_REMAP_C23_C24__VPCM_GAMUT_REMAP_C24__SHIFT 0x10 2621 #define VPCM_GAMUT_REMAP_C23_C24__VPCM_GAMUT_REMAP_C23_MASK 0x0000FFFFL 2622 #define VPCM_GAMUT_REMAP_C23_C24__VPCM_GAMUT_REMAP_C24_MASK 0xFFFF0000L 2623 //VPCM_GAMUT_REMAP_C31_C32 2624 #define VPCM_GAMUT_REMAP_C31_C32__VPCM_GAMUT_REMAP_C31__SHIFT 0x0 2625 #define VPCM_GAMUT_REMAP_C31_C32__VPCM_GAMUT_REMAP_C32__SHIFT 0x10 2626 #define VPCM_GAMUT_REMAP_C31_C32__VPCM_GAMUT_REMAP_C31_MASK 0x0000FFFFL 2627 #define VPCM_GAMUT_REMAP_C31_C32__VPCM_GAMUT_REMAP_C32_MASK 0xFFFF0000L 2628 //VPCM_GAMUT_REMAP_C33_C34 2629 #define VPCM_GAMUT_REMAP_C33_C34__VPCM_GAMUT_REMAP_C33__SHIFT 0x0 2630 #define VPCM_GAMUT_REMAP_C33_C34__VPCM_GAMUT_REMAP_C34__SHIFT 0x10 2631 #define VPCM_GAMUT_REMAP_C33_C34__VPCM_GAMUT_REMAP_C33_MASK 0x0000FFFFL 2632 #define VPCM_GAMUT_REMAP_C33_C34__VPCM_GAMUT_REMAP_C34_MASK 0xFFFF0000L 2633 //VPCM_BIAS_CR_R 2634 #define VPCM_BIAS_CR_R__VPCM_BIAS_CR_R__SHIFT 0x0 2635 #define VPCM_BIAS_CR_R__VPCM_BIAS_CR_R_MASK 0x0000FFFFL 2636 //VPCM_BIAS_Y_G_CB_B 2637 #define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_Y_G__SHIFT 0x0 2638 #define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_CB_B__SHIFT 0x10 2639 #define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_Y_G_MASK 0x0000FFFFL 2640 #define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_CB_B_MASK 0xFFFF0000L 2641 //VPCM_GAMCOR_CONTROL 2642 #define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE__SHIFT 0x0 2643 #define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_PWL_DISABLE__SHIFT 0x3 2644 #define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE_CURRENT__SHIFT 0x4 2645 #define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 2646 #define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE_MASK 0x00000003L 2647 #define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_PWL_DISABLE_MASK 0x00000008L 2648 #define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE_CURRENT_MASK 0x00000030L 2649 #define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L 2650 //VPCM_GAMCOR_LUT_INDEX 2651 #define VPCM_GAMCOR_LUT_INDEX__VPCM_GAMCOR_LUT_INDEX__SHIFT 0x0 2652 #define VPCM_GAMCOR_LUT_INDEX__VPCM_GAMCOR_LUT_INDEX_MASK 0x000001FFL 2653 //VPCM_GAMCOR_LUT_DATA 2654 #define VPCM_GAMCOR_LUT_DATA__VPCM_GAMCOR_LUT_DATA__SHIFT 0x0 2655 #define VPCM_GAMCOR_LUT_DATA__VPCM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL 2656 //VPCM_GAMCOR_LUT_CONTROL 2657 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 2658 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 2659 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 2660 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 2661 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 2662 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L 2663 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L 2664 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L 2665 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L 2666 #define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L 2667 //VPCM_GAMCOR_RAMA_START_CNTL_B 2668 #define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 2669 #define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 2670 #define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL 2671 #define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L 2672 //VPCM_GAMCOR_RAMA_START_CNTL_G 2673 #define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 2674 #define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 2675 #define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL 2676 #define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L 2677 //VPCM_GAMCOR_RAMA_START_CNTL_R 2678 #define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 2679 #define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 2680 #define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL 2681 #define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L 2682 //VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B 2683 #define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 2684 #define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL 2685 //VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G 2686 #define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 2687 #define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL 2688 //VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R 2689 #define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 2690 #define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL 2691 //VPCM_GAMCOR_RAMA_START_BASE_CNTL_B 2692 #define VPCM_GAMCOR_RAMA_START_BASE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 2693 #define VPCM_GAMCOR_RAMA_START_BASE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL 2694 //VPCM_GAMCOR_RAMA_START_BASE_CNTL_G 2695 #define VPCM_GAMCOR_RAMA_START_BASE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 2696 #define VPCM_GAMCOR_RAMA_START_BASE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL 2697 //VPCM_GAMCOR_RAMA_START_BASE_CNTL_R 2698 #define VPCM_GAMCOR_RAMA_START_BASE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 2699 #define VPCM_GAMCOR_RAMA_START_BASE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL 2700 //VPCM_GAMCOR_RAMA_END_CNTL1_B 2701 #define VPCM_GAMCOR_RAMA_END_CNTL1_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 2702 #define VPCM_GAMCOR_RAMA_END_CNTL1_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL 2703 //VPCM_GAMCOR_RAMA_END_CNTL2_B 2704 #define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 2705 #define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 2706 #define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL 2707 #define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L 2708 //VPCM_GAMCOR_RAMA_END_CNTL1_G 2709 #define VPCM_GAMCOR_RAMA_END_CNTL1_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 2710 #define VPCM_GAMCOR_RAMA_END_CNTL1_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL 2711 //VPCM_GAMCOR_RAMA_END_CNTL2_G 2712 #define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 2713 #define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 2714 #define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL 2715 #define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L 2716 //VPCM_GAMCOR_RAMA_END_CNTL1_R 2717 #define VPCM_GAMCOR_RAMA_END_CNTL1_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 2718 #define VPCM_GAMCOR_RAMA_END_CNTL1_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL 2719 //VPCM_GAMCOR_RAMA_END_CNTL2_R 2720 #define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 2721 #define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 2722 #define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL 2723 #define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L 2724 //VPCM_GAMCOR_RAMA_OFFSET_B 2725 #define VPCM_GAMCOR_RAMA_OFFSET_B__VPCM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 2726 #define VPCM_GAMCOR_RAMA_OFFSET_B__VPCM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL 2727 //VPCM_GAMCOR_RAMA_OFFSET_G 2728 #define VPCM_GAMCOR_RAMA_OFFSET_G__VPCM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 2729 #define VPCM_GAMCOR_RAMA_OFFSET_G__VPCM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL 2730 //VPCM_GAMCOR_RAMA_OFFSET_R 2731 #define VPCM_GAMCOR_RAMA_OFFSET_R__VPCM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 2732 #define VPCM_GAMCOR_RAMA_OFFSET_R__VPCM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL 2733 //VPCM_GAMCOR_RAMA_REGION_0_1 2734 #define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 2735 #define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc 2736 #define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 2737 #define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c 2738 #define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL 2739 #define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L 2740 #define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L 2741 #define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L 2742 //VPCM_GAMCOR_RAMA_REGION_2_3 2743 #define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 2744 #define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc 2745 #define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 2746 #define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c 2747 #define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL 2748 #define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L 2749 #define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L 2750 #define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L 2751 //VPCM_GAMCOR_RAMA_REGION_4_5 2752 #define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 2753 #define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc 2754 #define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 2755 #define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c 2756 #define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL 2757 #define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L 2758 #define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L 2759 #define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L 2760 //VPCM_GAMCOR_RAMA_REGION_6_7 2761 #define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 2762 #define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc 2763 #define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 2764 #define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c 2765 #define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL 2766 #define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L 2767 #define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L 2768 #define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L 2769 //VPCM_GAMCOR_RAMA_REGION_8_9 2770 #define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 2771 #define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc 2772 #define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 2773 #define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c 2774 #define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL 2775 #define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L 2776 #define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L 2777 #define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L 2778 //VPCM_GAMCOR_RAMA_REGION_10_11 2779 #define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 2780 #define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc 2781 #define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 2782 #define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c 2783 #define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL 2784 #define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L 2785 #define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L 2786 #define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L 2787 //VPCM_GAMCOR_RAMA_REGION_12_13 2788 #define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 2789 #define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc 2790 #define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 2791 #define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c 2792 #define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL 2793 #define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L 2794 #define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L 2795 #define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L 2796 //VPCM_GAMCOR_RAMA_REGION_14_15 2797 #define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 2798 #define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc 2799 #define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 2800 #define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c 2801 #define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL 2802 #define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L 2803 #define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L 2804 #define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L 2805 //VPCM_GAMCOR_RAMA_REGION_16_17 2806 #define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 2807 #define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc 2808 #define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 2809 #define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c 2810 #define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL 2811 #define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L 2812 #define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L 2813 #define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L 2814 //VPCM_GAMCOR_RAMA_REGION_18_19 2815 #define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 2816 #define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc 2817 #define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 2818 #define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c 2819 #define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL 2820 #define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L 2821 #define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L 2822 #define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L 2823 //VPCM_GAMCOR_RAMA_REGION_20_21 2824 #define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 2825 #define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc 2826 #define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 2827 #define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c 2828 #define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL 2829 #define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L 2830 #define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L 2831 #define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L 2832 //VPCM_GAMCOR_RAMA_REGION_22_23 2833 #define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 2834 #define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc 2835 #define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 2836 #define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c 2837 #define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL 2838 #define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L 2839 #define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L 2840 #define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L 2841 //VPCM_GAMCOR_RAMA_REGION_24_25 2842 #define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 2843 #define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc 2844 #define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 2845 #define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c 2846 #define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL 2847 #define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L 2848 #define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L 2849 #define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L 2850 //VPCM_GAMCOR_RAMA_REGION_26_27 2851 #define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 2852 #define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc 2853 #define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 2854 #define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c 2855 #define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL 2856 #define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L 2857 #define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L 2858 #define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L 2859 //VPCM_GAMCOR_RAMA_REGION_28_29 2860 #define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 2861 #define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc 2862 #define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 2863 #define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c 2864 #define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL 2865 #define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L 2866 #define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L 2867 #define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L 2868 //VPCM_GAMCOR_RAMA_REGION_30_31 2869 #define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 2870 #define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc 2871 #define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 2872 #define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c 2873 #define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL 2874 #define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L 2875 #define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L 2876 #define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L 2877 //VPCM_GAMCOR_RAMA_REGION_32_33 2878 #define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 2879 #define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc 2880 #define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 2881 #define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c 2882 #define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL 2883 #define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L 2884 #define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L 2885 #define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L 2886 //VPCM_HDR_MULT_COEF 2887 #define VPCM_HDR_MULT_COEF__VPCM_HDR_MULT_COEF__SHIFT 0x0 2888 #define VPCM_HDR_MULT_COEF__VPCM_HDR_MULT_COEF_MASK 0x0007FFFFL 2889 //VPCM_MEM_PWR_CTRL 2890 #define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 2891 #define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 2892 #define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L 2893 #define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L 2894 //VPCM_MEM_PWR_STATUS 2895 #define VPCM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 2896 #define VPCM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L 2897 //VPCM_DEALPHA 2898 #define VPCM_DEALPHA__VPCM_DEALPHA_EN__SHIFT 0x0 2899 #define VPCM_DEALPHA__VPCM_DEALPHA_ABLND__SHIFT 0x1 2900 #define VPCM_DEALPHA__VPCM_DEALPHA_EN_MASK 0x00000001L 2901 #define VPCM_DEALPHA__VPCM_DEALPHA_ABLND_MASK 0x00000002L 2902 //VPCM_COEF_FORMAT 2903 #define VPCM_COEF_FORMAT__VPCM_BIAS_FORMAT__SHIFT 0x0 2904 #define VPCM_COEF_FORMAT__VPCM_POST_CSC_COEF_FORMAT__SHIFT 0x4 2905 #define VPCM_COEF_FORMAT__VPCM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 2906 #define VPCM_COEF_FORMAT__VPCM_BIAS_FORMAT_MASK 0x00000001L 2907 #define VPCM_COEF_FORMAT__VPCM_POST_CSC_COEF_FORMAT_MASK 0x00000010L 2908 #define VPCM_COEF_FORMAT__VPCM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L 2909 //VPCM_TEST_DEBUG_INDEX 2910 #define VPCM_TEST_DEBUG_INDEX__VPCM_TEST_DEBUG_INDEX__SHIFT 0x0 2911 #define VPCM_TEST_DEBUG_INDEX__VPCM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 2912 #define VPCM_TEST_DEBUG_INDEX__VPCM_TEST_DEBUG_INDEX_MASK 0x000000FFL 2913 #define VPCM_TEST_DEBUG_INDEX__VPCM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 2914 //VPCM_TEST_DEBUG_DATA 2915 #define VPCM_TEST_DEBUG_DATA__VPCM_TEST_DEBUG_DATA__SHIFT 0x0 2916 #define VPCM_TEST_DEBUG_DATA__VPCM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL 2917 2918 2919 // addressBlock: vpe_vpep_vpdpp0_dispdec_vpdpp_top_dispdec 2920 //VPDPP_CONTROL 2921 #define VPDPP_CONTROL__VPDPP_CLOCK_ENABLE__SHIFT 0x4 2922 #define VPDPP_CONTROL__VPECLK_G_GATE_DISABLE__SHIFT 0x8 2923 #define VPDPP_CONTROL__VPECLK_G_DYN_GATE_DISABLE__SHIFT 0xa 2924 #define VPDPP_CONTROL__VPECLK_G_VPDSCL_GATE_DISABLE__SHIFT 0xc 2925 #define VPDPP_CONTROL__VPECLK_R_GATE_DISABLE__SHIFT 0xe 2926 #define VPDPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 2927 #define VPDPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 2928 #define VPDPP_CONTROL__VPDPP_FGCG_REP_DIS__SHIFT 0x18 2929 #define VPDPP_CONTROL__VPDPP_TEST_CLK_SEL__SHIFT 0x1c 2930 #define VPDPP_CONTROL__VPDPP_CLOCK_ENABLE_MASK 0x00000010L 2931 #define VPDPP_CONTROL__VPECLK_G_GATE_DISABLE_MASK 0x00000100L 2932 #define VPDPP_CONTROL__VPECLK_G_DYN_GATE_DISABLE_MASK 0x00000400L 2933 #define VPDPP_CONTROL__VPECLK_G_VPDSCL_GATE_DISABLE_MASK 0x00001000L 2934 #define VPDPP_CONTROL__VPECLK_R_GATE_DISABLE_MASK 0x00004000L 2935 #define VPDPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L 2936 #define VPDPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L 2937 #define VPDPP_CONTROL__VPDPP_FGCG_REP_DIS_MASK 0x01000000L 2938 #define VPDPP_CONTROL__VPDPP_TEST_CLK_SEL_MASK 0x70000000L 2939 //VPDPP_SOFT_RESET 2940 #define VPDPP_SOFT_RESET__VPCNVC_SOFT_RESET__SHIFT 0x0 2941 #define VPDPP_SOFT_RESET__VPDSCL_SOFT_RESET__SHIFT 0x4 2942 #define VPDPP_SOFT_RESET__VPCM_SOFT_RESET__SHIFT 0x8 2943 #define VPDPP_SOFT_RESET__VPOBUF_SOFT_RESET__SHIFT 0xc 2944 #define VPDPP_SOFT_RESET__VPCNVC_SOFT_RESET_MASK 0x00000001L 2945 #define VPDPP_SOFT_RESET__VPDSCL_SOFT_RESET_MASK 0x00000010L 2946 #define VPDPP_SOFT_RESET__VPCM_SOFT_RESET_MASK 0x00000100L 2947 #define VPDPP_SOFT_RESET__VPOBUF_SOFT_RESET_MASK 0x00001000L 2948 //VPDPP_CRC_VAL_R_G 2949 #define VPDPP_CRC_VAL_R_G__VPDPP_CRC_R_CR__SHIFT 0x0 2950 #define VPDPP_CRC_VAL_R_G__VPDPP_CRC_G_Y__SHIFT 0x10 2951 #define VPDPP_CRC_VAL_R_G__VPDPP_CRC_R_CR_MASK 0x0000FFFFL 2952 #define VPDPP_CRC_VAL_R_G__VPDPP_CRC_G_Y_MASK 0xFFFF0000L 2953 //VPDPP_CRC_VAL_B_A 2954 #define VPDPP_CRC_VAL_B_A__VPDPP_CRC_B_CB__SHIFT 0x0 2955 #define VPDPP_CRC_VAL_B_A__VPDPP_CRC_ALPHA__SHIFT 0x10 2956 #define VPDPP_CRC_VAL_B_A__VPDPP_CRC_B_CB_MASK 0x0000FFFFL 2957 #define VPDPP_CRC_VAL_B_A__VPDPP_CRC_ALPHA_MASK 0xFFFF0000L 2958 //VPDPP_CRC_CTRL 2959 #define VPDPP_CRC_CTRL__VPDPP_CRC_EN__SHIFT 0x0 2960 #define VPDPP_CRC_CTRL__VPDPP_CRC_CONT_EN__SHIFT 0x1 2961 #define VPDPP_CRC_CTRL__VPDPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 2962 #define VPDPP_CRC_CTRL__VPDPP_CRC_420_COMP_SEL__SHIFT 0x3 2963 #define VPDPP_CRC_CTRL__VPDPP_CRC_SRC_SEL__SHIFT 0x4 2964 #define VPDPP_CRC_CTRL__VPDPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb 2965 #define VPDPP_CRC_CTRL__VPDPP_CRC_MASK__SHIFT 0x10 2966 #define VPDPP_CRC_CTRL__VPDPP_CRC_EN_MASK 0x00000001L 2967 #define VPDPP_CRC_CTRL__VPDPP_CRC_CONT_EN_MASK 0x00000002L 2968 #define VPDPP_CRC_CTRL__VPDPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L 2969 #define VPDPP_CRC_CTRL__VPDPP_CRC_420_COMP_SEL_MASK 0x00000008L 2970 #define VPDPP_CRC_CTRL__VPDPP_CRC_SRC_SEL_MASK 0x00000030L 2971 #define VPDPP_CRC_CTRL__VPDPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L 2972 #define VPDPP_CRC_CTRL__VPDPP_CRC_MASK_MASK 0xFFFF0000L 2973 //VPHOST_READ_CONTROL 2974 #define VPHOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 2975 #define VPHOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL 2976 2977 2978 // addressBlock: vpe_vpep_vpmpc_vpmpcc0_dispdec 2979 //VPMPCC_TOP_SEL 2980 #define VPMPCC_TOP_SEL__VPMPCC_TOP_SEL__SHIFT 0x0 2981 #define VPMPCC_TOP_SEL__VPMPCC_TOP_SEL_MASK 0x0000000FL 2982 //VPMPCC_BOT_SEL 2983 #define VPMPCC_BOT_SEL__VPMPCC_BOT_SEL__SHIFT 0x0 2984 #define VPMPCC_BOT_SEL__VPMPCC_BOT_SEL_MASK 0x0000000FL 2985 //VPMPCC_VPOPP_ID 2986 #define VPMPCC_VPOPP_ID__VPMPCC_VPOPP_ID__SHIFT 0x0 2987 #define VPMPCC_VPOPP_ID__VPMPCC_VPOPP_ID_MASK 0x0000000FL 2988 //VPMPCC_CONTROL 2989 #define VPMPCC_CONTROL__VPMPCC_MODE__SHIFT 0x0 2990 #define VPMPCC_CONTROL__VPMPCC_ALPHA_BLND_MODE__SHIFT 0x4 2991 #define VPMPCC_CONTROL__VPMPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 2992 #define VPMPCC_CONTROL__VPMPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 2993 #define VPMPCC_CONTROL__VPMPCC_BG_BPC__SHIFT 0x8 2994 #define VPMPCC_CONTROL__VPMPCC_BOT_GAIN_MODE__SHIFT 0xb 2995 #define VPMPCC_CONTROL__VPMPCC_GLOBAL_ALPHA__SHIFT 0x10 2996 #define VPMPCC_CONTROL__VPMPCC_GLOBAL_GAIN__SHIFT 0x18 2997 #define VPMPCC_CONTROL__VPMPCC_MODE_MASK 0x00000003L 2998 #define VPMPCC_CONTROL__VPMPCC_ALPHA_BLND_MODE_MASK 0x00000030L 2999 #define VPMPCC_CONTROL__VPMPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L 3000 #define VPMPCC_CONTROL__VPMPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L 3001 #define VPMPCC_CONTROL__VPMPCC_BG_BPC_MASK 0x00000700L 3002 #define VPMPCC_CONTROL__VPMPCC_BOT_GAIN_MODE_MASK 0x00000800L 3003 #define VPMPCC_CONTROL__VPMPCC_GLOBAL_ALPHA_MASK 0x00FF0000L 3004 #define VPMPCC_CONTROL__VPMPCC_GLOBAL_GAIN_MASK 0xFF000000L 3005 //VPMPCC_TOP_GAIN 3006 #define VPMPCC_TOP_GAIN__VPMPCC_TOP_GAIN__SHIFT 0x0 3007 #define VPMPCC_TOP_GAIN__VPMPCC_TOP_GAIN_MASK 0x0007FFFFL 3008 //VPMPCC_BOT_GAIN_INSIDE 3009 #define VPMPCC_BOT_GAIN_INSIDE__VPMPCC_BOT_GAIN_INSIDE__SHIFT 0x0 3010 #define VPMPCC_BOT_GAIN_INSIDE__VPMPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL 3011 //VPMPCC_BOT_GAIN_OUTSIDE 3012 #define VPMPCC_BOT_GAIN_OUTSIDE__VPMPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 3013 #define VPMPCC_BOT_GAIN_OUTSIDE__VPMPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL 3014 //VPMPCC_MOVABLE_CM_LOCATION_CONTROL 3015 #define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x0 3016 #define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x4 3017 #define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001L 3018 #define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010L 3019 //VPMPCC_BG_R_CR 3020 #define VPMPCC_BG_R_CR__VPMPCC_BG_R_CR__SHIFT 0x0 3021 #define VPMPCC_BG_R_CR__VPMPCC_BG_R_CR_MASK 0x00000FFFL 3022 //VPMPCC_BG_G_Y 3023 #define VPMPCC_BG_G_Y__VPMPCC_BG_G_Y__SHIFT 0x0 3024 #define VPMPCC_BG_G_Y__VPMPCC_BG_G_Y_MASK 0x00000FFFL 3025 //VPMPCC_BG_B_CB 3026 #define VPMPCC_BG_B_CB__VPMPCC_BG_B_CB__SHIFT 0x0 3027 #define VPMPCC_BG_B_CB__VPMPCC_BG_B_CB_MASK 0x00000FFFL 3028 //VPMPCC_MEM_PWR_CTRL 3029 #define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 3030 #define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 3031 #define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 3032 #define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 3033 #define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L 3034 #define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L 3035 #define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L 3036 #define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L 3037 //VPMPCC_STATUS 3038 #define VPMPCC_STATUS__VPMPCC_IDLE__SHIFT 0x0 3039 #define VPMPCC_STATUS__VPMPCC_BUSY__SHIFT 0x1 3040 #define VPMPCC_STATUS__VPMPCC_DISABLED__SHIFT 0x2 3041 #define VPMPCC_STATUS__VPMPCC_IDLE_MASK 0x00000001L 3042 #define VPMPCC_STATUS__VPMPCC_BUSY_MASK 0x00000002L 3043 #define VPMPCC_STATUS__VPMPCC_DISABLED_MASK 0x00000004L 3044 3045 3046 // addressBlock: vpe_vpep_vpmpc_vpmpc_cfg_dispdec 3047 //VPMPC_CLOCK_CONTROL 3048 #define VPMPC_CLOCK_CONTROL__VPECLK_R_GATE_DISABLE__SHIFT 0x1 3049 #define VPMPC_CLOCK_CONTROL__VPMPC_TEST_CLK_SEL__SHIFT 0x4 3050 #define VPMPC_CLOCK_CONTROL__VPECLK_R_GATE_DISABLE_MASK 0x00000002L 3051 #define VPMPC_CLOCK_CONTROL__VPMPC_TEST_CLK_SEL_MASK 0x00000030L 3052 //VPMPC_SOFT_RESET 3053 #define VPMPC_SOFT_RESET__VPMPCC0_SOFT_RESET__SHIFT 0x0 3054 #define VPMPC_SOFT_RESET__VPMPC_SFR0_SOFT_RESET__SHIFT 0xa 3055 #define VPMPC_SOFT_RESET__VPMPC_SFT0_SOFT_RESET__SHIFT 0x14 3056 #define VPMPC_SOFT_RESET__VPMPC_SOFT_RESET__SHIFT 0x1f 3057 #define VPMPC_SOFT_RESET__VPMPCC0_SOFT_RESET_MASK 0x00000001L 3058 #define VPMPC_SOFT_RESET__VPMPC_SFR0_SOFT_RESET_MASK 0x00000400L 3059 #define VPMPC_SOFT_RESET__VPMPC_SFT0_SOFT_RESET_MASK 0x00100000L 3060 #define VPMPC_SOFT_RESET__VPMPC_SOFT_RESET_MASK 0x80000000L 3061 //VPMPC_CRC_CTRL 3062 #define VPMPC_CRC_CTRL__VPMPC_CRC_EN__SHIFT 0x0 3063 #define VPMPC_CRC_CTRL__VPMPC_CRC_CONT_EN__SHIFT 0x4 3064 #define VPMPC_CRC_CTRL__VPMPC_CRC_SRC_SEL__SHIFT 0x18 3065 #define VPMPC_CRC_CTRL__VPMPC_CRC_ONE_SHOT_PENDING__SHIFT 0x1c 3066 #define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_ENABLED__SHIFT 0x1e 3067 #define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_LOCK__SHIFT 0x1f 3068 #define VPMPC_CRC_CTRL__VPMPC_CRC_EN_MASK 0x00000001L 3069 #define VPMPC_CRC_CTRL__VPMPC_CRC_CONT_EN_MASK 0x00000010L 3070 #define VPMPC_CRC_CTRL__VPMPC_CRC_SRC_SEL_MASK 0x03000000L 3071 #define VPMPC_CRC_CTRL__VPMPC_CRC_ONE_SHOT_PENDING_MASK 0x10000000L 3072 #define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_ENABLED_MASK 0x40000000L 3073 #define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_LOCK_MASK 0x80000000L 3074 //VPMPC_CRC_SEL_CONTROL 3075 #define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPDPP_SEL__SHIFT 0x0 3076 #define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPOPP_SEL__SHIFT 0x4 3077 #define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_MASK__SHIFT 0x10 3078 #define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPDPP_SEL_MASK 0x0000000FL 3079 #define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPOPP_SEL_MASK 0x000000F0L 3080 #define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_MASK_MASK 0xFFFF0000L 3081 //VPMPC_CRC_RESULT_AR 3082 #define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_A__SHIFT 0x0 3083 #define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_R__SHIFT 0x10 3084 #define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_A_MASK 0x0000FFFFL 3085 #define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_R_MASK 0xFFFF0000L 3086 //VPMPC_CRC_RESULT_GB 3087 #define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_G__SHIFT 0x0 3088 #define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_B__SHIFT 0x10 3089 #define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_G_MASK 0x0000FFFFL 3090 #define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_B_MASK 0xFFFF0000L 3091 //VPMPC_CRC_RESULT_C 3092 #define VPMPC_CRC_RESULT_C__VPMPC_CRC_RESULT_C__SHIFT 0x0 3093 #define VPMPC_CRC_RESULT_C__VPMPC_CRC_RESULT_C_MASK 0x0000FFFFL 3094 //VPMPC_BYPASS_BG_AR 3095 #define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_ALPHA__SHIFT 0x0 3096 #define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_R_CR__SHIFT 0x10 3097 #define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_ALPHA_MASK 0x0000FFFFL 3098 #define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_R_CR_MASK 0xFFFF0000L 3099 //VPMPC_BYPASS_BG_GB 3100 #define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_G_Y__SHIFT 0x0 3101 #define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_B_CB__SHIFT 0x10 3102 #define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_G_Y_MASK 0x0000FFFFL 3103 #define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_B_CB_MASK 0xFFFF0000L 3104 //VPMPC_HOST_READ_CONTROL 3105 #define VPMPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 3106 #define VPMPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL 3107 //VPMPC_PENDING_STATUS_MISC 3108 #define VPMPC_PENDING_STATUS_MISC__VPMPCC0_CONFIG_UPDATE_PENDING__SHIFT 0x8 3109 #define VPMPC_PENDING_STATUS_MISC__VPMPCC0_CONFIG_UPDATE_PENDING_MASK 0x00000100L 3110 3111 3112 // addressBlock: vpe_vpep_vpmpc_vpmpcc_ogam0_dispdec 3113 //VPMPCC_OGAM_CONTROL 3114 #define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE__SHIFT 0x0 3115 #define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_PWL_DISABLE__SHIFT 0x3 3116 #define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE_CURRENT__SHIFT 0x7 3117 #define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 3118 #define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE_MASK 0x00000003L 3119 #define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_PWL_DISABLE_MASK 0x00000008L 3120 #define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE_CURRENT_MASK 0x00000180L 3121 #define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L 3122 //VPMPCC_OGAM_LUT_INDEX 3123 #define VPMPCC_OGAM_LUT_INDEX__VPMPCC_OGAM_LUT_INDEX__SHIFT 0x0 3124 #define VPMPCC_OGAM_LUT_INDEX__VPMPCC_OGAM_LUT_INDEX_MASK 0x000001FFL 3125 //VPMPCC_OGAM_LUT_DATA 3126 #define VPMPCC_OGAM_LUT_DATA__VPMPCC_OGAM_LUT_DATA__SHIFT 0x0 3127 #define VPMPCC_OGAM_LUT_DATA__VPMPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL 3128 //VPMPCC_OGAM_LUT_CONTROL 3129 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 3130 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 3131 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 3132 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 3133 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 3134 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L 3135 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L 3136 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L 3137 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L 3138 #define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L 3139 //VPMPCC_OGAM_RAMA_START_CNTL_B 3140 #define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 3141 #define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 3142 #define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL 3143 #define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L 3144 //VPMPCC_OGAM_RAMA_START_CNTL_G 3145 #define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 3146 #define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 3147 #define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL 3148 #define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L 3149 //VPMPCC_OGAM_RAMA_START_CNTL_R 3150 #define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 3151 #define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 3152 #define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL 3153 #define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L 3154 //VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B 3155 #define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 3156 #define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL 3157 //VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G 3158 #define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 3159 #define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL 3160 //VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R 3161 #define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 3162 #define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL 3163 //VPMPCC_OGAM_RAMA_START_BASE_CNTL_B 3164 #define VPMPCC_OGAM_RAMA_START_BASE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 3165 #define VPMPCC_OGAM_RAMA_START_BASE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL 3166 //VPMPCC_OGAM_RAMA_START_BASE_CNTL_G 3167 #define VPMPCC_OGAM_RAMA_START_BASE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 3168 #define VPMPCC_OGAM_RAMA_START_BASE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL 3169 //VPMPCC_OGAM_RAMA_START_BASE_CNTL_R 3170 #define VPMPCC_OGAM_RAMA_START_BASE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 3171 #define VPMPCC_OGAM_RAMA_START_BASE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL 3172 //VPMPCC_OGAM_RAMA_END_CNTL1_B 3173 #define VPMPCC_OGAM_RAMA_END_CNTL1_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 3174 #define VPMPCC_OGAM_RAMA_END_CNTL1_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL 3175 //VPMPCC_OGAM_RAMA_END_CNTL2_B 3176 #define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 3177 #define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 3178 #define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL 3179 #define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L 3180 //VPMPCC_OGAM_RAMA_END_CNTL1_G 3181 #define VPMPCC_OGAM_RAMA_END_CNTL1_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 3182 #define VPMPCC_OGAM_RAMA_END_CNTL1_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL 3183 //VPMPCC_OGAM_RAMA_END_CNTL2_G 3184 #define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 3185 #define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 3186 #define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL 3187 #define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L 3188 //VPMPCC_OGAM_RAMA_END_CNTL1_R 3189 #define VPMPCC_OGAM_RAMA_END_CNTL1_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 3190 #define VPMPCC_OGAM_RAMA_END_CNTL1_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL 3191 //VPMPCC_OGAM_RAMA_END_CNTL2_R 3192 #define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 3193 #define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 3194 #define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL 3195 #define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L 3196 //VPMPCC_OGAM_RAMA_OFFSET_B 3197 #define VPMPCC_OGAM_RAMA_OFFSET_B__VPMPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 3198 #define VPMPCC_OGAM_RAMA_OFFSET_B__VPMPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL 3199 //VPMPCC_OGAM_RAMA_OFFSET_G 3200 #define VPMPCC_OGAM_RAMA_OFFSET_G__VPMPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 3201 #define VPMPCC_OGAM_RAMA_OFFSET_G__VPMPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL 3202 //VPMPCC_OGAM_RAMA_OFFSET_R 3203 #define VPMPCC_OGAM_RAMA_OFFSET_R__VPMPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 3204 #define VPMPCC_OGAM_RAMA_OFFSET_R__VPMPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL 3205 //VPMPCC_OGAM_RAMA_REGION_0_1 3206 #define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 3207 #define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc 3208 #define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 3209 #define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c 3210 #define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL 3211 #define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L 3212 #define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L 3213 #define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L 3214 //VPMPCC_OGAM_RAMA_REGION_2_3 3215 #define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 3216 #define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc 3217 #define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 3218 #define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c 3219 #define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL 3220 #define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L 3221 #define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L 3222 #define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L 3223 //VPMPCC_OGAM_RAMA_REGION_4_5 3224 #define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 3225 #define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc 3226 #define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 3227 #define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c 3228 #define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL 3229 #define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L 3230 #define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L 3231 #define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L 3232 //VPMPCC_OGAM_RAMA_REGION_6_7 3233 #define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 3234 #define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc 3235 #define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 3236 #define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c 3237 #define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL 3238 #define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L 3239 #define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L 3240 #define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L 3241 //VPMPCC_OGAM_RAMA_REGION_8_9 3242 #define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 3243 #define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc 3244 #define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 3245 #define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c 3246 #define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL 3247 #define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L 3248 #define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L 3249 #define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L 3250 //VPMPCC_OGAM_RAMA_REGION_10_11 3251 #define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 3252 #define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc 3253 #define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 3254 #define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c 3255 #define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL 3256 #define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L 3257 #define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L 3258 #define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L 3259 //VPMPCC_OGAM_RAMA_REGION_12_13 3260 #define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 3261 #define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc 3262 #define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 3263 #define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c 3264 #define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL 3265 #define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L 3266 #define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L 3267 #define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L 3268 //VPMPCC_OGAM_RAMA_REGION_14_15 3269 #define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 3270 #define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc 3271 #define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 3272 #define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c 3273 #define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL 3274 #define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L 3275 #define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L 3276 #define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L 3277 //VPMPCC_OGAM_RAMA_REGION_16_17 3278 #define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 3279 #define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc 3280 #define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 3281 #define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c 3282 #define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL 3283 #define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L 3284 #define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L 3285 #define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L 3286 //VPMPCC_OGAM_RAMA_REGION_18_19 3287 #define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 3288 #define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc 3289 #define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 3290 #define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c 3291 #define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL 3292 #define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L 3293 #define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L 3294 #define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L 3295 //VPMPCC_OGAM_RAMA_REGION_20_21 3296 #define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 3297 #define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc 3298 #define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 3299 #define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c 3300 #define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL 3301 #define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L 3302 #define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L 3303 #define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L 3304 //VPMPCC_OGAM_RAMA_REGION_22_23 3305 #define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 3306 #define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc 3307 #define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 3308 #define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c 3309 #define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL 3310 #define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L 3311 #define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L 3312 #define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L 3313 //VPMPCC_OGAM_RAMA_REGION_24_25 3314 #define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 3315 #define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc 3316 #define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 3317 #define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c 3318 #define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL 3319 #define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L 3320 #define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L 3321 #define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L 3322 //VPMPCC_OGAM_RAMA_REGION_26_27 3323 #define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 3324 #define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc 3325 #define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 3326 #define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c 3327 #define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL 3328 #define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L 3329 #define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L 3330 #define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L 3331 //VPMPCC_OGAM_RAMA_REGION_28_29 3332 #define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 3333 #define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc 3334 #define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 3335 #define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c 3336 #define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL 3337 #define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L 3338 #define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L 3339 #define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L 3340 //VPMPCC_OGAM_RAMA_REGION_30_31 3341 #define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 3342 #define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc 3343 #define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 3344 #define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c 3345 #define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL 3346 #define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L 3347 #define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L 3348 #define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L 3349 //VPMPCC_OGAM_RAMA_REGION_32_33 3350 #define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 3351 #define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc 3352 #define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 3353 #define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c 3354 #define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL 3355 #define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L 3356 #define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L 3357 #define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L 3358 //VPMPCC_GAMUT_REMAP_COEF_FORMAT 3359 #define VPMPCC_GAMUT_REMAP_COEF_FORMAT__VPMPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 3360 #define VPMPCC_GAMUT_REMAP_COEF_FORMAT__VPMPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L 3361 //VPMPCC_GAMUT_REMAP_MODE 3362 #define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE__SHIFT 0x0 3363 #define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 3364 #define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE_MASK 0x00000001L 3365 #define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000080L 3366 //VPMPC_GAMUT_REMAP_C11_C12_A 3367 #define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 3368 #define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 3369 #define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL 3370 #define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L 3371 //VPMPC_GAMUT_REMAP_C13_C14_A 3372 #define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 3373 #define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 3374 #define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL 3375 #define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L 3376 //VPMPC_GAMUT_REMAP_C21_C22_A 3377 #define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 3378 #define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 3379 #define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL 3380 #define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L 3381 //VPMPC_GAMUT_REMAP_C23_C24_A 3382 #define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 3383 #define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 3384 #define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL 3385 #define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L 3386 //VPMPC_GAMUT_REMAP_C31_C32_A 3387 #define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 3388 #define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 3389 #define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL 3390 #define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L 3391 //VPMPC_GAMUT_REMAP_C33_C34_A 3392 #define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 3393 #define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 3394 #define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL 3395 #define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L 3396 3397 3398 // addressBlock: vpe_vpep_vpmpc_vpmpcc_mcm0_dispdec 3399 //VPMPCC_MCM_SHAPER_CONTROL 3400 #define VPMPCC_MCM_SHAPER_CONTROL__VPMPCC_MCM_SHAPER_LUT_MODE__SHIFT 0x0 3401 #define VPMPCC_MCM_SHAPER_CONTROL__VPMPCC_MCM_SHAPER_MODE_CURRENT__SHIFT 0x2 3402 #define VPMPCC_MCM_SHAPER_CONTROL__VPMPCC_MCM_SHAPER_SELECT_CURRENT__SHIFT 0x4 3403 #define VPMPCC_MCM_SHAPER_CONTROL__VPMPCC_MCM_SHAPER_LUT_MODE_MASK 0x00000003L 3404 #define VPMPCC_MCM_SHAPER_CONTROL__VPMPCC_MCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL 3405 #define VPMPCC_MCM_SHAPER_CONTROL__VPMPCC_MCM_SHAPER_SELECT_CURRENT_MASK 0x00000010L 3406 //VPMPCC_MCM_SHAPER_OFFSET_R 3407 #define VPMPCC_MCM_SHAPER_OFFSET_R__VPMPCC_MCM_SHAPER_OFFSET_R__SHIFT 0x0 3408 #define VPMPCC_MCM_SHAPER_OFFSET_R__VPMPCC_MCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL 3409 //VPMPCC_MCM_SHAPER_OFFSET_G 3410 #define VPMPCC_MCM_SHAPER_OFFSET_G__VPMPCC_MCM_SHAPER_OFFSET_G__SHIFT 0x0 3411 #define VPMPCC_MCM_SHAPER_OFFSET_G__VPMPCC_MCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL 3412 //VPMPCC_MCM_SHAPER_OFFSET_B 3413 #define VPMPCC_MCM_SHAPER_OFFSET_B__VPMPCC_MCM_SHAPER_OFFSET_B__SHIFT 0x0 3414 #define VPMPCC_MCM_SHAPER_OFFSET_B__VPMPCC_MCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL 3415 //VPMPCC_MCM_SHAPER_SCALE_R 3416 #define VPMPCC_MCM_SHAPER_SCALE_R__VPMPCC_MCM_SHAPER_SCALE_R__SHIFT 0x0 3417 #define VPMPCC_MCM_SHAPER_SCALE_R__VPMPCC_MCM_SHAPER_SCALE_R_MASK 0x0000FFFFL 3418 //VPMPCC_MCM_SHAPER_SCALE_G_B 3419 #define VPMPCC_MCM_SHAPER_SCALE_G_B__VPMPCC_MCM_SHAPER_SCALE_G__SHIFT 0x0 3420 #define VPMPCC_MCM_SHAPER_SCALE_G_B__VPMPCC_MCM_SHAPER_SCALE_B__SHIFT 0x10 3421 #define VPMPCC_MCM_SHAPER_SCALE_G_B__VPMPCC_MCM_SHAPER_SCALE_G_MASK 0x0000FFFFL 3422 #define VPMPCC_MCM_SHAPER_SCALE_G_B__VPMPCC_MCM_SHAPER_SCALE_B_MASK 0xFFFF0000L 3423 //VPMPCC_MCM_SHAPER_LUT_INDEX 3424 #define VPMPCC_MCM_SHAPER_LUT_INDEX__VPMPCC_MCM_SHAPER_LUT_INDEX__SHIFT 0x0 3425 #define VPMPCC_MCM_SHAPER_LUT_INDEX__VPMPCC_MCM_SHAPER_LUT_INDEX_MASK 0x000000FFL 3426 //VPMPCC_MCM_SHAPER_LUT_DATA 3427 #define VPMPCC_MCM_SHAPER_LUT_DATA__VPMPCC_MCM_SHAPER_LUT_DATA__SHIFT 0x0 3428 #define VPMPCC_MCM_SHAPER_LUT_DATA__VPMPCC_MCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL 3429 //VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 3430 #define VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 3431 #define VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__VPMPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 3432 #define VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L 3433 #define VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__VPMPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L 3434 //VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B 3435 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 3436 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 3437 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL 3438 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L 3439 //VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G 3440 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 3441 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 3442 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL 3443 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L 3444 //VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R 3445 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 3446 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 3447 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL 3448 #define VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L 3449 //VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B 3450 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 3451 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 3452 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL 3453 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L 3454 //VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G 3455 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 3456 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 3457 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL 3458 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L 3459 //VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R 3460 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 3461 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 3462 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL 3463 #define VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L 3464 //VPMPCC_MCM_SHAPER_RAMA_REGION_0_1 3465 #define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 3466 #define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc 3467 #define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 3468 #define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c 3469 #define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL 3470 #define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L 3471 #define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L 3472 #define VPMPCC_MCM_SHAPER_RAMA_REGION_0_1__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L 3473 //VPMPCC_MCM_SHAPER_RAMA_REGION_2_3 3474 #define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 3475 #define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc 3476 #define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 3477 #define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c 3478 #define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL 3479 #define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L 3480 #define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L 3481 #define VPMPCC_MCM_SHAPER_RAMA_REGION_2_3__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L 3482 //VPMPCC_MCM_SHAPER_RAMA_REGION_4_5 3483 #define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 3484 #define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc 3485 #define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 3486 #define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c 3487 #define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL 3488 #define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L 3489 #define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L 3490 #define VPMPCC_MCM_SHAPER_RAMA_REGION_4_5__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L 3491 //VPMPCC_MCM_SHAPER_RAMA_REGION_6_7 3492 #define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 3493 #define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc 3494 #define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 3495 #define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c 3496 #define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL 3497 #define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L 3498 #define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L 3499 #define VPMPCC_MCM_SHAPER_RAMA_REGION_6_7__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L 3500 //VPMPCC_MCM_SHAPER_RAMA_REGION_8_9 3501 #define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 3502 #define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc 3503 #define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 3504 #define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c 3505 #define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL 3506 #define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L 3507 #define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L 3508 #define VPMPCC_MCM_SHAPER_RAMA_REGION_8_9__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L 3509 //VPMPCC_MCM_SHAPER_RAMA_REGION_10_11 3510 #define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 3511 #define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc 3512 #define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 3513 #define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c 3514 #define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL 3515 #define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L 3516 #define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L 3517 #define VPMPCC_MCM_SHAPER_RAMA_REGION_10_11__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L 3518 //VPMPCC_MCM_SHAPER_RAMA_REGION_12_13 3519 #define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 3520 #define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc 3521 #define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 3522 #define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c 3523 #define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL 3524 #define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L 3525 #define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L 3526 #define VPMPCC_MCM_SHAPER_RAMA_REGION_12_13__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L 3527 //VPMPCC_MCM_SHAPER_RAMA_REGION_14_15 3528 #define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 3529 #define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc 3530 #define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 3531 #define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c 3532 #define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL 3533 #define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L 3534 #define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L 3535 #define VPMPCC_MCM_SHAPER_RAMA_REGION_14_15__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L 3536 //VPMPCC_MCM_SHAPER_RAMA_REGION_16_17 3537 #define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 3538 #define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc 3539 #define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 3540 #define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c 3541 #define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL 3542 #define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L 3543 #define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L 3544 #define VPMPCC_MCM_SHAPER_RAMA_REGION_16_17__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L 3545 //VPMPCC_MCM_SHAPER_RAMA_REGION_18_19 3546 #define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 3547 #define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc 3548 #define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 3549 #define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c 3550 #define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL 3551 #define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L 3552 #define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L 3553 #define VPMPCC_MCM_SHAPER_RAMA_REGION_18_19__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L 3554 //VPMPCC_MCM_SHAPER_RAMA_REGION_20_21 3555 #define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 3556 #define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc 3557 #define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 3558 #define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c 3559 #define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL 3560 #define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L 3561 #define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L 3562 #define VPMPCC_MCM_SHAPER_RAMA_REGION_20_21__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L 3563 //VPMPCC_MCM_SHAPER_RAMA_REGION_22_23 3564 #define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 3565 #define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc 3566 #define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 3567 #define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c 3568 #define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL 3569 #define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L 3570 #define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L 3571 #define VPMPCC_MCM_SHAPER_RAMA_REGION_22_23__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L 3572 //VPMPCC_MCM_SHAPER_RAMA_REGION_24_25 3573 #define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 3574 #define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc 3575 #define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 3576 #define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c 3577 #define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL 3578 #define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L 3579 #define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L 3580 #define VPMPCC_MCM_SHAPER_RAMA_REGION_24_25__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L 3581 //VPMPCC_MCM_SHAPER_RAMA_REGION_26_27 3582 #define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 3583 #define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc 3584 #define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 3585 #define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c 3586 #define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL 3587 #define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L 3588 #define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L 3589 #define VPMPCC_MCM_SHAPER_RAMA_REGION_26_27__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L 3590 //VPMPCC_MCM_SHAPER_RAMA_REGION_28_29 3591 #define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 3592 #define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc 3593 #define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 3594 #define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c 3595 #define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL 3596 #define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L 3597 #define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L 3598 #define VPMPCC_MCM_SHAPER_RAMA_REGION_28_29__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L 3599 //VPMPCC_MCM_SHAPER_RAMA_REGION_30_31 3600 #define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 3601 #define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc 3602 #define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 3603 #define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c 3604 #define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL 3605 #define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L 3606 #define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L 3607 #define VPMPCC_MCM_SHAPER_RAMA_REGION_30_31__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L 3608 //VPMPCC_MCM_SHAPER_RAMA_REGION_32_33 3609 #define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 3610 #define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc 3611 #define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 3612 #define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c 3613 #define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL 3614 #define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L 3615 #define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L 3616 #define VPMPCC_MCM_SHAPER_RAMA_REGION_32_33__VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L 3617 //VPMPCC_MCM_3DLUT_MODE 3618 #define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_MODE__SHIFT 0x0 3619 #define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_SIZE__SHIFT 0x4 3620 #define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_MODE_CURRENT__SHIFT 0x8 3621 #define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_SELECT_CURRENT__SHIFT 0xa 3622 #define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_MODE_MASK 0x00000003L 3623 #define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_SIZE_MASK 0x00000010L 3624 #define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_MODE_CURRENT_MASK 0x00000300L 3625 #define VPMPCC_MCM_3DLUT_MODE__VPMPCC_MCM_3DLUT_SELECT_CURRENT_MASK 0x00000400L 3626 //VPMPCC_MCM_3DLUT_INDEX 3627 #define VPMPCC_MCM_3DLUT_INDEX__VPMPCC_MCM_3DLUT_INDEX__SHIFT 0x0 3628 #define VPMPCC_MCM_3DLUT_INDEX__VPMPCC_MCM_3DLUT_INDEX_MASK 0x000007FFL 3629 //VPMPCC_MCM_3DLUT_DATA 3630 #define VPMPCC_MCM_3DLUT_DATA__VPMPCC_MCM_3DLUT_DATA0__SHIFT 0x0 3631 #define VPMPCC_MCM_3DLUT_DATA__VPMPCC_MCM_3DLUT_DATA1__SHIFT 0x10 3632 #define VPMPCC_MCM_3DLUT_DATA__VPMPCC_MCM_3DLUT_DATA0_MASK 0x0000FFFFL 3633 #define VPMPCC_MCM_3DLUT_DATA__VPMPCC_MCM_3DLUT_DATA1_MASK 0xFFFF0000L 3634 //VPMPCC_MCM_3DLUT_DATA_30BIT 3635 #define VPMPCC_MCM_3DLUT_DATA_30BIT__VPMPCC_MCM_3DLUT_DATA_30BIT__SHIFT 0x2 3636 #define VPMPCC_MCM_3DLUT_DATA_30BIT__VPMPCC_MCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL 3637 //VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL 3638 #define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 3639 #define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_RAM_SEL__SHIFT 0x4 3640 #define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_30BIT_EN__SHIFT 0x8 3641 #define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_READ_SEL__SHIFT 0x10 3642 #define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL 3643 #define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_RAM_SEL_MASK 0x00000010L 3644 #define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_30BIT_EN_MASK 0x00000100L 3645 #define VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL__VPMPCC_MCM_3DLUT_READ_SEL_MASK 0x00030000L 3646 //VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR 3647 #define VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR__VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 3648 #define VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR__VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL 3649 //VPMPCC_MCM_3DLUT_OUT_OFFSET_R 3650 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_R__VPMPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 3651 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_R__VPMPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 3652 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_R__VPMPCC_MCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL 3653 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_R__VPMPCC_MCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L 3654 //VPMPCC_MCM_3DLUT_OUT_OFFSET_G 3655 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_G__VPMPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 3656 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_G__VPMPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 3657 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_G__VPMPCC_MCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL 3658 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_G__VPMPCC_MCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L 3659 //VPMPCC_MCM_3DLUT_OUT_OFFSET_B 3660 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_B__VPMPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 3661 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_B__VPMPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 3662 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_B__VPMPCC_MCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL 3663 #define VPMPCC_MCM_3DLUT_OUT_OFFSET_B__VPMPCC_MCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L 3664 //VPMPCC_MCM_1DLUT_CONTROL 3665 #define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE__SHIFT 0x0 3666 #define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x3 3667 #define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x4 3668 #define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x6 3669 #define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE_MASK 0x00000003L 3670 #define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008L 3671 #define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030L 3672 #define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040L 3673 //VPMPCC_MCM_1DLUT_LUT_INDEX 3674 #define VPMPCC_MCM_1DLUT_LUT_INDEX__VPMPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x0 3675 #define VPMPCC_MCM_1DLUT_LUT_INDEX__VPMPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001FFL 3676 //VPMPCC_MCM_1DLUT_LUT_DATA 3677 #define VPMPCC_MCM_1DLUT_LUT_DATA__VPMPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x0 3678 #define VPMPCC_MCM_1DLUT_LUT_DATA__VPMPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003FFFFL 3679 //VPMPCC_MCM_1DLUT_LUT_CONTROL 3680 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x0 3681 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x3 3682 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x5 3683 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x6 3684 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x7 3685 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007L 3686 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018L 3687 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020L 3688 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040L 3689 #define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080L 3690 //VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B 3691 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x0 3692 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 3693 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL 3694 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L 3695 //VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G 3696 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x0 3697 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 3698 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL 3699 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L 3700 //VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R 3701 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x0 3702 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 3703 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL 3704 #define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L 3705 //VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 3706 #define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 3707 #define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL 3708 //VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 3709 #define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 3710 #define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL 3711 //VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 3712 #define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 3713 #define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL 3714 //VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 3715 #define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 3716 #define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL 3717 //VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 3718 #define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 3719 #define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL 3720 //VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 3721 #define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 3722 #define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL 3723 //VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B 3724 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 3725 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL 3726 //VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B 3727 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x0 3728 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 3729 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL 3730 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L 3731 //VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G 3732 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 3733 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL 3734 //VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G 3735 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x0 3736 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 3737 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL 3738 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L 3739 //VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R 3740 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 3741 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL 3742 //VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R 3743 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x0 3744 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 3745 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL 3746 #define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L 3747 //VPMPCC_MCM_1DLUT_RAMA_OFFSET_B 3748 #define VPMPCC_MCM_1DLUT_RAMA_OFFSET_B__VPMPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x0 3749 #define VPMPCC_MCM_1DLUT_RAMA_OFFSET_B__VPMPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007FFFFL 3750 //VPMPCC_MCM_1DLUT_RAMA_OFFSET_G 3751 #define VPMPCC_MCM_1DLUT_RAMA_OFFSET_G__VPMPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x0 3752 #define VPMPCC_MCM_1DLUT_RAMA_OFFSET_G__VPMPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007FFFFL 3753 //VPMPCC_MCM_1DLUT_RAMA_OFFSET_R 3754 #define VPMPCC_MCM_1DLUT_RAMA_OFFSET_R__VPMPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x0 3755 #define VPMPCC_MCM_1DLUT_RAMA_OFFSET_R__VPMPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007FFFFL 3756 //VPMPCC_MCM_1DLUT_RAMA_REGION_0_1 3757 #define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 3758 #define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc 3759 #define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 3760 #define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c 3761 #define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL 3762 #define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L 3763 #define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L 3764 #define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L 3765 //VPMPCC_MCM_1DLUT_RAMA_REGION_2_3 3766 #define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 3767 #define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc 3768 #define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 3769 #define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c 3770 #define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL 3771 #define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L 3772 #define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L 3773 #define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L 3774 //VPMPCC_MCM_1DLUT_RAMA_REGION_4_5 3775 #define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 3776 #define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc 3777 #define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 3778 #define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c 3779 #define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL 3780 #define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L 3781 #define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L 3782 #define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L 3783 //VPMPCC_MCM_1DLUT_RAMA_REGION_6_7 3784 #define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 3785 #define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc 3786 #define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 3787 #define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c 3788 #define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL 3789 #define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L 3790 #define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L 3791 #define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L 3792 //VPMPCC_MCM_1DLUT_RAMA_REGION_8_9 3793 #define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 3794 #define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc 3795 #define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 3796 #define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c 3797 #define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL 3798 #define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L 3799 #define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L 3800 #define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L 3801 //VPMPCC_MCM_1DLUT_RAMA_REGION_10_11 3802 #define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 3803 #define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc 3804 #define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 3805 #define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c 3806 #define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL 3807 #define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L 3808 #define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L 3809 #define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L 3810 //VPMPCC_MCM_1DLUT_RAMA_REGION_12_13 3811 #define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 3812 #define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc 3813 #define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 3814 #define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c 3815 #define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL 3816 #define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L 3817 #define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L 3818 #define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L 3819 //VPMPCC_MCM_1DLUT_RAMA_REGION_14_15 3820 #define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 3821 #define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc 3822 #define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 3823 #define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c 3824 #define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL 3825 #define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L 3826 #define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L 3827 #define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L 3828 //VPMPCC_MCM_1DLUT_RAMA_REGION_16_17 3829 #define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 3830 #define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc 3831 #define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 3832 #define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c 3833 #define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL 3834 #define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L 3835 #define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L 3836 #define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L 3837 //VPMPCC_MCM_1DLUT_RAMA_REGION_18_19 3838 #define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 3839 #define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc 3840 #define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 3841 #define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c 3842 #define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL 3843 #define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L 3844 #define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L 3845 #define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L 3846 //VPMPCC_MCM_1DLUT_RAMA_REGION_20_21 3847 #define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 3848 #define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc 3849 #define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 3850 #define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c 3851 #define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL 3852 #define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L 3853 #define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L 3854 #define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L 3855 //VPMPCC_MCM_1DLUT_RAMA_REGION_22_23 3856 #define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 3857 #define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc 3858 #define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 3859 #define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c 3860 #define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL 3861 #define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L 3862 #define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L 3863 #define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L 3864 //VPMPCC_MCM_1DLUT_RAMA_REGION_24_25 3865 #define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 3866 #define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc 3867 #define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 3868 #define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c 3869 #define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL 3870 #define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L 3871 #define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L 3872 #define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L 3873 //VPMPCC_MCM_1DLUT_RAMA_REGION_26_27 3874 #define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 3875 #define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc 3876 #define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 3877 #define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c 3878 #define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL 3879 #define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L 3880 #define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L 3881 #define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L 3882 //VPMPCC_MCM_1DLUT_RAMA_REGION_28_29 3883 #define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 3884 #define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc 3885 #define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 3886 #define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c 3887 #define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL 3888 #define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L 3889 #define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L 3890 #define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L 3891 //VPMPCC_MCM_1DLUT_RAMA_REGION_30_31 3892 #define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 3893 #define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc 3894 #define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 3895 #define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c 3896 #define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL 3897 #define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L 3898 #define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L 3899 #define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L 3900 //VPMPCC_MCM_1DLUT_RAMA_REGION_32_33 3901 #define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 3902 #define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc 3903 #define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 3904 #define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c 3905 #define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL 3906 #define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L 3907 #define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L 3908 #define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L 3909 //VPMPCC_MCM_MEM_PWR_CTRL 3910 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 3911 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 3912 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 3913 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 3914 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa 3915 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc 3916 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x10 3917 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x12 3918 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x14 3919 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 3920 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a 3921 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x1c 3922 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L 3923 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L 3924 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L 3925 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L 3926 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L 3927 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L 3928 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000L 3929 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000L 3930 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000L 3931 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L 3932 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L 3933 #define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000L 3934 //VPMPCC_MCM_TEST_DEBUG_INDEX 3935 #define VPMPCC_MCM_TEST_DEBUG_INDEX__VPMPCC_MCM_TEST_DEBUG_INDEX__SHIFT 0x0 3936 #define VPMPCC_MCM_TEST_DEBUG_INDEX__VPMPCC_MCM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 3937 #define VPMPCC_MCM_TEST_DEBUG_INDEX__VPMPCC_MCM_TEST_DEBUG_INDEX_MASK 0x000000FFL 3938 #define VPMPCC_MCM_TEST_DEBUG_INDEX__VPMPCC_MCM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 3939 //VPMPCC_MCM_TEST_DEBUG_DATA 3940 #define VPMPCC_MCM_TEST_DEBUG_DATA__VPMPCC_MCM_TEST_DEBUG_DATA__SHIFT 0x0 3941 #define VPMPCC_MCM_TEST_DEBUG_DATA__VPMPCC_MCM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL 3942 3943 3944 // addressBlock: vpe_vpep_vpmpc_vpmpc_ocsc_dispdec 3945 //VPMPC_OUT0_MUX 3946 #define VPMPC_OUT0_MUX__VPMPC_OUT_MUX__SHIFT 0x0 3947 #define VPMPC_OUT0_MUX__VPMPC_OUT_MUX_MASK 0x0000000FL 3948 //VPMPC_OUT0_FLOAT_CONTROL 3949 #define VPMPC_OUT0_FLOAT_CONTROL__VPMPC_OUT_FLOAT_EN__SHIFT 0x0 3950 #define VPMPC_OUT0_FLOAT_CONTROL__VPMPC_OUT_FLOAT_EN_MASK 0x00000001L 3951 //VPMPC_OUT0_DENORM_CONTROL 3952 #define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 3953 #define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc 3954 #define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_MODE__SHIFT 0x18 3955 #define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL 3956 #define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L 3957 #define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_MODE_MASK 0x07000000L 3958 //VPMPC_OUT0_DENORM_CLAMP_G_Y 3959 #define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 3960 #define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc 3961 #define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL 3962 #define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L 3963 //VPMPC_OUT0_DENORM_CLAMP_B_CB 3964 #define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 3965 #define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc 3966 #define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL 3967 #define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L 3968 //VPMPC_OUT_CSC_COEF_FORMAT 3969 #define VPMPC_OUT_CSC_COEF_FORMAT__VPMPC_OCSC0_COEF_FORMAT__SHIFT 0x0 3970 #define VPMPC_OUT_CSC_COEF_FORMAT__VPMPC_OCSC0_COEF_FORMAT_MASK 0x00000001L 3971 //VPMPC_OUT0_CSC_MODE 3972 #define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE__SHIFT 0x0 3973 #define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE_CURRENT__SHIFT 0x7 3974 #define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE_MASK 0x00000001L 3975 #define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE_CURRENT_MASK 0x00000080L 3976 //VPMPC_OUT0_CSC_C11_C12_A 3977 #define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C11_A__SHIFT 0x0 3978 #define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C12_A__SHIFT 0x10 3979 #define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C11_A_MASK 0x0000FFFFL 3980 #define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C12_A_MASK 0xFFFF0000L 3981 //VPMPC_OUT0_CSC_C13_C14_A 3982 #define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C13_A__SHIFT 0x0 3983 #define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C14_A__SHIFT 0x10 3984 #define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C13_A_MASK 0x0000FFFFL 3985 #define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C14_A_MASK 0xFFFF0000L 3986 //VPMPC_OUT0_CSC_C21_C22_A 3987 #define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C21_A__SHIFT 0x0 3988 #define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C22_A__SHIFT 0x10 3989 #define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C21_A_MASK 0x0000FFFFL 3990 #define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C22_A_MASK 0xFFFF0000L 3991 //VPMPC_OUT0_CSC_C23_C24_A 3992 #define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C23_A__SHIFT 0x0 3993 #define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C24_A__SHIFT 0x10 3994 #define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C23_A_MASK 0x0000FFFFL 3995 #define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C24_A_MASK 0xFFFF0000L 3996 //VPMPC_OUT0_CSC_C31_C32_A 3997 #define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C31_A__SHIFT 0x0 3998 #define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C32_A__SHIFT 0x10 3999 #define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C31_A_MASK 0x0000FFFFL 4000 #define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C32_A_MASK 0xFFFF0000L 4001 //VPMPC_OUT0_CSC_C33_C34_A 4002 #define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C33_A__SHIFT 0x0 4003 #define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C34_A__SHIFT 0x10 4004 #define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C33_A_MASK 0x0000FFFFL 4005 #define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C34_A_MASK 0xFFFF0000L 4006 4007 4008 // addressBlock: vpe_vpep_vpopp_vpfmt0_dispdec 4009 //VPFMT_CLAMP_COMPONENT_R 4010 #define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_LOWER_R__SHIFT 0x0 4011 #define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_UPPER_R__SHIFT 0x10 4012 #define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_LOWER_R_MASK 0x0000FFFFL 4013 #define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_UPPER_R_MASK 0xFFFF0000L 4014 //VPFMT_CLAMP_COMPONENT_G 4015 #define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_LOWER_G__SHIFT 0x0 4016 #define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_UPPER_G__SHIFT 0x10 4017 #define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_LOWER_G_MASK 0x0000FFFFL 4018 #define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_UPPER_G_MASK 0xFFFF0000L 4019 //VPFMT_CLAMP_COMPONENT_B 4020 #define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_LOWER_B__SHIFT 0x0 4021 #define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_UPPER_B__SHIFT 0x10 4022 #define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_LOWER_B_MASK 0x0000FFFFL 4023 #define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_UPPER_B_MASK 0xFFFF0000L 4024 //VPFMT_DYNAMIC_EXP_CNTL 4025 #define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_EN__SHIFT 0x0 4026 #define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_MODE__SHIFT 0x4 4027 #define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_EN_MASK 0x00000001L 4028 #define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_MODE_MASK 0x00000010L 4029 //VPFMT_CONTROL 4030 #define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 4031 #define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc 4032 #define VPFMT_CONTROL__VPFMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 4033 #define VPFMT_CONTROL__VPFMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 4034 #define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L 4035 #define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L 4036 #define VPFMT_CONTROL__VPFMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L 4037 #define VPFMT_CONTROL__VPFMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L 4038 //VPFMT_BIT_DEPTH_CONTROL 4039 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_EN__SHIFT 0x0 4040 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_MODE__SHIFT 0x1 4041 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_DEPTH__SHIFT 0x4 4042 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_EN__SHIFT 0x8 4043 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_MODE__SHIFT 0x9 4044 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb 4045 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_FRAME_RANDOM_ENABLE__SHIFT 0xd 4046 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_RGB_RANDOM_ENABLE__SHIFT 0xe 4047 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf 4048 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_EN_MASK 0x00000001L 4049 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_MODE_MASK 0x00000002L 4050 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_DEPTH_MASK 0x00000030L 4051 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_EN_MASK 0x00000100L 4052 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_MODE_MASK 0x00000600L 4053 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L 4054 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L 4055 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_RGB_RANDOM_ENABLE_MASK 0x00004000L 4056 #define VPFMT_BIT_DEPTH_CONTROL__VPFMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L 4057 //VPFMT_DITHER_RAND_R_SEED 4058 #define VPFMT_DITHER_RAND_R_SEED__VPFMT_RAND_R_SEED__SHIFT 0x0 4059 #define VPFMT_DITHER_RAND_R_SEED__VPFMT_OFFSET_R_CR__SHIFT 0x10 4060 #define VPFMT_DITHER_RAND_R_SEED__VPFMT_RAND_R_SEED_MASK 0x000000FFL 4061 #define VPFMT_DITHER_RAND_R_SEED__VPFMT_OFFSET_R_CR_MASK 0xFFFF0000L 4062 //VPFMT_DITHER_RAND_G_SEED 4063 #define VPFMT_DITHER_RAND_G_SEED__VPFMT_RAND_G_SEED__SHIFT 0x0 4064 #define VPFMT_DITHER_RAND_G_SEED__VPFMT_OFFSET_G_Y__SHIFT 0x10 4065 #define VPFMT_DITHER_RAND_G_SEED__VPFMT_RAND_G_SEED_MASK 0x000000FFL 4066 #define VPFMT_DITHER_RAND_G_SEED__VPFMT_OFFSET_G_Y_MASK 0xFFFF0000L 4067 //VPFMT_DITHER_RAND_B_SEED 4068 #define VPFMT_DITHER_RAND_B_SEED__VPFMT_RAND_B_SEED__SHIFT 0x0 4069 #define VPFMT_DITHER_RAND_B_SEED__VPFMT_OFFSET_B_CB__SHIFT 0x10 4070 #define VPFMT_DITHER_RAND_B_SEED__VPFMT_RAND_B_SEED_MASK 0x000000FFL 4071 #define VPFMT_DITHER_RAND_B_SEED__VPFMT_OFFSET_B_CB_MASK 0xFFFF0000L 4072 //VPFMT_CLAMP_CNTL 4073 #define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_DATA_EN__SHIFT 0x0 4074 #define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 4075 #define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_DATA_EN_MASK 0x00000001L 4076 #define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L 4077 4078 4079 // addressBlock: vpe_vpep_vpopp_vpopp_pipe0_dispdec 4080 //VPOPP_PIPE_CONTROL 4081 #define VPOPP_PIPE_CONTROL__VPOPP_PIPE_CLOCK_ON__SHIFT 0x1 4082 #define VPOPP_PIPE_CONTROL__VPOPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 4083 #define VPOPP_PIPE_CONTROL__VPOPP_PIPE_ALPHA__SHIFT 0x10 4084 #define VPOPP_PIPE_CONTROL__VPOPP_PIPE_CLOCK_ON_MASK 0x00000002L 4085 #define VPOPP_PIPE_CONTROL__VPOPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L 4086 #define VPOPP_PIPE_CONTROL__VPOPP_PIPE_ALPHA_MASK 0xFFFF0000L 4087 4088 4089 // addressBlock: vpe_vpep_vpopp_vpopp_pipe_crc0_dispdec 4090 //VPOPP_PIPE_CRC_CONTROL 4091 #define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_EN__SHIFT 0x0 4092 #define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_CONT_EN__SHIFT 0x4 4093 #define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 4094 #define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c 4095 #define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_EN_MASK 0x00000001L 4096 #define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_CONT_EN_MASK 0x00000010L 4097 #define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L 4098 #define VPOPP_PIPE_CRC_CONTROL__VPOPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L 4099 //VPOPP_PIPE_CRC_MASK 4100 #define VPOPP_PIPE_CRC_MASK__VPOPP_PIPE_CRC_MASK__SHIFT 0x0 4101 #define VPOPP_PIPE_CRC_MASK__VPOPP_PIPE_CRC_MASK_MASK 0x0000FFFFL 4102 //VPOPP_PIPE_CRC_RESULT0 4103 #define VPOPP_PIPE_CRC_RESULT0__VPOPP_PIPE_CRC_RESULT_A__SHIFT 0x0 4104 #define VPOPP_PIPE_CRC_RESULT0__VPOPP_PIPE_CRC_RESULT_R__SHIFT 0x10 4105 #define VPOPP_PIPE_CRC_RESULT0__VPOPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL 4106 #define VPOPP_PIPE_CRC_RESULT0__VPOPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L 4107 //VPOPP_PIPE_CRC_RESULT1 4108 #define VPOPP_PIPE_CRC_RESULT1__VPOPP_PIPE_CRC_RESULT_G__SHIFT 0x0 4109 #define VPOPP_PIPE_CRC_RESULT1__VPOPP_PIPE_CRC_RESULT_B__SHIFT 0x10 4110 #define VPOPP_PIPE_CRC_RESULT1__VPOPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL 4111 #define VPOPP_PIPE_CRC_RESULT1__VPOPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L 4112 //VPOPP_PIPE_CRC_RESULT2 4113 #define VPOPP_PIPE_CRC_RESULT2__VPOPP_PIPE_CRC_RESULT_C__SHIFT 0x0 4114 #define VPOPP_PIPE_CRC_RESULT2__VPOPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL 4115 4116 4117 // addressBlock: vpe_vpep_vpopp_vpopp_top_dispdec 4118 //VPOPP_TOP_CLK_CONTROL 4119 #define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_R_GATE_DIS__SHIFT 0x0 4120 #define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_G_GATE_DIS__SHIFT 0x1 4121 #define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_R_GATE_DIS_MASK 0x00000001L 4122 #define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_G_GATE_DIS_MASK 0x00000002L 4123 4124 4125 // addressBlock: vpe_vpep_vpcdc_cdc_dispdec 4126 //VPEP_MGCG_CNTL 4127 #define VPEP_MGCG_CNTL__VPDPP0_CLK_GATE_DIS__SHIFT 0x0 4128 #define VPEP_MGCG_CNTL__VPMPC_CLK_GATE_DIS__SHIFT 0xc 4129 #define VPEP_MGCG_CNTL__VPOPP_CLK_GATE_DIS__SHIFT 0x12 4130 #define VPEP_MGCG_CNTL__VPCDC_SOCCLK_G_GATE_DIS__SHIFT 0x14 4131 #define VPEP_MGCG_CNTL__VPCDC_SOCCLK_R_GATE_DIS__SHIFT 0x15 4132 #define VPEP_MGCG_CNTL__VPCDC_VPECLK_G_GATE_DIS__SHIFT 0x16 4133 #define VPEP_MGCG_CNTL__VPCDC_VPECLK_R_GATE_DIS__SHIFT 0x17 4134 #define VPEP_MGCG_CNTL__VPDPP0_CLK_GATE_DIS_MASK 0x00000007L 4135 #define VPEP_MGCG_CNTL__VPMPC_CLK_GATE_DIS_MASK 0x00003000L 4136 #define VPEP_MGCG_CNTL__VPOPP_CLK_GATE_DIS_MASK 0x000C0000L 4137 #define VPEP_MGCG_CNTL__VPCDC_SOCCLK_G_GATE_DIS_MASK 0x00100000L 4138 #define VPEP_MGCG_CNTL__VPCDC_SOCCLK_R_GATE_DIS_MASK 0x00200000L 4139 #define VPEP_MGCG_CNTL__VPCDC_VPECLK_G_GATE_DIS_MASK 0x00400000L 4140 #define VPEP_MGCG_CNTL__VPCDC_VPECLK_R_GATE_DIS_MASK 0x00800000L 4141 //VPCDC_SOFT_RESET 4142 #define VPCDC_SOFT_RESET__VPCDC_SOCCLK_SOFT_RESET__SHIFT 0x0 4143 #define VPCDC_SOFT_RESET__VPCDC_VPECLK_SOFT_RESET__SHIFT 0x1 4144 #define VPCDC_SOFT_RESET__VPCDC_SOCCLK_SOFT_RESET_MASK 0x00000001L 4145 #define VPCDC_SOFT_RESET__VPCDC_VPECLK_SOFT_RESET_MASK 0x00000002L 4146 //VPCDC_FE0_SURFACE_CONFIG 4147 #define VPCDC_FE0_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_FE0__SHIFT 0x0 4148 #define VPCDC_FE0_SURFACE_CONFIG__ROTATION_ANGLE_FE0__SHIFT 0x8 4149 #define VPCDC_FE0_SURFACE_CONFIG__H_MIRROR_EN_FE0__SHIFT 0xa 4150 #define VPCDC_FE0_SURFACE_CONFIG__PIX_SURFACE_LINEAR_FE0__SHIFT 0xb 4151 #define VPCDC_FE0_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_FE0_MASK 0x0000007FL 4152 #define VPCDC_FE0_SURFACE_CONFIG__ROTATION_ANGLE_FE0_MASK 0x00000300L 4153 #define VPCDC_FE0_SURFACE_CONFIG__H_MIRROR_EN_FE0_MASK 0x00000400L 4154 #define VPCDC_FE0_SURFACE_CONFIG__PIX_SURFACE_LINEAR_FE0_MASK 0x00000800L 4155 //VPCDC_FE0_CROSSBAR_CONFIG 4156 #define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_ALPHA_FE0__SHIFT 0x0 4157 #define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_Y_G_FE0__SHIFT 0x2 4158 #define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CB_B_FE0__SHIFT 0x4 4159 #define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CR_R_FE0__SHIFT 0x6 4160 #define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_ALPHA_FE0_MASK 0x00000003L 4161 #define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_Y_G_FE0_MASK 0x0000000CL 4162 #define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CB_B_FE0_MASK 0x00000030L 4163 #define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CR_R_FE0_MASK 0x000000C0L 4164 //VPCDC_FE0_VIEWPORT_START_CONFIG 4165 #define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_X_START_FE0__SHIFT 0x0 4166 #define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_Y_START_FE0__SHIFT 0x10 4167 #define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_X_START_FE0_MASK 0x00003FFFL 4168 #define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_Y_START_FE0_MASK 0x3FFF0000L 4169 //VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG 4170 #define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_WIDTH_FE0__SHIFT 0x0 4171 #define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_HEIGHT_FE0__SHIFT 0x10 4172 #define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_WIDTH_FE0_MASK 0x00003FFFL 4173 #define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_HEIGHT_FE0_MASK 0x3FFF0000L 4174 //VPCDC_FE0_VIEWPORT_START_C_CONFIG 4175 #define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_X_START_C_FE0__SHIFT 0x0 4176 #define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_Y_START_C_FE0__SHIFT 0x10 4177 #define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_X_START_C_FE0_MASK 0x00003FFFL 4178 #define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_Y_START_C_FE0_MASK 0x3FFF0000L 4179 //VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG 4180 #define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_WIDTH_C_FE0__SHIFT 0x0 4181 #define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_HEIGHT_C_FE0__SHIFT 0x10 4182 #define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_WIDTH_C_FE0_MASK 0x00003FFFL 4183 #define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_HEIGHT_C_FE0_MASK 0x3FFF0000L 4184 //VPCDC_BE0_P2B_CONFIG 4185 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL0__SHIFT 0x0 4186 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL1__SHIFT 0x2 4187 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL2__SHIFT 0x4 4188 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL3__SHIFT 0x6 4189 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_FORMAT_SEL__SHIFT 0x8 4190 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL0_MASK 0x00000003L 4191 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL1_MASK 0x0000000CL 4192 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL2_MASK 0x00000030L 4193 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL3_MASK 0x000000C0L 4194 #define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_FORMAT_SEL_MASK 0x00000300L 4195 //VPCDC_BE0_GLOBAL_SYNC_CONFIG 4196 #define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_OFFSET__SHIFT 0x0 4197 #define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_WIDTH__SHIFT 0xa 4198 #define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VREADY_OFFSET__SHIFT 0x14 4199 #define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_OFFSET_MASK 0x000003FFL 4200 #define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_WIDTH_MASK 0x000FFC00L 4201 #define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VREADY_OFFSET_MASK 0x3FF00000L 4202 //VPCDC_GLOBAL_SYNC_TRIGGER 4203 #define VPCDC_GLOBAL_SYNC_TRIGGER__VPBE_GS_TRIG__SHIFT 0x0 4204 #define VPCDC_GLOBAL_SYNC_TRIGGER__VPBE_GS_TRIG_MASK 0x00000003L 4205 //VPCDC_VREADY_STATUS 4206 #define VPCDC_VREADY_STATUS__VPFE_VR_STATUS__SHIFT 0x0 4207 #define VPCDC_VREADY_STATUS__VPFE_VR_STATUS_MASK 0x00000003L 4208 //VPEP_MEM_GLOBAL_PWR_REQ_CNTL 4209 #define VPEP_MEM_GLOBAL_PWR_REQ_CNTL__MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 4210 #define VPEP_MEM_GLOBAL_PWR_REQ_CNTL__MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001L 4211 //VPFE_MEM_PWR_CNTL 4212 #define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_FORCE__SHIFT 0x0 4213 #define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_MODE__SHIFT 0x2 4214 #define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_STATE__SHIFT 0x4 4215 #define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_DIS__SHIFT 0x6 4216 #define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_FORCE_MASK 0x00000003L 4217 #define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_MODE_MASK 0x0000000CL 4218 #define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_STATE_MASK 0x00000030L 4219 #define VPFE_MEM_PWR_CNTL__VPFE0_MEM_PWR_DIS_MASK 0x00000040L 4220 //VPBE_MEM_PWR_CNTL 4221 #define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_FORCE__SHIFT 0x0 4222 #define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_MODE__SHIFT 0x2 4223 #define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_STATE__SHIFT 0x4 4224 #define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_DIS__SHIFT 0x6 4225 #define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_FORCE_MASK 0x00000003L 4226 #define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_MODE_MASK 0x0000000CL 4227 #define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_STATE_MASK 0x00000030L 4228 #define VPBE_MEM_PWR_CNTL__VPBE0_MEM_PWR_DIS_MASK 0x00000040L 4229 //VPEP_RBBMIF_TIMEOUT 4230 #define VPEP_RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 4231 #define VPEP_RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_HOLD__SHIFT 0x14 4232 #define VPEP_RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0x000FFFFFL 4233 #define VPEP_RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_HOLD_MASK 0xFFF00000L 4234 //VPEP_RBBMIF_STATUS 4235 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0 4236 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c 4237 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d 4238 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e 4239 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f 4240 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0x0000000FL 4241 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000L 4242 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000L 4243 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000L 4244 #define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000L 4245 //VPEP_RBBMIF_TIMEOUT_DIS 4246 #define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0 4247 #define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1 4248 #define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2 4249 #define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3 4250 #define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x00000001L 4251 #define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x00000002L 4252 #define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x00000004L 4253 #define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x00000008L 4254 4255 4256 // addressBlock: vpe_vpep_vpcdc_vpcdc_dcperfmon_dc_perfmon_dispdec 4257 //PERFCOUNTER_CNTL 4258 #define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 4259 #define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 4260 #define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc 4261 #define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf 4262 #define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 4263 #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 4264 #define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 4265 #define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 4266 #define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 4267 #define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a 4268 #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d 4269 #define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL 4270 #define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L 4271 #define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L 4272 #define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L 4273 #define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L 4274 #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L 4275 #define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L 4276 #define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L 4277 #define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L 4278 #define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L 4279 #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L 4280 //PERFCOUNTER_CNTL2 4281 #define PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 4282 #define PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 4283 #define PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 4284 #define PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 4285 #define PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d 4286 #define PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L 4287 #define PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L 4288 #define PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L 4289 #define PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L 4290 #define PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L 4291 //PERFCOUNTER_STATE 4292 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 4293 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 4294 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 4295 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 4296 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 4297 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa 4298 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc 4299 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe 4300 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 4301 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 4302 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 4303 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 4304 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 4305 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a 4306 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c 4307 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e 4308 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L 4309 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L 4310 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L 4311 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L 4312 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L 4313 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L 4314 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L 4315 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L 4316 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L 4317 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L 4318 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L 4319 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L 4320 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L 4321 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L 4322 #define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L 4323 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L 4324 //PERFMON_CNTL 4325 #define PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 4326 #define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 4327 #define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c 4328 #define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d 4329 #define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e 4330 #define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f 4331 #define PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L 4332 #define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L 4333 #define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L 4334 #define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L 4335 #define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L 4336 #define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L 4337 //PERFMON_CNTL2 4338 #define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 4339 #define PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 4340 #define PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 4341 #define PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa 4342 #define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L 4343 #define PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L 4344 #define PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL 4345 #define PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L 4346 //PERFMON_CVALUE_INT_MISC 4347 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 4348 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 4349 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 4350 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 4351 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 4352 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 4353 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 4354 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 4355 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 4356 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 4357 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa 4358 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb 4359 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc 4360 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd 4361 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe 4362 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf 4363 #define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 4364 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L 4365 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L 4366 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L 4367 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L 4368 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L 4369 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L 4370 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L 4371 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L 4372 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L 4373 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L 4374 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L 4375 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L 4376 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L 4377 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L 4378 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L 4379 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L 4380 #define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L 4381 //PERFMON_CVALUE_LOW 4382 #define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 4383 #define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL 4384 //PERFMON_HI 4385 #define PERFMON_HI__PERFMON_HI__SHIFT 0x0 4386 #define PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d 4387 #define PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL 4388 #define PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L 4389 //PERFMON_LOW 4390 #define PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 4391 #define PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL 4392 4393 #endif 4394