1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_VIDEO_CC_H 7 #define _DT_BINDINGS_CLK_QCOM_SA8775P_VIDEO_CC_H 8 9 /* VIDEO_CC clocks */ 10 #define VIDEO_CC_AHB_CLK 0 11 #define VIDEO_CC_AHB_CLK_SRC 1 12 #define VIDEO_CC_MVS0_CLK 2 13 #define VIDEO_CC_MVS0_CLK_SRC 3 14 #define VIDEO_CC_MVS0_DIV_CLK_SRC 4 15 #define VIDEO_CC_MVS0C_CLK 5 16 #define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 6 17 #define VIDEO_CC_MVS1_CLK 7 18 #define VIDEO_CC_MVS1_CLK_SRC 8 19 #define VIDEO_CC_MVS1_DIV_CLK_SRC 9 20 #define VIDEO_CC_MVS1C_CLK 10 21 #define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 11 22 #define VIDEO_CC_PLL_LOCK_MONITOR_CLK 12 23 #define VIDEO_CC_SLEEP_CLK 13 24 #define VIDEO_CC_SLEEP_CLK_SRC 14 25 #define VIDEO_CC_SM_DIV_CLK_SRC 15 26 #define VIDEO_CC_SM_OBS_CLK 16 27 #define VIDEO_CC_XO_CLK 17 28 #define VIDEO_CC_XO_CLK_SRC 18 29 #define VIDEO_PLL0 19 30 #define VIDEO_PLL1 20 31 32 /* VIDEO_CC power domains */ 33 #define VIDEO_CC_MVS0C_GDSC 0 34 #define VIDEO_CC_MVS0_GDSC 1 35 #define VIDEO_CC_MVS1C_GDSC 2 36 #define VIDEO_CC_MVS1_GDSC 3 37 38 /* VIDEO_CC resets */ 39 #define VIDEO_CC_INTERFACE_BCR 0 40 #define VIDEO_CC_MVS0_BCR 1 41 #define VIDEO_CC_MVS0C_CLK_ARES 2 42 #define VIDEO_CC_MVS0C_BCR 3 43 #define VIDEO_CC_MVS1_BCR 4 44 #define VIDEO_CC_MVS1C_CLK_ARES 5 45 #define VIDEO_CC_MVS1C_BCR 6 46 47 #endif 48