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Searched refs:VID (Results 1 – 25 of 43) sorted by relevance

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/linux/drivers/net/ethernet/mellanox/mlxsw/
H A Dspectrum_acl_flex_keys.c14 MLXSW_AFK_ELEMENT_INST_U32(VID, 0x08, 0, 12),
22 MLXSW_AFK_ELEMENT_INST_U32(VID, 0x08, 0, 12),
55 MLXSW_AFK_ELEMENT_INST_U32(VID, 0x00, 0, 12),
144 MLXSW_AFK_ELEMENT_INST_U32(VID, 0x04, 16, 12),
150 MLXSW_AFK_ELEMENT_INST_U32(VID, 0x04, 16, 12),
155 MLXSW_AFK_ELEMENT_INST_U32(VID, 0x04, 16, 12),
323 MLXSW_AFK_ELEMENT_INST_U32(VID, 0x04, 18, 12),
/linux/Documentation/hwmon/
H A Dmp2856.rst30 - Can configured VOUT readout in direct or VID format and allows
31 setting of different formats on rails 1 and 2. For VID the following
46 Device supports VID and direct formats for reading output voltage.
47 The below VID modes are supported: AMD SVI3.
H A Dadm1025.rst46 input, or as the a fifth digital entry for the VID reading (bit 4). It's
52 properly, you'll have a wrong +12V reading or a wrong VID reading. The way
59 only in that it has "open-drain VID inputs while the ADM1025 has on-chip
60 100k pull-ups on the VID inputs". It doesn't make any difference for us.
H A Dmp2975.rst30 - Can configured VOUT readout in direct or VID format and allows
31 setting of different formats on rails 1 and 2. For VID the following
47 Device supports VID and direct formats for reading output voltage.
48 The below VID modes are supported: VR12, VR13, IMVP9.
H A Dw83627hf.rst57 VID reading. However the two chips have the identical 128 pin package. So,
58 it is possible or even likely for a w83627thf to have the VID signals routed
60 the w83627thf driver interprets these as VID. If the VID on your board
62 doesn't help, you may just ignore the bogus VID reading with no harm done.
H A Dsmsc47m192.rst36 as well as CPU voltage VID input.
53 a +12V voltage measurement or a 5 bit CPU VID, but not both.
54 The default setting is to use the pin as 12V input, and use only 4 bit VID.
112 vrm CPU VID standard used for decoding CPU voltage
H A Dlm78.rst38 the LM78 and LM78-J are exactly identical. The LM79 has one more VID line,
43 seven voltage sensors, VID lines, alarms, and some miscellaneous stuff.
67 The VID lines encode the core voltage value: the voltage level your processor
H A Dasb100.rst29 sensors, four temperature sensors, VID lines and alarms. In addition to
42 The VID lines encode the core voltage value: the voltage level your
H A Dadm1026.rst98 The datasheet shows an example application with VID signals attached to
99 GPIO lines. Unfortunately, the chip may not be connected to the VID lines
101 get a VID voltage.
H A Dw83793.rst44 sets of 6-pin CPU VID input.
104 * VID and VRM
H A Dadt7475.rst51 measurement inputs and VID support. The ADT7490 also has additional
89 * VID support
H A Dlm93.rst40 VID" from the datasheet. It greatly simplifies the interface to allow
46 A "0" configures the VID pins for V(ih) = 2.1V min, V(il) = 0.8V max.
47 A "1" configures the VID pins for V(ih) = 0.8V min, V(il) = 0.4V max.
49 I.e. this parameter controls the VID pin input thresholds; if your VID
H A Dmp2888.rst26 - PWM-VID Interface
H A Dxdpe12284.rst39 Device supports VID format for reading output voltage. The below modes are
H A Dadm9240.rst165 VID Monitor
167 The chip has five inputs to read the 5-bit VID and reports the mV value
H A Df71805f.rst55 6 VID inputs. The VID inputs are not yet supported by this driver.
H A Dpc87360.rst167 When available, VID inputs are used to provide the nominal CPU Core voltage.
169 The chipsets can handle two sets of VID inputs (on dual-CPU systems), but
/linux/drivers/gpu/drm/sti/
H A DNOTES11 - The video plug (VID) connects to the HQVDP output.
28 Vid >--+ HQVDP +--+VID Aux +---+ | :===========:
42 buffers) and to HQVDP+VID (video buffers)
56 +-> | HQVDP | |VID Aux |<+ | | | :===========: |
/linux/Documentation/usb/
H A Dlinux-cdc-acm.inf82 ; When developing your USB device, the VID and PID used in the PC side
84 ; Modify the below line to use your VID and PID. Use the format as shown
87 ; VID and PIDs. For each supported device, append
/linux/drivers/cpufreq/
H A Dpowernow-k7.h12 VID:5, // 12:8 member
/linux/include/uapi/linux/
H A Dif_vlan.h56 int VID; member
/linux/Documentation/networking/
H A Dswitchdev.rst189 bridge fdb add dev DEV ADDRESS [vlan VID] [self] static
202 bridge fdb add dev DEV ADDRESS [vlan VID] master static
440 of a VLAN-aware bridge doing ingress VID checking). See below for details.
465 device with a VID that is not programmed into the bridge/switch's VLAN table
469 the device with a VID that is not programmed into the bridges/switch's VLAN
470 table must be dropped (strict VID checking).
485 configured to map all traffic, except the packets tagged with a VID
486 belonging to a VLAN upper interface, to an internal VID corresponding to
487 untagged packets. This internal VID spans all ports of the VLAN-unaware
488 bridge. The VID corresponding to the VLAN upper interface spans the
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dtrinityd.h41 # define VID(x) ((x) << 16) macro
/linux/drivers/scsi/megaraid/
H A DKconfig.megaraid24 OEM Product Name VID :DID :SVID:SSID
/linux/Documentation/admin-guide/perf/
H A Dcxl.rst64 $# perf stat -a -e cxl_pmu_mem0.0/vid=VID,gid=GID,mask=MASK/

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