xref: /linux/drivers/net/wireless/realtek/rtlwifi/rtl8192d/def.h (revision 621cde16e49b3ecf7d59a8106a20aaebfb4a59a9)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
3 
4 #ifndef __RTL92D_DEF_H__
5 #define __RTL92D_DEF_H__
6 
7 /* Min Spacing related settings. */
8 #define	MAX_MSS_DENSITY_2T				0x13
9 #define	MAX_MSS_DENSITY_1T				0x0A
10 
11 #define RF6052_MAX_TX_PWR				0x3F
12 #define RF6052_MAX_PATH					2
13 
14 #define	PHY_RSSI_SLID_WIN_MAX				100
15 #define	PHY_LINKQUALITY_SLID_WIN_MAX			20
16 #define	PHY_BEACON_RSSI_SLID_WIN_MAX			10
17 
18 #define RT_AC_INT_MASKS		(IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
19 
20 #define RX_SMOOTH_FACTOR				20
21 
22 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE			0
23 #define HAL_PRIME_CHNL_OFFSET_LOWER			1
24 #define HAL_PRIME_CHNL_OFFSET_UPPER			2
25 
26 #define RX_MPDU_QUEUE					0
27 #define RX_CMD_QUEUE					1
28 
29 enum version_8192d {
30 	VERSION_TEST_CHIP_88C = 0x0000,
31 	VERSION_TEST_CHIP_92C = 0x0020,
32 	VERSION_TEST_UMC_CHIP_8723 = 0x0081,
33 	VERSION_NORMAL_TSMC_CHIP_88C = 0x0008,
34 	VERSION_NORMAL_TSMC_CHIP_92C = 0x0028,
35 	VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x0018,
36 	VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x0088,
37 	VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x00a8,
38 	VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x0098,
39 	VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT = 0x0089,
40 	VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT = 0x1089,
41 	VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x1088,
42 	VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x10a8,
43 	VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x1090,
44 	VERSION_TEST_CHIP_92D_SINGLEPHY = 0x0022,
45 	VERSION_TEST_CHIP_92D_DUALPHY = 0x0002,
46 	VERSION_NORMAL_CHIP_92D_SINGLEPHY = 0x002a,
47 	VERSION_NORMAL_CHIP_92D_DUALPHY = 0x000a,
48 	VERSION_NORMAL_CHIP_92D_C_CUT_SINGLEPHY = 0x202a,
49 	VERSION_NORMAL_CHIP_92D_C_CUT_DUALPHY = 0x200a,
50 	VERSION_NORMAL_CHIP_92D_D_CUT_SINGLEPHY = 0x302a,
51 	VERSION_NORMAL_CHIP_92D_D_CUT_DUALPHY = 0x300a,
52 	VERSION_NORMAL_CHIP_92D_E_CUT_SINGLEPHY = 0x402a,
53 	VERSION_NORMAL_CHIP_92D_E_CUT_DUALPHY = 0x400a,
54 };
55 
56 /* for 92D */
57 #define CHIP_92D_SINGLEPHY		BIT(9)
58 
59 /* Chip specific */
60 #define CHIP_BONDING_IDENTIFIER(_value)	(((_value)>>22)&0x3)
61 #define CHIP_BONDING_92C_1T2R			0x1
62 #define CHIP_BONDING_88C_USB_MCARD		0x2
63 #define CHIP_BONDING_88C_USB_HP			0x1
64 
65 /* [15:12] IC version(CUT): A-cut=0, B-cut=1, C-cut=2, D-cut=3 */
66 /* [7] Manufacturer: TSMC=0, UMC=1 */
67 /* [6:4] RF type: 1T1R=0, 1T2R=1, 2T2R=2 */
68 /* [3] Chip type: TEST=0, NORMAL=1 */
69 /* [2:0] IC type: 81xxC=0, 8723=1, 92D=2 */
70 #define CHIP_8723			BIT(0)
71 #define CHIP_92D			BIT(1)
72 #define NORMAL_CHIP			BIT(3)
73 #define RF_TYPE_1T1R			(~(BIT(4)|BIT(5)|BIT(6)))
74 #define RF_TYPE_1T2R			BIT(4)
75 #define RF_TYPE_2T2R			BIT(5)
76 #define CHIP_VENDOR_UMC			BIT(7)
77 #define CHIP_92D_B_CUT			BIT(12)
78 #define CHIP_92D_C_CUT			BIT(13)
79 #define CHIP_92D_D_CUT			(BIT(13)|BIT(12))
80 #define CHIP_92D_E_CUT			BIT(14)
81 
82 /* MASK */
83 #define IC_TYPE_MASK			(BIT(0)|BIT(1)|BIT(2))
84 #define CHIP_TYPE_MASK			BIT(3)
85 #define RF_TYPE_MASK			(BIT(4)|BIT(5)|BIT(6))
86 #define MANUFACTUER_MASK		BIT(7)
87 #define ROM_VERSION_MASK		(BIT(11)|BIT(10)|BIT(9)|BIT(8))
88 #define CUT_VERSION_MASK		(BIT(15)|BIT(14)|BIT(13)|BIT(12))
89 
90 
91 /* Get element */
92 #define GET_CVID_IC_TYPE(version)	((version) & IC_TYPE_MASK)
93 #define GET_CVID_CHIP_TYPE(version)	((version) & CHIP_TYPE_MASK)
94 #define GET_CVID_RF_TYPE(version)	((version) & RF_TYPE_MASK)
95 #define GET_CVID_MANUFACTUER(version)	((version) & MANUFACTUER_MASK)
96 #define GET_CVID_ROM_VERSION(version)	((version) & ROM_VERSION_MASK)
97 #define GET_CVID_CUT_VERSION(version)	((version) & CUT_VERSION_MASK)
98 
99 #define IS_1T1R(version)		((GET_CVID_RF_TYPE(version)) ?	\
100 					 false : true)
101 #define IS_1T2R(version)		((GET_CVID_RF_TYPE(version) ==	\
102 					 RF_TYPE_1T2R) ? true : false)
103 #define IS_2T2R(version)		((GET_CVID_RF_TYPE(version) ==	\
104 					 RF_TYPE_2T2R) ? true : false)
105 
106 #define IS_92D_SINGLEPHY(version)	((IS_92D(version)) ?		\
107 				 (IS_2T2R(version) ? true : false) : false)
108 #define IS_92D(version)			((GET_CVID_IC_TYPE(version) ==	\
109 					 CHIP_92D) ? true : false)
110 #define IS_92D_C_CUT(version)		((IS_92D(version)) ?		\
111 				 ((GET_CVID_CUT_VERSION(version) ==	\
112 				 CHIP_92D_C_CUT) ? true : false) : false)
113 #define IS_92D_D_CUT(version)			((IS_92D(version)) ?	\
114 				 ((GET_CVID_CUT_VERSION(version) ==	\
115 				 CHIP_92D_D_CUT) ? true : false) : false)
116 #define IS_92D_E_CUT(version)		((IS_92D(version)) ?		\
117 				 ((GET_CVID_CUT_VERSION(version) ==	\
118 				 CHIP_92D_E_CUT) ? true : false) : false)
119 
120 enum rf_optype {
121 	RF_OP_BY_SW_3WIRE = 0,
122 	RF_OP_BY_FW,
123 	RF_OP_MAX
124 };
125 
126 enum rtl_desc_qsel {
127 	QSLT_BK = 0x2,
128 	QSLT_BE = 0x0,
129 	QSLT_VI = 0x5,
130 	QSLT_VO = 0x7,
131 	QSLT_BEACON = 0x10,
132 	QSLT_HIGH = 0x11,
133 	QSLT_MGNT = 0x12,
134 	QSLT_CMD = 0x13,
135 };
136 
137 enum channel_plan {
138 	CHPL_FCC	= 0,
139 	CHPL_IC		= 1,
140 	CHPL_ETSI	= 2,
141 	CHPL_SPAIN	= 3,
142 	CHPL_FRANCE	= 4,
143 	CHPL_MKK	= 5,
144 	CHPL_MKK1	= 6,
145 	CHPL_ISRAEL	= 7,
146 	CHPL_TELEC	= 8,
147 	CHPL_GLOBAL	= 9,
148 	CHPL_WORLD	= 10,
149 };
150 
151 struct phy_sts_cck_8192d {
152 	u8 adc_pwdb_X[4];
153 	u8 sq_rpt;
154 	u8 cck_agc_rpt;
155 };
156 
157 struct h2c_cmd_8192c {
158 	u8 element_id;
159 	u32 cmd_len;
160 	u8 *p_cmdbuffer;
161 };
162 
163 struct txpower_info {
164 	u8 cck_index[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
165 	u8 ht40_1sindex[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
166 	u8 ht40_2sindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
167 	u8 ht20indexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
168 	u8 ofdmindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
169 	u8 ht40maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
170 	u8 ht20maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
171 	u8 tssi_a[3];		/* 5GL/5GM/5GH */
172 	u8 tssi_b[3];
173 };
174 
175 #endif
176