xref: /linux/drivers/media/platform/verisilicon/rockchip_vpu2_regs.h (revision 4f2c0a4acffbec01079c28f839422e64ddeff004)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Hantro VPU codec driver
4  *
5  * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
6  *	Alpha Lin <alpha.lin@rock-chips.com>
7  */
8 
9 #ifndef ROCKCHIP_VPU2_REGS_H_
10 #define ROCKCHIP_VPU2_REGS_H_
11 
12 /* Encoder registers. */
13 #define VEPU_REG_VP8_QUT_1ST(i)			(0x000 + ((i) * 0x24))
14 #define     VEPU_REG_VP8_QUT_DC_Y2(x)			(((x) & 0x3fff) << 16)
15 #define     VEPU_REG_VP8_QUT_DC_Y1(x)			(((x) & 0x3fff) << 0)
16 #define VEPU_REG_VP8_QUT_2ND(i)			(0x004 + ((i) * 0x24))
17 #define     VEPU_REG_VP8_QUT_AC_Y1(x)			(((x) & 0x3fff) << 16)
18 #define     VEPU_REG_VP8_QUT_DC_CHR(x)			(((x) & 0x3fff) << 0)
19 #define VEPU_REG_VP8_QUT_3RD(i)			(0x008 + ((i) * 0x24))
20 #define     VEPU_REG_VP8_QUT_AC_CHR(x)			(((x) & 0x3fff) << 16)
21 #define     VEPU_REG_VP8_QUT_AC_Y2(x)			(((x) & 0x3fff) << 0)
22 #define VEPU_REG_VP8_QUT_4TH(i)			(0x00c + ((i) * 0x24))
23 #define     VEPU_REG_VP8_QUT_ZB_DC_CHR(x)		(((x) & 0x1ff) << 18)
24 #define     VEPU_REG_VP8_QUT_ZB_DC_Y2(x)		(((x) & 0x1ff) << 9)
25 #define     VEPU_REG_VP8_QUT_ZB_DC_Y1(x)		(((x) & 0x1ff) << 0)
26 #define VEPU_REG_VP8_QUT_5TH(i)			(0x010 + ((i) * 0x24))
27 #define     VEPU_REG_VP8_QUT_ZB_AC_CHR(x)		(((x) & 0x1ff) << 18)
28 #define     VEPU_REG_VP8_QUT_ZB_AC_Y2(x)		(((x) & 0x1ff) << 9)
29 #define     VEPU_REG_VP8_QUT_ZB_AC_Y1(x)		(((x) & 0x1ff) << 0)
30 #define VEPU_REG_VP8_QUT_6TH(i)			(0x014 + ((i) * 0x24))
31 #define     VEPU_REG_VP8_QUT_RND_DC_CHR(x)		(((x) & 0xff) << 16)
32 #define     VEPU_REG_VP8_QUT_RND_DC_Y2(x)		(((x) & 0xff) << 8)
33 #define     VEPU_REG_VP8_QUT_RND_DC_Y1(x)		(((x) & 0xff) << 0)
34 #define VEPU_REG_VP8_QUT_7TH(i)			(0x018 + ((i) * 0x24))
35 #define     VEPU_REG_VP8_QUT_RND_AC_CHR(x)		(((x) & 0xff) << 16)
36 #define     VEPU_REG_VP8_QUT_RND_AC_Y2(x)		(((x) & 0xff) << 8)
37 #define     VEPU_REG_VP8_QUT_RND_AC_Y1(x)		(((x) & 0xff) << 0)
38 #define VEPU_REG_VP8_QUT_8TH(i)			(0x01c + ((i) * 0x24))
39 #define     VEPU_REG_VP8_SEG_FILTER_LEVEL(x)		(((x) & 0x3f) << 25)
40 #define     VEPU_REG_VP8_DEQUT_DC_CHR(x)		(((x) & 0xff) << 17)
41 #define     VEPU_REG_VP8_DEQUT_DC_Y2(x)			(((x) & 0x1ff) << 8)
42 #define     VEPU_REG_VP8_DEQUT_DC_Y1(x)			(((x) & 0xff) << 0)
43 #define VEPU_REG_VP8_QUT_9TH(i)			(0x020 + ((i) * 0x24))
44 #define     VEPU_REG_VP8_DEQUT_AC_CHR(x)		(((x) & 0x1ff) << 18)
45 #define     VEPU_REG_VP8_DEQUT_AC_Y2(x)			(((x) & 0x1ff) << 9)
46 #define     VEPU_REG_VP8_DEQUT_AC_Y1(x)			(((x) & 0x1ff) << 0)
47 #define VEPU_REG_ADDR_VP8_SEG_MAP		0x06c
48 #define VEPU_REG_VP8_INTRA_4X4_PENALTY(i)	(0x070 + ((i) * 0x4))
49 #define     VEPU_REG_VP8_INTRA_4X4_PENALTY_0(x)		(((x) & 0xfff) << 0)
50 #define     VEPU_REG_VP8_INTRA_4x4_PENALTY_1(x)		(((x) & 0xfff) << 16)
51 #define VEPU_REG_VP8_INTRA_16X16_PENALTY(i)	(0x084 + ((i) * 0x4))
52 #define     VEPU_REG_VP8_INTRA_16X16_PENALTY_0(x)	(((x) & 0xfff) << 0)
53 #define     VEPU_REG_VP8_INTRA_16X16_PENALTY_1(x)	(((x) & 0xfff) << 16)
54 #define VEPU_REG_VP8_CONTROL			0x0a0
55 #define     VEPU_REG_VP8_LF_MODE_DELTA_BPRED(x)		(((x) & 0x1f) << 24)
56 #define     VEPU_REG_VP8_LF_REF_DELTA_INTRA_MB(x)	(((x) & 0x7f) << 16)
57 #define     VEPU_REG_VP8_INTER_TYPE_BIT_COST(x)		(((x) & 0xfff) << 0)
58 #define VEPU_REG_VP8_REF_FRAME_VAL		0x0a4
59 #define     VEPU_REG_VP8_COEF_DMV_PENALTY(x)		(((x) & 0xfff) << 16)
60 #define     VEPU_REG_VP8_REF_FRAME(x)			(((x) & 0xfff) << 0)
61 #define VEPU_REG_VP8_LOOP_FILTER_REF_DELTA	0x0a8
62 #define     VEPU_REG_VP8_LF_REF_DELTA_ALT_REF(x)	(((x) & 0x7f) << 16)
63 #define     VEPU_REG_VP8_LF_REF_DELTA_LAST_REF(x)	(((x) & 0x7f) << 8)
64 #define     VEPU_REG_VP8_LF_REF_DELTA_GOLDEN(x)		(((x) & 0x7f) << 0)
65 #define VEPU_REG_VP8_LOOP_FILTER_MODE_DELTA	0x0ac
66 #define     VEPU_REG_VP8_LF_MODE_DELTA_SPLITMV(x)	(((x) & 0x7f) << 16)
67 #define     VEPU_REG_VP8_LF_MODE_DELTA_ZEROMV(x)	(((x) & 0x7f) << 8)
68 #define     VEPU_REG_VP8_LF_MODE_DELTA_NEWMV(x)		(((x) & 0x7f) << 0)
69 #define	VEPU_REG_JPEG_LUMA_QUAT(i)		(0x000 + ((i) * 0x4))
70 #define	VEPU_REG_JPEG_CHROMA_QUAT(i)		(0x040 + ((i) * 0x4))
71 #define VEPU_REG_INTRA_SLICE_BITMAP(i)		(0x0b0 + ((i) * 0x4))
72 #define VEPU_REG_ADDR_VP8_DCT_PART(i)		(0x0b0 + ((i) * 0x4))
73 #define VEPU_REG_INTRA_AREA_CTRL		0x0b8
74 #define     VEPU_REG_INTRA_AREA_TOP(x)			(((x) & 0xff) << 24)
75 #define     VEPU_REG_INTRA_AREA_BOTTOM(x)		(((x) & 0xff) << 16)
76 #define     VEPU_REG_INTRA_AREA_LEFT(x)			(((x) & 0xff) << 8)
77 #define     VEPU_REG_INTRA_AREA_RIGHT(x)		(((x) & 0xff) << 0)
78 #define VEPU_REG_CIR_INTRA_CTRL			0x0bc
79 #define     VEPU_REG_CIR_INTRA_FIRST_MB(x)		(((x) & 0xffff) << 16)
80 #define     VEPU_REG_CIR_INTRA_INTERVAL(x)		(((x) & 0xffff) << 0)
81 #define VEPU_REG_ADDR_IN_PLANE_0		0x0c0
82 #define VEPU_REG_ADDR_IN_PLANE_1		0x0c4
83 #define VEPU_REG_ADDR_IN_PLANE_2		0x0c8
84 #define VEPU_REG_STR_HDR_REM_MSB		0x0cc
85 #define VEPU_REG_STR_HDR_REM_LSB		0x0d0
86 #define VEPU_REG_STR_BUF_LIMIT			0x0d4
87 #define VEPU_REG_AXI_CTRL			0x0d8
88 #define     VEPU_REG_AXI_CTRL_READ_ID(x)		(((x) & 0xff) << 24)
89 #define     VEPU_REG_AXI_CTRL_WRITE_ID(x)		(((x) & 0xff) << 16)
90 #define     VEPU_REG_AXI_CTRL_BURST_LEN(x)		(((x) & 0x3f) << 8)
91 #define     VEPU_REG_AXI_CTRL_INCREMENT_MODE(x)		(((x) & 0x01) << 2)
92 #define     VEPU_REG_AXI_CTRL_BIRST_DISCARD(x)		(((x) & 0x01) << 1)
93 #define     VEPU_REG_AXI_CTRL_BIRST_DISABLE		BIT(0)
94 #define VEPU_QP_ADJUST_MAD_DELTA_ROI		0x0dc
95 #define     VEPU_REG_ROI_QP_DELTA_1			(((x) & 0xf) << 12)
96 #define     VEPU_REG_ROI_QP_DELTA_2			(((x) & 0xf) << 8)
97 #define     VEPU_REG_MAD_QP_ADJUSTMENT			(((x) & 0xf) << 0)
98 #define VEPU_REG_ADDR_REF_LUMA			0x0e0
99 #define VEPU_REG_ADDR_REF_CHROMA		0x0e4
100 #define VEPU_REG_QP_SUM_DIV2			0x0e8
101 #define     VEPU_REG_QP_SUM(x)				(((x) & 0x001fffff) * 2)
102 #define VEPU_REG_ENC_CTRL0			0x0ec
103 #define     VEPU_REG_DISABLE_QUARTER_PIXEL_MV		BIT(28)
104 #define     VEPU_REG_DEBLOCKING_FILTER_MODE(x)		(((x) & 0x3) << 24)
105 #define     VEPU_REG_CABAC_INIT_IDC(x)			(((x) & 0x3) << 21)
106 #define     VEPU_REG_ENTROPY_CODING_MODE		BIT(20)
107 #define     VEPU_REG_H264_TRANS8X8_MODE			BIT(17)
108 #define     VEPU_REG_H264_INTER4X4_MODE			BIT(16)
109 #define     VEPU_REG_H264_STREAM_MODE			BIT(15)
110 #define     VEPU_REG_H264_SLICE_SIZE(x)			(((x) & 0x7f) << 8)
111 #define VEPU_REG_ENC_OVER_FILL_STRM_OFFSET	0x0f0
112 #define     VEPU_REG_STREAM_START_OFFSET(x)		(((x) & 0x3f) << 16)
113 #define     VEPU_REG_SKIP_MACROBLOCK_PENALTY(x)		(((x) & 0xff) << 8)
114 #define     VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(x)		(((x) & 0x3) << 4)
115 #define     VEPU_REG_IN_IMG_CTRL_OVRFLB(x)		(((x) & 0xf) << 0)
116 #define VEPU_REG_INPUT_LUMA_INFO		0x0f4
117 #define     VEPU_REG_IN_IMG_CHROMA_OFFSET(x)		(((x) & 0x7) << 20)
118 #define     VEPU_REG_IN_IMG_LUMA_OFFSET(x)		(((x) & 0x7) << 16)
119 #define     VEPU_REG_IN_IMG_CTRL_ROW_LEN(x)		(((x) & 0x3fff) << 0)
120 #define VEPU_REG_RLC_SUM			0x0f8
121 #define     VEPU_REG_RLC_SUM_OUT(x)			(((x) & 0x007fffff) * 4)
122 #define VEPU_REG_SPLIT_PENALTY_4X4		0x0f8
123 #define	    VEPU_REG_VP8_SPLIT_PENALTY_4X4		(((x) & 0x1ff) << 19)
124 #define VEPU_REG_ADDR_REC_LUMA			0x0fc
125 #define VEPU_REG_ADDR_REC_CHROMA		0x100
126 #define VEPU_REG_CHECKPOINT(i)			(0x104 + ((i) * 0x4))
127 #define     VEPU_REG_CHECKPOINT_CHECK0(x)		(((x) & 0xffff))
128 #define     VEPU_REG_CHECKPOINT_CHECK1(x)		(((x) & 0xffff) << 16)
129 #define     VEPU_REG_CHECKPOINT_RESULT(x) \
130 		((((x) >> (16 - 16 * ((i) & 1))) & 0xffff) * 32)
131 #define VEPU_REG_VP8_SEG0_QUANT_AC_Y1		0x104
132 #define     VEPU_REG_VP8_SEG0_RND_AC_Y1(x)		(((x) & 0xff) << 23)
133 #define     VEPU_REG_VP8_SEG0_ZBIN_AC_Y1(x)		(((x) & 0x1ff) << 14)
134 #define     VEPU_REG_VP8_SEG0_QUT_AC_Y1(x)		(((x) & 0x3fff) << 0)
135 #define VEPU_REG_VP8_SEG0_QUANT_DC_Y2		0x108
136 #define     VEPU_REG_VP8_SEG0_RND_DC_Y2(x)		(((x) & 0xff) << 23)
137 #define     VEPU_REG_VP8_SEG0_ZBIN_DC_Y2(x)		(((x) & 0x1ff) << 14)
138 #define     VEPU_REG_VP8_SEG0_QUT_DC_Y2(x)		(((x) & 0x3fff) << 0)
139 #define VEPU_REG_VP8_SEG0_QUANT_AC_Y2		0x10c
140 #define     VEPU_REG_VP8_SEG0_RND_AC_Y2(x)		(((x) & 0xff) << 23)
141 #define     VEPU_REG_VP8_SEG0_ZBIN_AC_Y2(x)		(((x) & 0x1ff) << 14)
142 #define     VEPU_REG_VP8_SEG0_QUT_AC_Y2(x)		(((x) & 0x3fff) << 0)
143 #define VEPU_REG_VP8_SEG0_QUANT_DC_CHR		0x110
144 #define     VEPU_REG_VP8_SEG0_RND_DC_CHR(x)		(((x) & 0xff) << 23)
145 #define     VEPU_REG_VP8_SEG0_ZBIN_DC_CHR(x)		(((x) & 0x1ff) << 14)
146 #define     VEPU_REG_VP8_SEG0_QUT_DC_CHR(x)		(((x) & 0x3fff) << 0)
147 #define VEPU_REG_VP8_SEG0_QUANT_AC_CHR		0x114
148 #define     VEPU_REG_VP8_SEG0_RND_AC_CHR(x)		(((x) & 0xff) << 23)
149 #define     VEPU_REG_VP8_SEG0_ZBIN_AC_CHR(x)		(((x) & 0x1ff) << 14)
150 #define     VEPU_REG_VP8_SEG0_QUT_AC_CHR(x)		(((x) & 0x3fff) << 0)
151 #define VEPU_REG_VP8_SEG0_QUANT_DQUT		0x118
152 #define     VEPU_REG_VP8_MV_REF_IDX1(x)			(((x) & 0x03) << 26)
153 #define     VEPU_REG_VP8_SEG0_DQUT_DC_Y2(x)		(((x) & 0x1ff) << 17)
154 #define     VEPU_REG_VP8_SEG0_DQUT_AC_Y1(x)		(((x) & 0x1ff) << 8)
155 #define     VEPU_REG_VP8_SEG0_DQUT_DC_Y1(x)		(((x) & 0xff) << 0)
156 #define VEPU_REG_CHKPT_WORD_ERR(i)		(0x118 + ((i) * 0x4))
157 #define     VEPU_REG_CHKPT_WORD_ERR_CHK0(x)		(((x) & 0xffff))
158 #define     VEPU_REG_CHKPT_WORD_ERR_CHK1(x)		(((x) & 0xffff) << 16)
159 #define VEPU_REG_VP8_SEG0_QUANT_DQUT_1		0x11c
160 #define     VEPU_REG_VP8_SEGMENT_MAP_UPDATE		BIT(30)
161 #define     VEPU_REG_VP8_SEGMENT_EN			BIT(29)
162 #define     VEPU_REG_VP8_MV_REF_IDX2_EN			BIT(28)
163 #define     VEPU_REG_VP8_MV_REF_IDX2(x)			(((x) & 0x03) << 26)
164 #define     VEPU_REG_VP8_SEG0_DQUT_AC_CHR(x)		(((x) & 0x1ff) << 17)
165 #define     VEPU_REG_VP8_SEG0_DQUT_DC_CHR(x)		(((x) & 0xff) << 9)
166 #define     VEPU_REG_VP8_SEG0_DQUT_AC_Y2(x)		(((x) & 0x1ff) << 0)
167 #define VEPU_REG_VP8_BOOL_ENC_VALUE		0x120
168 #define VEPU_REG_CHKPT_DELTA_QP			0x124
169 #define     VEPU_REG_CHKPT_DELTA_QP_CHK0(x)		(((x) & 0x0f) << 0)
170 #define     VEPU_REG_CHKPT_DELTA_QP_CHK1(x)		(((x) & 0x0f) << 4)
171 #define     VEPU_REG_CHKPT_DELTA_QP_CHK2(x)		(((x) & 0x0f) << 8)
172 #define     VEPU_REG_CHKPT_DELTA_QP_CHK3(x)		(((x) & 0x0f) << 12)
173 #define     VEPU_REG_CHKPT_DELTA_QP_CHK4(x)		(((x) & 0x0f) << 16)
174 #define     VEPU_REG_CHKPT_DELTA_QP_CHK5(x)		(((x) & 0x0f) << 20)
175 #define     VEPU_REG_CHKPT_DELTA_QP_CHK6(x)		(((x) & 0x0f) << 24)
176 #define VEPU_REG_VP8_ENC_CTRL2			0x124
177 #define     VEPU_REG_VP8_ZERO_MV_PENALTY_FOR_REF2(x)	(((x) & 0xff) << 24)
178 #define     VEPU_REG_VP8_FILTER_SHARPNESS(x)		(((x) & 0x07) << 21)
179 #define     VEPU_REG_VP8_FILTER_LEVEL(x)		(((x) & 0x3f) << 15)
180 #define     VEPU_REG_VP8_DCT_PARTITION_CNT(x)		(((x) & 0x03) << 13)
181 #define     VEPU_REG_VP8_BOOL_ENC_VALUE_BITS(x)		(((x) & 0x1f) << 8)
182 #define     VEPU_REG_VP8_BOOL_ENC_RANGE(x)		(((x) & 0xff) << 0)
183 #define VEPU_REG_ENC_CTRL1			0x128
184 #define     VEPU_REG_MAD_THRESHOLD(x)			(((x) & 0x3f) << 24)
185 #define     VEPU_REG_COMPLETED_SLICES(x)		(((x) & 0xff) << 16)
186 #define     VEPU_REG_IN_IMG_CTRL_FMT(x)			(((x) & 0xf) << 4)
187 #define     VEPU_REG_IN_IMG_ROTATE_MODE(x)		(((x) & 0x3) << 2)
188 #define     VEPU_REG_SIZE_TABLE_PRESENT			BIT(0)
189 #define VEPU_REG_INTRA_INTER_MODE		0x12c
190 #define     VEPU_REG_INTRA16X16_MODE(x)			(((x) & 0xffff) << 16)
191 #define     VEPU_REG_INTER_MODE(x)			(((x) & 0xffff) << 0)
192 #define VEPU_REG_ENC_CTRL2			0x130
193 #define     VEPU_REG_PPS_INIT_QP(x)			(((x) & 0x3f) << 26)
194 #define     VEPU_REG_SLICE_FILTER_ALPHA(x)		(((x) & 0xf) << 22)
195 #define     VEPU_REG_SLICE_FILTER_BETA(x)		(((x) & 0xf) << 18)
196 #define     VEPU_REG_CHROMA_QP_OFFSET(x)		(((x) & 0x1f) << 13)
197 #define     VEPU_REG_FILTER_DISABLE			BIT(5)
198 #define     VEPU_REG_IDR_PIC_ID(x)			(((x) & 0xf) << 1)
199 #define     VEPU_REG_CONSTRAINED_INTRA_PREDICTION	BIT(0)
200 #define VEPU_REG_ADDR_OUTPUT_STREAM		0x134
201 #define VEPU_REG_ADDR_OUTPUT_CTRL		0x138
202 #define VEPU_REG_ADDR_NEXT_PIC			0x13c
203 #define VEPU_REG_ADDR_MV_OUT			0x140
204 #define VEPU_REG_ADDR_CABAC_TBL			0x144
205 #define VEPU_REG_ROI1				0x148
206 #define     VEPU_REG_ROI1_TOP_MB(x)			(((x) & 0xff) << 24)
207 #define     VEPU_REG_ROI1_BOTTOM_MB(x)			(((x) & 0xff) << 16)
208 #define     VEPU_REG_ROI1_LEFT_MB(x)			(((x) & 0xff) << 8)
209 #define     VEPU_REG_ROI1_RIGHT_MB(x)			(((x) & 0xff) << 0)
210 #define VEPU_REG_ROI2				0x14c
211 #define     VEPU_REG_ROI2_TOP_MB(x)			(((x) & 0xff) << 24)
212 #define     VEPU_REG_ROI2_BOTTOM_MB(x)			(((x) & 0xff) << 16)
213 #define     VEPU_REG_ROI2_LEFT_MB(x)			(((x) & 0xff) << 8)
214 #define     VEPU_REG_ROI2_RIGHT_MB(x)			(((x) & 0xff) << 0)
215 #define VEPU_REG_STABLE_MATRIX(i)		(0x150 + ((i) * 0x4))
216 #define VEPU_REG_STABLE_MOTION_SUM		0x174
217 #define VEPU_REG_STABILIZATION_OUTPUT		0x178
218 #define     VEPU_REG_STABLE_MIN_VALUE(x)		(((x) & 0xffffff) << 8)
219 #define     VEPU_REG_STABLE_MODE_SEL(x)			(((x) & 0x3) << 6)
220 #define     VEPU_REG_STABLE_HOR_GMV(x)			(((x) & 0x3f) << 0)
221 #define VEPU_REG_RGB2YUV_CONVERSION_COEF1	0x17c
222 #define     VEPU_REG_RGB2YUV_CONVERSION_COEFB(x)	(((x) & 0xffff) << 16)
223 #define     VEPU_REG_RGB2YUV_CONVERSION_COEFA(x)	(((x) & 0xffff) << 0)
224 #define VEPU_REG_RGB2YUV_CONVERSION_COEF2	0x180
225 #define     VEPU_REG_RGB2YUV_CONVERSION_COEFE(x)	(((x) & 0xffff) << 16)
226 #define     VEPU_REG_RGB2YUV_CONVERSION_COEFC(x)	(((x) & 0xffff) << 0)
227 #define VEPU_REG_RGB2YUV_CONVERSION_COEF3	0x184
228 #define     VEPU_REG_RGB2YUV_CONVERSION_COEFF(x)	(((x) & 0xffff) << 0)
229 #define VEPU_REG_RGB_MASK_MSB			0x188
230 #define     VEPU_REG_RGB_MASK_B_MSB(x)			(((x) & 0x1f) << 16)
231 #define     VEPU_REG_RGB_MASK_G_MSB(x)			(((x) & 0x1f) << 8)
232 #define     VEPU_REG_RGB_MASK_R_MSB(x)			(((x) & 0x1f) << 0)
233 #define VEPU_REG_MV_PENALTY			0x18c
234 #define     VEPU_REG_1MV_PENALTY(x)			(((x) & 0x3ff) << 21)
235 #define     VEPU_REG_QMV_PENALTY(x)			(((x) & 0x3ff) << 11)
236 #define     VEPU_REG_4MV_PENALTY(x)			(((x) & 0x3ff) << 1)
237 #define     VEPU_REG_SPLIT_MV_MODE_EN			BIT(0)
238 #define VEPU_REG_QP_VAL				0x190
239 #define     VEPU_REG_H264_LUMA_INIT_QP(x)		(((x) & 0x3f) << 26)
240 #define     VEPU_REG_H264_QP_MAX(x)			(((x) & 0x3f) << 20)
241 #define     VEPU_REG_H264_QP_MIN(x)			(((x) & 0x3f) << 14)
242 #define     VEPU_REG_H264_CHKPT_DISTANCE(x)		(((x) & 0xfff) << 0)
243 #define VEPU_REG_VP8_SEG0_QUANT_DC_Y1		0x190
244 #define     VEPU_REG_VP8_SEG0_RND_DC_Y1(x)		(((x) & 0xff) << 23)
245 #define     VEPU_REG_VP8_SEG0_ZBIN_DC_Y1(x)		(((x) & 0x1ff) << 14)
246 #define     VEPU_REG_VP8_SEG0_QUT_DC_Y1(x)		(((x) & 0x3fff) << 0)
247 #define VEPU_REG_MVC_RELATE			0x198
248 #define     VEPU_REG_ZERO_MV_FAVOR_D2(x)		(((x) & 0xf) << 20)
249 #define     VEPU_REG_PENALTY_4X4MV(x)			(((x) & 0x1ff) << 11)
250 #define     VEPU_REG_MVC_VIEW_ID(x)			(((x) & 0x7) << 8)
251 #define     VEPU_REG_MVC_ANCHOR_PIC_FLAG		BIT(7)
252 #define     VEPU_REG_MVC_PRIORITY_ID(x)			(((x) & 0x7) << 4)
253 #define     VEPU_REG_MVC_TEMPORAL_ID(x)			(((x) & 0x7) << 1)
254 #define     VEPU_REG_MVC_INTER_VIEW_FLAG		BIT(0)
255 #define VEPU_REG_ENCODE_START			0x19c
256 #define     VEPU_REG_MB_HEIGHT(x)			(((x) & 0x1ff) << 20)
257 #define     VEPU_REG_MB_WIDTH(x)			(((x) & 0x1ff) << 8)
258 #define     VEPU_REG_FRAME_TYPE_INTER			(0x0 << 6)
259 #define     VEPU_REG_FRAME_TYPE_INTRA			(0x1 << 6)
260 #define     VEPU_REG_FRAME_TYPE_MVCINTER		(0x2 << 6)
261 #define     VEPU_REG_ENCODE_FORMAT_JPEG			(0x2 << 4)
262 #define     VEPU_REG_ENCODE_FORMAT_H264			(0x3 << 4)
263 #define     VEPU_REG_ENCODE_ENABLE			BIT(0)
264 #define VEPU_REG_MB_CTRL			0x1a0
265 #define     VEPU_REG_MB_CNT_OUT(x)			(((x) & 0xffff) << 16)
266 #define     VEPU_REG_MB_CNT_SET(x)			(((x) & 0xffff) << 0)
267 #define VEPU_REG_DATA_ENDIAN			0x1a4
268 #define     VEPU_REG_INPUT_SWAP8			BIT(31)
269 #define     VEPU_REG_INPUT_SWAP16			BIT(30)
270 #define     VEPU_REG_INPUT_SWAP32			BIT(29)
271 #define     VEPU_REG_OUTPUT_SWAP8			BIT(28)
272 #define     VEPU_REG_OUTPUT_SWAP16			BIT(27)
273 #define     VEPU_REG_OUTPUT_SWAP32			BIT(26)
274 #define     VEPU_REG_TEST_IRQ				BIT(24)
275 #define     VEPU_REG_TEST_COUNTER(x)			(((x) & 0xf) << 20)
276 #define     VEPU_REG_TEST_REG				BIT(19)
277 #define     VEPU_REG_TEST_MEMORY			BIT(18)
278 #define     VEPU_REG_TEST_LEN(x)			(((x) & 0x3ffff) << 0)
279 #define VEPU_REG_ENC_CTRL3			0x1a8
280 #define     VEPU_REG_PPS_ID(x)				(((x) & 0xff) << 24)
281 #define     VEPU_REG_INTRA_PRED_MODE(x)			(((x) & 0xff) << 16)
282 #define     VEPU_REG_FRAME_NUM(x)			(((x) & 0xffff) << 0)
283 #define VEPU_REG_ENC_CTRL4			0x1ac
284 #define     VEPU_REG_MV_PENALTY_16X8_8X16(x)		(((x) & 0x3ff) << 20)
285 #define     VEPU_REG_MV_PENALTY_8X8(x)			(((x) & 0x3ff) << 10)
286 #define     VEPU_REG_MV_PENALTY_8X4_4X8(x)		(((x) & 0x3ff) << 0)
287 #define VEPU_REG_ADDR_VP8_PROB_CNT		0x1b0
288 #define VEPU_REG_INTERRUPT			0x1b4
289 #define     VEPU_REG_INTERRUPT_NON			BIT(28)
290 #define     VEPU_REG_MV_WRITE_EN			BIT(24)
291 #define     VEPU_REG_RECON_WRITE_DIS			BIT(20)
292 #define     VEPU_REG_INTERRUPT_SLICE_READY_EN		BIT(16)
293 #define     VEPU_REG_CLK_GATING_EN			BIT(12)
294 #define     VEPU_REG_INTERRUPT_TIMEOUT_EN		BIT(10)
295 #define     VEPU_REG_INTERRUPT_RESET			BIT(9)
296 #define     VEPU_REG_INTERRUPT_DIS_BIT			BIT(8)
297 #define     VEPU_REG_INTERRUPT_TIMEOUT			BIT(6)
298 #define     VEPU_REG_INTERRUPT_BUFFER_FULL		BIT(5)
299 #define     VEPU_REG_INTERRUPT_BUS_ERROR		BIT(4)
300 #define     VEPU_REG_INTERRUPT_FUSE			BIT(3)
301 #define     VEPU_REG_INTERRUPT_SLICE_READY		BIT(2)
302 #define     VEPU_REG_INTERRUPT_FRAME_READY		BIT(1)
303 #define     VEPU_REG_INTERRUPT_BIT			BIT(0)
304 #define VEPU_REG_DMV_PENALTY_TBL(i)		(0x1E0 + ((i) * 0x4))
305 #define     VEPU_REG_DMV_PENALTY_TABLE_BIT(x, i)        ((x) << (i) * 8)
306 #define VEPU_REG_DMV_Q_PIXEL_PENALTY_TBL(i)	(0x260 + ((i) * 0x4))
307 #define     VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT(x, i)	((x) << (i) * 8)
308 
309 /* vpu decoder register */
310 #define VDPU_REG_DEC_CTRL0			0x0c8 // 50
311 #define     VDPU_REG_REF_BUF_CTRL2_REFBU2_PICID(x)	(((x) & 0x1f) << 25)
312 #define     VDPU_REG_REF_BUF_CTRL2_REFBU2_THR(x)	(((x) & 0xfff) << 13)
313 #define     VDPU_REG_CONFIG_TILED_MODE_LSB		BIT(12)
314 #define     VDPU_REG_CONFIG_DEC_ADV_PRE_DIS		BIT(11)
315 #define     VDPU_REG_CONFIG_DEC_SCMD_DIS		BIT(10)
316 #define     VDPU_REG_DEC_CTRL0_SKIP_MODE		BIT(9)
317 #define     VDPU_REG_DEC_CTRL0_FILTERING_DIS		BIT(8)
318 #define     VDPU_REG_DEC_CTRL0_PIC_FIXED_QUANT		BIT(7)
319 #define     VDPU_REG_CONFIG_DEC_LATENCY(x)		(((x) & 0x3f) << 1)
320 #define     VDPU_REG_CONFIG_TILED_MODE_MSB(x)		BIT(0)
321 #define     VDPU_REG_CONFIG_DEC_OUT_TILED_E		BIT(0)
322 #define VDPU_REG_STREAM_LEN			0x0cc
323 #define     VDPU_REG_DEC_CTRL3_INIT_QP(x)		(((x) & 0x3f) << 25)
324 #define     VDPU_REG_DEC_STREAM_LEN_HI			BIT(24)
325 #define     VDPU_REG_DEC_CTRL3_STREAM_LEN(x)		(((x) & 0xffffff) << 0)
326 #define VDPU_REG_ERROR_CONCEALMENT		0x0d0
327 #define     VDPU_REG_REF_BUF_CTRL2_APF_THRESHOLD(x)	(((x) & 0x3fff) << 17)
328 #define     VDPU_REG_ERR_CONC_STARTMB_X(x)		(((x) & 0x1ff) << 8)
329 #define     VDPU_REG_ERR_CONC_STARTMB_Y(x)		(((x) & 0xff) << 0)
330 #define VDPU_REG_DEC_FORMAT			0x0d4
331 #define     VDPU_REG_DEC_CTRL0_DEC_MODE(x)		(((x) & 0xf) << 0)
332 #define VDPU_REG_DATA_ENDIAN			0x0d8
333 #define     VDPU_REG_CONFIG_DEC_STRENDIAN_E		BIT(5)
334 #define     VDPU_REG_CONFIG_DEC_STRSWAP32_E		BIT(4)
335 #define     VDPU_REG_CONFIG_DEC_OUTSWAP32_E		BIT(3)
336 #define     VDPU_REG_CONFIG_DEC_INSWAP32_E		BIT(2)
337 #define     VDPU_REG_CONFIG_DEC_OUT_ENDIAN		BIT(1)
338 #define     VDPU_REG_CONFIG_DEC_IN_ENDIAN		BIT(0)
339 #define VDPU_REG_INTERRUPT			0x0dc
340 #define     VDPU_REG_INTERRUPT_DEC_TIMEOUT		BIT(13)
341 #define     VDPU_REG_INTERRUPT_DEC_ERROR_INT		BIT(12)
342 #define     VDPU_REG_INTERRUPT_DEC_PIC_INF		BIT(10)
343 #define     VDPU_REG_INTERRUPT_DEC_SLICE_INT		BIT(9)
344 #define     VDPU_REG_INTERRUPT_DEC_ASO_INT		BIT(8)
345 #define     VDPU_REG_INTERRUPT_DEC_BUFFER_INT		BIT(6)
346 #define     VDPU_REG_INTERRUPT_DEC_BUS_INT		BIT(5)
347 #define     VDPU_REG_INTERRUPT_DEC_RDY_INT		BIT(4)
348 #define     VDPU_REG_INTERRUPT_DEC_IRQ_DIS		BIT(1)
349 #define     VDPU_REG_INTERRUPT_DEC_IRQ			BIT(0)
350 #define VDPU_REG_AXI_CTRL			0x0e0
351 #define     VDPU_REG_AXI_DEC_SEL			BIT(23)
352 #define     VDPU_REG_CONFIG_DEC_DATA_DISC_E		BIT(22)
353 #define     VDPU_REG_PARAL_BUS_E(x)			BIT(21)
354 #define     VDPU_REG_CONFIG_DEC_MAX_BURST(x)		(((x) & 0x1f) << 16)
355 #define     VDPU_REG_DEC_CTRL0_DEC_AXI_WR_ID(x)		(((x) & 0xff) << 8)
356 #define     VDPU_REG_CONFIG_DEC_AXI_RD_ID(x)		(((x) & 0xff) << 0)
357 #define VDPU_REG_EN_FLAGS			0x0e4
358 #define     VDPU_REG_AHB_HLOCK_E			BIT(31)
359 #define     VDPU_REG_CACHE_E				BIT(29)
360 #define     VDPU_REG_PREFETCH_SINGLE_CHANNEL_E		BIT(28)
361 #define     VDPU_REG_INTRA_3_CYCLE_ENHANCE		BIT(27)
362 #define     VDPU_REG_INTRA_DOUBLE_SPEED			BIT(26)
363 #define     VDPU_REG_INTER_DOUBLE_SPEED			BIT(25)
364 #define     VDPU_REG_DEC_CTRL3_START_CODE_E		BIT(22)
365 #define     VDPU_REG_DEC_CTRL3_CH_8PIX_ILEAV_E		BIT(21)
366 #define     VDPU_REG_DEC_CTRL0_RLC_MODE_E		BIT(20)
367 #define     VDPU_REG_DEC_CTRL0_DIVX3_E			BIT(19)
368 #define     VDPU_REG_DEC_CTRL0_PJPEG_E			BIT(18)
369 #define     VDPU_REG_DEC_CTRL0_PIC_INTERLACE_E		BIT(17)
370 #define     VDPU_REG_DEC_CTRL0_PIC_FIELDMODE_E		BIT(16)
371 #define     VDPU_REG_DEC_CTRL0_PIC_B_E			BIT(15)
372 #define     VDPU_REG_DEC_CTRL0_PIC_INTER_E		BIT(14)
373 #define     VDPU_REG_DEC_CTRL0_PIC_TOPFIELD_E		BIT(13)
374 #define     VDPU_REG_DEC_CTRL0_FWD_INTERLACE_E		BIT(12)
375 #define     VDPU_REG_DEC_CTRL0_SORENSON_E		BIT(11)
376 #define     VDPU_REG_DEC_CTRL0_WRITE_MVS_E		BIT(10)
377 #define     VDPU_REG_DEC_CTRL0_REF_TOPFIELD_E		BIT(9)
378 #define     VDPU_REG_DEC_CTRL0_REFTOPFIRST_E		BIT(8)
379 #define     VDPU_REG_DEC_CTRL0_SEQ_MBAFF_E		BIT(7)
380 #define     VDPU_REG_DEC_CTRL0_PICORD_COUNT_E		BIT(6)
381 #define     VDPU_REG_CONFIG_DEC_TIMEOUT_E		BIT(5)
382 #define     VDPU_REG_CONFIG_DEC_CLK_GATE_E		BIT(4)
383 #define     VDPU_REG_DEC_CTRL0_DEC_OUT_DIS		BIT(2)
384 #define     VDPU_REG_REF_BUF_CTRL2_REFBU2_BUF_E		BIT(1)
385 #define     VDPU_REG_INTERRUPT_DEC_E			BIT(0)
386 #define VDPU_REG_SOFT_RESET			0x0e8
387 #define VDPU_REG_PRED_FLT			0x0ec
388 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_0_0(x)	(((x) & 0x3ff) << 22)
389 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_0_1(x)	(((x) & 0x3ff) << 12)
390 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_0_2(x)	(((x) & 0x3ff) << 2)
391 #define VDPU_REG_ADDITIONAL_CHROMA_ADDRESS	0x0f0
392 #define VDPU_REG_ADDR_QTABLE			0x0f4
393 #define VDPU_REG_DIRECT_MV_ADDR			0x0f8
394 #define VDPU_REG_ADDR_DST			0x0fc
395 #define VDPU_REG_ADDR_STR			0x100
396 #define VDPU_REG_REFBUF_RELATED			0x104
397 #define VDPU_REG_FWD_PIC(i)			(0x128 + ((i) * 0x4))
398 #define     VDPU_REG_FWD_PIC_PINIT_RLIST_F5(x)		(((x) & 0x1f) << 25)
399 #define     VDPU_REG_FWD_PIC_PINIT_RLIST_F4(x)		(((x) & 0x1f) << 20)
400 #define     VDPU_REG_FWD_PIC_PINIT_RLIST_F3(x)		(((x) & 0x1f) << 15)
401 #define     VDPU_REG_FWD_PIC_PINIT_RLIST_F2(x)		(((x) & 0x1f) << 10)
402 #define     VDPU_REG_FWD_PIC_PINIT_RLIST_F1(x)		(((x) & 0x1f) << 5)
403 #define     VDPU_REG_FWD_PIC_PINIT_RLIST_F0(x)		(((x) & 0x1f) << 0)
404 #define VDPU_REG_REF_PIC(i)			(0x130 + ((i) * 0x4))
405 #define     VDPU_REG_REF_PIC_REFER1_NBR(x)		(((x) & 0xffff) << 16)
406 #define     VDPU_REG_REF_PIC_REFER0_NBR(x)		(((x) & 0xffff) << 0)
407 #define VDPU_REG_H264_ADDR_REF(i)			(0x150 + ((i) * 0x4))
408 #define     VDPU_REG_ADDR_REF_FIELD_E			BIT(1)
409 #define     VDPU_REG_ADDR_REF_TOPC_E			BIT(0)
410 #define VDPU_REG_INITIAL_REF_PIC_LIST0		0x190
411 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_F5(x)	(((x) & 0x1f) << 25)
412 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_F4(x)	(((x) & 0x1f) << 20)
413 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_F3(x)	(((x) & 0x1f) << 15)
414 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_F2(x)	(((x) & 0x1f) << 10)
415 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_F1(x)	(((x) & 0x1f) << 5)
416 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_F0(x)	(((x) & 0x1f) << 0)
417 #define VDPU_REG_INITIAL_REF_PIC_LIST1		0x194
418 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_F11(x)	(((x) & 0x1f) << 25)
419 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_F10(x)	(((x) & 0x1f) << 20)
420 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_F9(x)	(((x) & 0x1f) << 15)
421 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_F8(x)	(((x) & 0x1f) << 10)
422 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_F7(x)	(((x) & 0x1f) << 5)
423 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_F6(x)	(((x) & 0x1f) << 0)
424 #define VDPU_REG_INITIAL_REF_PIC_LIST2		0x198
425 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_F15(x)	(((x) & 0x1f) << 15)
426 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_F14(x)	(((x) & 0x1f) << 10)
427 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_F13(x)	(((x) & 0x1f) << 5)
428 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_F12(x)	(((x) & 0x1f) << 0)
429 #define VDPU_REG_INITIAL_REF_PIC_LIST3		0x19c
430 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_B5(x)	(((x) & 0x1f) << 25)
431 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_B4(x)	(((x) & 0x1f) << 20)
432 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_B3(x)	(((x) & 0x1f) << 15)
433 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_B2(x)	(((x) & 0x1f) << 10)
434 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_B1(x)	(((x) & 0x1f) << 5)
435 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_B0(x)	(((x) & 0x1f) << 0)
436 #define VDPU_REG_INITIAL_REF_PIC_LIST4		0x1a0
437 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_B11(x)	(((x) & 0x1f) << 25)
438 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_B10(x)	(((x) & 0x1f) << 20)
439 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_B9(x)	(((x) & 0x1f) << 15)
440 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_B8(x)	(((x) & 0x1f) << 10)
441 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_B7(x)	(((x) & 0x1f) << 5)
442 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_B6(x)	(((x) & 0x1f) << 0)
443 #define VDPU_REG_INITIAL_REF_PIC_LIST5		0x1a4
444 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_B15(x)	(((x) & 0x1f) << 15)
445 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_B14(x)	(((x) & 0x1f) << 10)
446 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_B13(x)	(((x) & 0x1f) << 5)
447 #define     VDPU_REG_BD_REF_PIC_BINIT_RLIST_B12(x)	(((x) & 0x1f) << 0)
448 #define VDPU_REG_INITIAL_REF_PIC_LIST6		0x1a8
449 #define     VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F3(x)	(((x) & 0x1f) << 15)
450 #define     VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F2(x)	(((x) & 0x1f) << 10)
451 #define     VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F1(x)	(((x) & 0x1f) << 5)
452 #define     VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F0(x)	(((x) & 0x1f) << 0)
453 #define VDPU_REG_LT_REF				0x1ac
454 #define VDPU_REG_VALID_REF			0x1b0
455 #define VDPU_REG_H264_PIC_MB_SIZE		0x1b8
456 #define     VDPU_REG_DEC_CTRL2_CH_QP_OFFSET2(x)		(((x) & 0x1f) << 22)
457 #define     VDPU_REG_DEC_CTRL2_CH_QP_OFFSET(x)		(((x) & 0x1f) << 17)
458 #define     VDPU_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(x)	(((x) & 0xff) << 9)
459 #define     VDPU_REG_DEC_CTRL1_PIC_MB_WIDTH(x)		(((x) & 0x1ff) << 0)
460 #define VDPU_REG_H264_CTRL			0x1bc
461 #define     VDPU_REG_DEC_CTRL4_WEIGHT_BIPR_IDC(x)	(((x) & 0x3) << 16)
462 #define     VDPU_REG_DEC_CTRL1_REF_FRAMES(x)		(((x) & 0x1f) << 0)
463 #define VDPU_REG_CURRENT_FRAME			0x1c0
464 #define     VDPU_REG_DEC_CTRL5_FILT_CTRL_PRES		BIT(31)
465 #define     VDPU_REG_DEC_CTRL5_RDPIC_CNT_PRES		BIT(30)
466 #define     VDPU_REG_DEC_CTRL4_FRAMENUM_LEN(x)		(((x) & 0x1f) << 16)
467 #define     VDPU_REG_DEC_CTRL4_FRAMENUM(x)		(((x) & 0xffff) << 0)
468 #define VDPU_REG_REF_FRAME			0x1c4
469 #define     VDPU_REG_DEC_CTRL5_REFPIC_MK_LEN(x)		(((x) & 0x7ff) << 16)
470 #define     VDPU_REG_DEC_CTRL5_IDR_PIC_ID(x)		(((x) & 0xffff) << 0)
471 #define VDPU_REG_DEC_CTRL6			0x1c8
472 #define     VDPU_REG_DEC_CTRL6_PPS_ID(x)		(((x) & 0xff) << 24)
473 #define     VDPU_REG_DEC_CTRL6_REFIDX1_ACTIVE(x)	(((x) & 0x1f) << 19)
474 #define     VDPU_REG_DEC_CTRL6_REFIDX0_ACTIVE(x)	(((x) & 0x1f) << 14)
475 #define     VDPU_REG_DEC_CTRL6_POC_LENGTH(x)		(((x) & 0xff) << 0)
476 #define VDPU_REG_ENABLE_FLAG			0x1cc
477 #define     VDPU_REG_DEC_CTRL5_IDR_PIC_E		BIT(8)
478 #define     VDPU_REG_DEC_CTRL4_DIR_8X8_INFER_E		BIT(7)
479 #define     VDPU_REG_DEC_CTRL4_BLACKWHITE_E		BIT(6)
480 #define     VDPU_REG_DEC_CTRL4_CABAC_E			BIT(5)
481 #define     VDPU_REG_DEC_CTRL4_WEIGHT_PRED_E		BIT(4)
482 #define     VDPU_REG_DEC_CTRL5_CONST_INTRA_E		BIT(3)
483 #define     VDPU_REG_DEC_CTRL5_8X8TRANS_FLAG_E		BIT(2)
484 #define     VDPU_REG_DEC_CTRL2_TYPE1_QUANT_E		BIT(1)
485 #define     VDPU_REG_DEC_CTRL2_FIELDPIC_FLAG_E		BIT(0)
486 #define VDPU_REG_VP8_PIC_MB_SIZE		0x1e0
487 #define     VDPU_REG_DEC_PIC_MB_WIDTH(x)		(((x) & 0x1ff) << 23)
488 #define	    VDPU_REG_DEC_MB_WIDTH_OFF(x)		(((x) & 0xf) << 19)
489 #define	    VDPU_REG_DEC_PIC_MB_HEIGHT_P(x)		(((x) & 0xff) << 11)
490 #define     VDPU_REG_DEC_MB_HEIGHT_OFF(x)		(((x) & 0xf) << 7)
491 #define     VDPU_REG_DEC_CTRL1_PIC_MB_W_EXT(x)		(((x) & 0x7) << 3)
492 #define     VDPU_REG_DEC_CTRL1_PIC_MB_H_EXT(x)		(((x) & 0x7) << 0)
493 #define VDPU_REG_VP8_DCT_START_BIT		0x1e4
494 #define     VDPU_REG_DEC_CTRL4_DCT1_START_BIT(x)	(((x) & 0x3f) << 26)
495 #define     VDPU_REG_DEC_CTRL4_DCT2_START_BIT(x)	(((x) & 0x3f) << 20)
496 #define     VDPU_REG_DEC_CTRL4_VC1_HEIGHT_EXT		BIT(13)
497 #define     VDPU_REG_DEC_CTRL4_BILIN_MC_E		BIT(12)
498 #define VDPU_REG_VP8_CTRL0			0x1e8
499 #define     VDPU_REG_DEC_CTRL2_STRM_START_BIT(x)	(((x) & 0x3f) << 26)
500 #define     VDPU_REG_DEC_CTRL2_STRM1_START_BIT(x)	(((x) & 0x3f) << 18)
501 #define     VDPU_REG_DEC_CTRL2_BOOLEAN_VALUE(x)		(((x) & 0xff) << 8)
502 #define     VDPU_REG_DEC_CTRL2_BOOLEAN_RANGE(x)		(((x) & 0xff) << 0)
503 #define VDPU_REG_VP8_DATA_VAL			0x1f0
504 #define     VDPU_REG_DEC_CTRL6_COEFFS_PART_AM(x)	(((x) & 0xf) << 24)
505 #define     VDPU_REG_DEC_CTRL6_STREAM1_LEN(x)		(((x) & 0xffffff) << 0)
506 #define VDPU_REG_PRED_FLT7			0x1f4
507 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_5_1(x)	(((x) & 0x3ff) << 22)
508 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_5_2(x)	(((x) & 0x3ff) << 12)
509 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_5_3(x)	(((x) & 0x3ff) << 2)
510 #define VDPU_REG_PRED_FLT8			0x1f8
511 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_6_0(x)	(((x) & 0x3ff) << 22)
512 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_6_1(x)	(((x) & 0x3ff) << 12)
513 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_6_2(x)	(((x) & 0x3ff) << 2)
514 #define VDPU_REG_PRED_FLT9			0x1fc
515 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_6_3(x)	(((x) & 0x3ff) << 22)
516 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_7_0(x)	(((x) & 0x3ff) << 12)
517 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_7_1(x)	(((x) & 0x3ff) << 2)
518 #define VDPU_REG_PRED_FLT10			0x200
519 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_7_2(x)	(((x) & 0x3ff) << 22)
520 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_7_3(x)	(((x) & 0x3ff) << 12)
521 #define     VDPU_REG_BD_REF_PIC_PRED_TAP_2_M1(x)	(((x) & 0x3) << 10)
522 #define     VDPU_REG_BD_REF_PIC_PRED_TAP_2_4(x)		(((x) & 0x3) << 8)
523 #define     VDPU_REG_BD_REF_PIC_PRED_TAP_4_M1(x)	(((x) & 0x3) << 6)
524 #define     VDPU_REG_BD_REF_PIC_PRED_TAP_4_4(x)		(((x) & 0x3) << 4)
525 #define     VDPU_REG_BD_REF_PIC_PRED_TAP_6_M1(x)	(((x) & 0x3) << 2)
526 #define     VDPU_REG_BD_REF_PIC_PRED_TAP_6_4(x)		(((x) & 0x3) << 0)
527 #define VDPU_REG_FILTER_LEVEL			0x204
528 #define     VDPU_REG_REF_PIC_LF_LEVEL_0(x)		(((x) & 0x3f) << 18)
529 #define     VDPU_REG_REF_PIC_LF_LEVEL_1(x)		(((x) & 0x3f) << 12)
530 #define     VDPU_REG_REF_PIC_LF_LEVEL_2(x)		(((x) & 0x3f) << 6)
531 #define     VDPU_REG_REF_PIC_LF_LEVEL_3(x)		(((x) & 0x3f) << 0)
532 #define VDPU_REG_VP8_QUANTER0			0x208
533 #define     VDPU_REG_REF_PIC_QUANT_DELTA_0(x)		(((x) & 0x1f) << 27)
534 #define     VDPU_REG_REF_PIC_QUANT_DELTA_1(x)		(((x) & 0x1f) << 22)
535 #define     VDPU_REG_REF_PIC_QUANT_0(x)			(((x) & 0x7ff) << 11)
536 #define     VDPU_REG_REF_PIC_QUANT_1(x)			(((x) & 0x7ff) << 0)
537 #define VDPU_REG_VP8_ADDR_REF0			0x20c
538 #define VDPU_REG_FILTER_MB_ADJ			0x210
539 #define     VDPU_REG_REF_PIC_FILT_TYPE_E		BIT(31)
540 #define     VDPU_REG_REF_PIC_FILT_SHARPNESS(x)		(((x) & 0x7) << 28)
541 #define     VDPU_REG_FILT_MB_ADJ_0(x)			(((x) & 0x7f) << 21)
542 #define     VDPU_REG_FILT_MB_ADJ_1(x)			(((x) & 0x7f) << 14)
543 #define     VDPU_REG_FILT_MB_ADJ_2(x)			(((x) & 0x7f) << 7)
544 #define     VDPU_REG_FILT_MB_ADJ_3(x)			(((x) & 0x7f) << 0)
545 #define VDPU_REG_FILTER_REF_ADJ			0x214
546 #define     VDPU_REG_REF_PIC_ADJ_0(x)			(((x) & 0x7f) << 21)
547 #define     VDPU_REG_REF_PIC_ADJ_1(x)			(((x) & 0x7f) << 14)
548 #define     VDPU_REG_REF_PIC_ADJ_2(x)			(((x) & 0x7f) << 7)
549 #define     VDPU_REG_REF_PIC_ADJ_3(x)			(((x) & 0x7f) << 0)
550 #define VDPU_REG_VP8_ADDR_REF2_5(i)		(0x218 + ((i) * 0x4))
551 #define     VDPU_REG_VP8_GREF_SIGN_BIAS			BIT(0)
552 #define     VDPU_REG_VP8_AREF_SIGN_BIAS			BIT(0)
553 #define VDPU_REG_VP8_DCT_BASE(i)		(0x230 + ((i) * 0x4))
554 #define VDPU_REG_VP8_ADDR_CTRL_PART		0x244
555 #define VDPU_REG_VP8_ADDR_REF1			0x250
556 #define VDPU_REG_VP8_SEGMENT_VAL		0x254
557 #define     VDPU_REG_FWD_PIC1_SEGMENT_BASE(x)		((x) << 0)
558 #define     VDPU_REG_FWD_PIC1_SEGMENT_UPD_E		BIT(1)
559 #define     VDPU_REG_FWD_PIC1_SEGMENT_E			BIT(0)
560 #define VDPU_REG_VP8_DCT_START_BIT2		0x258
561 #define     VDPU_REG_DEC_CTRL7_DCT3_START_BIT(x)	(((x) & 0x3f) << 24)
562 #define     VDPU_REG_DEC_CTRL7_DCT4_START_BIT(x)	(((x) & 0x3f) << 18)
563 #define     VDPU_REG_DEC_CTRL7_DCT5_START_BIT(x)	(((x) & 0x3f) << 12)
564 #define     VDPU_REG_DEC_CTRL7_DCT6_START_BIT(x)	(((x) & 0x3f) << 6)
565 #define     VDPU_REG_DEC_CTRL7_DCT7_START_BIT(x)	(((x) & 0x3f) << 0)
566 #define VDPU_REG_VP8_QUANTER1			0x25c
567 #define     VDPU_REG_REF_PIC_QUANT_DELTA_2(x)		(((x) & 0x1f) << 27)
568 #define     VDPU_REG_REF_PIC_QUANT_DELTA_3(x)		(((x) & 0x1f) << 22)
569 #define     VDPU_REG_REF_PIC_QUANT_2(x)			(((x) & 0x7ff) << 11)
570 #define     VDPU_REG_REF_PIC_QUANT_3(x)			(((x) & 0x7ff) << 0)
571 #define VDPU_REG_VP8_QUANTER2			0x260
572 #define     VDPU_REG_REF_PIC_QUANT_DELTA_4(x)		(((x) & 0x1f) << 27)
573 #define     VDPU_REG_REF_PIC_QUANT_4(x)			(((x) & 0x7ff) << 11)
574 #define     VDPU_REG_REF_PIC_QUANT_5(x)			(((x) & 0x7ff) << 0)
575 #define VDPU_REG_PRED_FLT1			0x264
576 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_0_3(x)	(((x) & 0x3ff) << 22)
577 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_1_0(x)	(((x) & 0x3ff) << 12)
578 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_1_1(x)	(((x) & 0x3ff) << 2)
579 #define VDPU_REG_PRED_FLT2			0x268
580 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_1_2(x)	(((x) & 0x3ff) << 22)
581 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_1_3(x)	(((x) & 0x3ff) << 12)
582 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_2_0(x)	(((x) & 0x3ff) << 2)
583 #define VDPU_REG_PRED_FLT3			0x26c
584 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_2_1(x)	(((x) & 0x3ff) << 22)
585 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_2_2(x)	(((x) & 0x3ff) << 12)
586 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_2_3(x)	(((x) & 0x3ff) << 2)
587 #define VDPU_REG_PRED_FLT4			0x270
588 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_3_0(x)	(((x) & 0x3ff) << 22)
589 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_3_1(x)	(((x) & 0x3ff) << 12)
590 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_3_2(x)	(((x) & 0x3ff) << 2)
591 #define VDPU_REG_PRED_FLT5			0x274
592 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_3_3(x)	(((x) & 0x3ff) << 22)
593 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_4_0(x)	(((x) & 0x3ff) << 12)
594 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_4_1(x)	(((x) & 0x3ff) << 2)
595 #define VDPU_REG_PRED_FLT6			0x278
596 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_4_2(x)	(((x) & 0x3ff) << 22)
597 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_4_3(x)	(((x) & 0x3ff) << 12)
598 #define     VDPU_REG_PRED_FLT_PRED_BC_TAP_5_0(x)	(((x) & 0x3ff) << 2)
599 
600 #endif /* ROCKCHIP_VPU2_REGS_H_ */
601