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Searched refs:UvdLevel (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvegam_smumgr.c1324 table->UvdLevel[count].MinVoltage = 0; in vegam_populate_smc_uvd_level()
1325 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; in vegam_populate_smc_uvd_level()
1326 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk; in vegam_populate_smc_uvd_level()
1327 table->UvdLevel[count].MinVoltage |= in vegam_populate_smc_uvd_level()
1338 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; in vegam_populate_smc_uvd_level()
1339 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT; in vegam_populate_smc_uvd_level()
1343 table->UvdLevel[count].VclkFrequency, &dividers); in vegam_populate_smc_uvd_level()
1347 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; in vegam_populate_smc_uvd_level()
1350 table->UvdLevel[count].DclkFrequency, &dividers); in vegam_populate_smc_uvd_level()
1354 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider; in vegam_populate_smc_uvd_level()
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H A Dfiji_smumgr.c1568 table->UvdLevel[count].MinVoltage = 0; in fiji_populate_smc_uvd_level()
1569 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; in fiji_populate_smc_uvd_level()
1570 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk; in fiji_populate_smc_uvd_level()
1571 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc * in fiji_populate_smc_uvd_level()
1573 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc - in fiji_populate_smc_uvd_level()
1575 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT; in fiji_populate_smc_uvd_level()
1579 table->UvdLevel[count].VclkFrequency, &dividers); in fiji_populate_smc_uvd_level()
1583 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; in fiji_populate_smc_uvd_level()
1586 table->UvdLevel[count].DclkFrequency, &dividers); in fiji_populate_smc_uvd_level()
1590 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider; in fiji_populate_smc_uvd_level()
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H A Dci_smumgr.c1530 table->UvdLevel[count].VclkFrequency = in ci_populate_smc_uvd_level()
1532 table->UvdLevel[count].DclkFrequency = in ci_populate_smc_uvd_level()
1534 table->UvdLevel[count].MinVddc = in ci_populate_smc_uvd_level()
1536 table->UvdLevel[count].MinVddcPhases = 1; in ci_populate_smc_uvd_level()
1539 table->UvdLevel[count].VclkFrequency, &dividers); in ci_populate_smc_uvd_level()
1543 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_uvd_level()
1546 table->UvdLevel[count].DclkFrequency, &dividers); in ci_populate_smc_uvd_level()
1550 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_uvd_level()
1551 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency); in ci_populate_smc_uvd_level()
1552 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency); in ci_populate_smc_uvd_level()
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/linux/drivers/gpu/drm/radeon/
H A Dsmu7_fusion.h226 SMU7_Fusion_UvdLevel UvdLevel[SMU7_MAX_LEVELS_UVD]; member
H A Dsmu7_discrete.h314 SMU7_Discrete_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD]; member
H A Dkv_dpm.c721 offsetof(SMU7_Fusion_DpmTable, UvdLevel), in kv_populate_uvd_table()
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu7_fusion.h226 SMU7_Fusion_UvdLevel UvdLevel[SMU7_MAX_LEVELS_UVD]; member
H A Dsmu7_discrete.h328 SMU7_Discrete_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD]; member
H A Dsmu72_discrete.h270 SMU72_Discrete_UvdLevel UvdLevel[SMU72_MAX_LEVELS_UVD]; member
H A Dsmu74_discrete.h287 SMU74_Discrete_UvdLevel UvdLevel[SMU74_MAX_LEVELS_UVD]; member
H A Dsmu73_discrete.h244 SMU73_Discrete_UvdLevel UvdLevel[SMU73_MAX_LEVELS_UVD]; member
H A Dsmu75_discrete.h292 SMU75_Discrete_UvdLevel UvdLevel [SMU75_MAX_LEVELS_UVD]; member