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Searched refs:UVD_SUVD_CGC_CTRL__SRE_MODE_MASK (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h255 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK … macro
H A Duvd_5_0_sh_mask.h785 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1 macro
H A Duvd_6_0_sh_mask.h779 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h547 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK … macro
H A Dvcn_2_5_sh_mask.h2180 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK … macro
H A Dvcn_2_0_0_sh_mask.h3306 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3851 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2937 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK … macro
H A Dvcn_5_0_0_sh_mask.h2398 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK … macro
H A Dvcn_4_0_5_sh_mask.h2897 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK … macro
H A Dvcn_4_0_0_sh_mask.h2865 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK … macro
H A Dvcn_4_0_3_sh_mask.h2865 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v5_0.c716 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | in uvd_v5_0_set_sw_clock_gating()
H A Dvcn_v4_0_5.c768 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v4_0_5_disable_clock_gating_dpg_mode()
887 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v4_0_5_start_dpg_mode()
H A Dvcn_v4_0_3.c707 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v4_0_3_disable_clock_gating_dpg_mode()
812 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v4_0_3_start_dpg_mode()
H A Dvcn_v1_0.c603 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v1_0_disable_clock_gating()
676 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v1_0_enable_clock_gating()
H A Dvcn_v2_0.c630 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v2_0_disable_clock_gating()
741 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v2_0_enable_clock_gating()
H A Dvcn_v2_5.c864 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
975 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v2_5_start_dpg_mode()
H A Dvcn_v4_0.c841 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v4_0_disable_clock_gating_dpg_mode()
960 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
H A Dvcn_v3_0.c882 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v3_0_clock_gating_dpg_mode()
1002 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v3_0_start_dpg_mode()
H A Duvd_v6_0.c1374 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | in uvd_v6_0_set_sw_clock_gating()