UVD_CGC_CTRL__UDEC_RE_MODE_MASK (reference) in projects: linux

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Searched refs:UVD_CGC_CTRL__UDEC_RE_MODE_MASK (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A D	uvd_7_0_sh_mask.h	`444 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK … macro`
H A D	uvd_3_1_sh_mask.h	`227 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 macro`
H A D	uvd_4_2_sh_mask.h	`227 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 macro`
H A D	uvd_4_0_sh_mask.h	`72 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L macro`
H A D	uvd_5_0_sh_mask.h	`249 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 macro`
H A D	uvd_6_0_sh_mask.h	`251 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 macro`
/linux/drivers/gpu/drm/amd/amdgpu/
H A D	vcn_v4_0_5.c	`685 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v4_0_5_disable_clock_gating() 770 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK \| in vcn_v4_0_5_disable_clock_gating_dpg_mode() 828 data \|= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v4_0_5_enable_clock_gating()`
H A D	vcn_v2_0.c	`575 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v2_0_disable_clock_gating() 651 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK \| in vcn_v2_0_clock_gating_dpg_mode() 712 data \|= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v2_0_enable_clock_gating()`
H A D	vcn_v4_0.c	`749 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v4_0_disable_clock_gating() 834 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK \| in vcn_v4_0_disable_clock_gating_dpg_mode() 892 data \|= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v4_0_enable_clock_gating()`
H A D	vcn_v1_0.c	`547 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v1_0_disable_clock_gating() 647 data \|= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v1_0_enable_clock_gating() 705 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK \| in vcn_v1_0_clock_gating_dpg_mode()`
H A D	uvd_v5_0.c	`696 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK \| in uvd_v5_0_set_sw_clock_gating()`
H A D	vcn_v2_5.c	`665 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v2_5_disable_clock_gating() 742 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK \| in vcn_v2_5_clock_gating_dpg_mode() 804 data \|= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v2_5_enable_clock_gating()`
H A D	vcn_v3_0.c	`784 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v3_0_disable_clock_gating() 883 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK \| in vcn_v3_0_clock_gating_dpg_mode() 942 data \|= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v3_0_enable_clock_gating()`
H A D	uvd_v6_0.c	`1353 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK \| in uvd_v6_0_set_sw_clock_gating()`
H A D	uvd_v7_0.c	`1635 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK \|`
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A D	vcn_1_0_sh_mask.h	`937 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK … macro`
H A D	vcn_2_5_sh_mask.h	`2005 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK … macro`
H A D	vcn_2_0_0_sh_mask.h	`1956 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK … macro`
H A D	vcn_2_6_0_sh_mask.h	`3676 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK … macro`
H A D	vcn_3_0_0_sh_mask.h	`2735 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK … macro`
H A D	vcn_5_0_0_sh_mask.h	`113 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK … macro`
H A D	vcn_4_0_5_sh_mask.h	`109 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK … macro`
H A D	vcn_4_0_0_sh_mask.h	`113 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK … macro`
H A D	vcn_4_0_3_sh_mask.h	`113 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK … macro`