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Searched refs:UVD_CGC_CTRL__REGS_MODE_MASK (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h452 #define UVD_CGC_CTRL__REGS_MODE_MASK … macro
H A Duvd_3_1_sh_mask.h243 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 macro
H A Duvd_4_2_sh_mask.h243 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 macro
H A Duvd_4_0_sh_mask.h56 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L macro
H A Duvd_5_0_sh_mask.h265 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 macro
H A Duvd_6_0_sh_mask.h267 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c691 | UVD_CGC_CTRL__REGS_MODE_MASK in vcn_v4_0_5_disable_clock_gating()
776 UVD_CGC_CTRL__REGS_MODE_MASK | in vcn_v4_0_5_disable_clock_gating_dpg_mode()
834 | UVD_CGC_CTRL__REGS_MODE_MASK in vcn_v4_0_5_enable_clock_gating()
H A Dvcn_v4_0_3.c630 | UVD_CGC_CTRL__REGS_MODE_MASK in vcn_v4_0_3_disable_clock_gating()
702 UVD_CGC_CTRL__REGS_MODE_MASK | in vcn_v4_0_3_disable_clock_gating_dpg_mode()
757 | UVD_CGC_CTRL__REGS_MODE_MASK in vcn_v4_0_3_enable_clock_gating()
H A Dvcn_v1_0.c555 | UVD_CGC_CTRL__REGS_MODE_MASK in vcn_v1_0_disable_clock_gating()
655 | UVD_CGC_CTRL__REGS_MODE_MASK in vcn_v1_0_enable_clock_gating()
713 UVD_CGC_CTRL__REGS_MODE_MASK | in vcn_v1_0_clock_gating_dpg_mode()
H A Dvcn_v2_0.c581 | UVD_CGC_CTRL__REGS_MODE_MASK in vcn_v2_0_disable_clock_gating()
657 UVD_CGC_CTRL__REGS_MODE_MASK | in vcn_v2_0_clock_gating_dpg_mode()
718 | UVD_CGC_CTRL__REGS_MODE_MASK in vcn_v2_0_enable_clock_gating()
H A Duvd_v5_0.c703 UVD_CGC_CTRL__REGS_MODE_MASK | in uvd_v5_0_set_sw_clock_gating()
H A Dvcn_v2_5.c671 | UVD_CGC_CTRL__REGS_MODE_MASK in vcn_v2_5_disable_clock_gating()
748 UVD_CGC_CTRL__REGS_MODE_MASK | in vcn_v2_5_clock_gating_dpg_mode()
810 | UVD_CGC_CTRL__REGS_MODE_MASK in vcn_v2_5_enable_clock_gating()
H A Dvcn_v4_0.c764 | UVD_CGC_CTRL__REGS_MODE_MASK in vcn_v4_0_disable_clock_gating()
849 UVD_CGC_CTRL__REGS_MODE_MASK | in vcn_v4_0_disable_clock_gating_dpg_mode()
907 | UVD_CGC_CTRL__REGS_MODE_MASK in vcn_v4_0_enable_clock_gating()
H A Dvcn_v3_0.c790 | UVD_CGC_CTRL__REGS_MODE_MASK in vcn_v3_0_disable_clock_gating()
889 UVD_CGC_CTRL__REGS_MODE_MASK | in vcn_v3_0_clock_gating_dpg_mode()
948 | UVD_CGC_CTRL__REGS_MODE_MASK in vcn_v3_0_enable_clock_gating()
H A Duvd_v6_0.c1360 UVD_CGC_CTRL__REGS_MODE_MASK | in uvd_v6_0_set_sw_clock_gating()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h945 #define UVD_CGC_CTRL__REGS_MODE_MASK … macro
H A Dvcn_2_5_sh_mask.h2013 #define UVD_CGC_CTRL__REGS_MODE_MASK … macro
H A Dvcn_2_0_0_sh_mask.h1964 #define UVD_CGC_CTRL__REGS_MODE_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3684 #define UVD_CGC_CTRL__REGS_MODE_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2743 #define UVD_CGC_CTRL__REGS_MODE_MASK … macro
H A Dvcn_5_0_0_sh_mask.h121 #define UVD_CGC_CTRL__REGS_MODE_MASK … macro
H A Dvcn_4_0_5_sh_mask.h117 #define UVD_CGC_CTRL__REGS_MODE_MASK … macro
H A Dvcn_4_0_0_sh_mask.h121 #define UVD_CGC_CTRL__REGS_MODE_MASK … macro
H A Dvcn_4_0_3_sh_mask.h121 #define UVD_CGC_CTRL__REGS_MODE_MASK … macro