UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK (reference) in projects: linux

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Searched refs:UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK (Results 1 – 25 of 27) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A D	uvd_v5_0.c	`692 data \|= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK \| in uvd_v5_0_set_sw_clock_gating() 779 data \|= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v5_0_enable_mgcg() 788 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v5_0_enable_mgcg() 856 if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) in uvd_v5_0_get_clockgating_state()`
H A D	uvd_v4_2.c	`620 data \|= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v4_2_enable_mgcg() 629 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v4_2_enable_mgcg() 644 tmp \|= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK \| in uvd_v4_2_set_dcm()`
H A D	uvd_v3_1.c	`215 tmp \|= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK \| in uvd_v3_1_set_dcm() 606 data \|= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v3_1_enable_mgcg() 615 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v3_1_enable_mgcg()`
H A D	uvd_v6_0.c	`1349 data \|= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK \| in uvd_v6_0_set_sw_clock_gating() 1439 data \|= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v6_0_enable_mgcg() 1448 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v6_0_enable_mgcg() 1521 if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) in uvd_v6_0_get_clockgating_state()`
H A D	uvd_v7_0.c	`868 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0); in uvd_v7_0_sriov_start() 981 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK); in uvd_v7_0_start() 1631 data \|= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK \|`
H A D	vcn_v4_0_5.c	`654 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in vcn_v4_0_5_disable_clock_gating()`
H A D	vcn_v4_0_3.c	`577 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in vcn_v4_0_3_disable_clock_gating()`
H A D	vcn_v2_0.c	`546 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in vcn_v2_0_disable_clock_gating()`
H A D	vcn_v4_0.c	`718 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in vcn_v4_0_disable_clock_gating()`
H A D	vcn_v1_0.c	`517 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in vcn_v1_0_disable_clock_gating()`
H A D	vcn_v2_5.c	`633 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in vcn_v2_5_disable_clock_gating()`
H A D	vcn_v3_0.c	`752 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in vcn_v3_0_disable_clock_gating()`
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A D	uvd_7_0_sh_mask.h	`441 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK … macro`
H A D	uvd_3_1_sh_mask.h	`221 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 macro`
H A D	uvd_4_2_sh_mask.h	`221 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 macro`
H A D	uvd_4_0_sh_mask.h	`36 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L macro`
H A D	uvd_5_0_sh_mask.h	`241 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 macro`
H A D	uvd_6_0_sh_mask.h	`243 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 macro`
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A D	vcn_1_0_sh_mask.h	`934 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK … macro`
H A D	vcn_2_5_sh_mask.h	`2002 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK … macro`
H A D	vcn_2_0_0_sh_mask.h	`1953 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK … macro`
H A D	vcn_2_6_0_sh_mask.h	`3673 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK … macro`
H A D	vcn_3_0_0_sh_mask.h	`2732 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK … macro`
H A D	vcn_5_0_0_sh_mask.h	`110 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK … macro`
H A D	vcn_4_0_5_sh_mask.h	`106 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK … macro`