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Searched refs:UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h442 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK … macro
H A Duvd_3_1_sh_mask.h223 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c macro
H A Duvd_4_2_sh_mask.h223 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c macro
H A Duvd_4_0_sh_mask.h32 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL macro
H A Duvd_5_0_sh_mask.h245 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c macro
H A Duvd_6_0_sh_mask.h247 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v4_2.c643 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); in uvd_v4_2_set_dcm()
H A Duvd_v3_1.c214 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); in uvd_v3_1_set_dcm()
H A Duvd_v5_0.c689 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); in uvd_v5_0_set_sw_clock_gating()
H A Duvd_v6_0.c1346 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); in uvd_v6_0_set_sw_clock_gating()
H A Duvd_v7_0.c1623 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h935 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK … macro
H A Dvcn_2_5_sh_mask.h2003 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK … macro
H A Dvcn_2_0_0_sh_mask.h1954 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3674 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2733 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK … macro
H A Dvcn_5_0_0_sh_mask.h111 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK … macro
H A Dvcn_4_0_5_sh_mask.h107 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK … macro
H A Dvcn_4_0_0_sh_mask.h111 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK … macro
H A Dvcn_4_0_3_sh_mask.h111 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK … macro