1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * dwc3-am62.c - TI specific Glue layer for AM62 DWC3 USB Controller 4 * 5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com 6 */ 7 8 #include <linux/init.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/of.h> 14 #include <linux/of_platform.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/clk.h> 17 #include <linux/regmap.h> 18 #include <linux/pinctrl/consumer.h> 19 20 #include "core.h" 21 22 /* USB WRAPPER register offsets */ 23 #define USBSS_PID 0x0 24 #define USBSS_OVERCURRENT_CTRL 0x4 25 #define USBSS_PHY_CONFIG 0x8 26 #define USBSS_PHY_TEST 0xc 27 #define USBSS_CORE_STAT 0x14 28 #define USBSS_HOST_VBUS_CTRL 0x18 29 #define USBSS_MODE_CONTROL 0x1c 30 #define USBSS_WAKEUP_CONFIG 0x30 31 #define USBSS_WAKEUP_STAT 0x34 32 #define USBSS_OVERRIDE_CONFIG 0x38 33 #define USBSS_IRQ_MISC_STATUS_RAW 0x430 34 #define USBSS_IRQ_MISC_STATUS 0x434 35 #define USBSS_IRQ_MISC_ENABLE_SET 0x438 36 #define USBSS_IRQ_MISC_ENABLE_CLR 0x43c 37 #define USBSS_IRQ_MISC_EOI 0x440 38 #define USBSS_INTR_TEST 0x490 39 #define USBSS_VBUS_FILTER 0x614 40 #define USBSS_VBUS_STAT 0x618 41 #define USBSS_DEBUG_CFG 0x708 42 #define USBSS_DEBUG_DATA 0x70c 43 #define USBSS_HOST_HUB_CTRL 0x714 44 45 /* PHY CONFIG register bits */ 46 #define USBSS_PHY_VBUS_SEL_MASK GENMASK(2, 1) 47 #define USBSS_PHY_VBUS_SEL_SHIFT 1 48 #define USBSS_PHY_LANE_REVERSE BIT(0) 49 50 /* CORE STAT register bits */ 51 #define USBSS_CORE_OPERATIONAL_MODE_MASK GENMASK(13, 12) 52 #define USBSS_CORE_OPERATIONAL_MODE_SHIFT 12 53 54 /* MODE CONTROL register bits */ 55 #define USBSS_MODE_VALID BIT(0) 56 57 /* WAKEUP CONFIG register bits */ 58 #define USBSS_WAKEUP_CFG_OVERCURRENT_EN BIT(3) 59 #define USBSS_WAKEUP_CFG_LINESTATE_EN BIT(2) 60 #define USBSS_WAKEUP_CFG_SESSVALID_EN BIT(1) 61 #define USBSS_WAKEUP_CFG_VBUSVALID_EN BIT(0) 62 63 #define USBSS_WAKEUP_CFG_ALL (USBSS_WAKEUP_CFG_VBUSVALID_EN | \ 64 USBSS_WAKEUP_CFG_SESSVALID_EN | \ 65 USBSS_WAKEUP_CFG_LINESTATE_EN | \ 66 USBSS_WAKEUP_CFG_OVERCURRENT_EN) 67 68 #define USBSS_WAKEUP_CFG_NONE 0 69 70 /* WAKEUP STAT register bits */ 71 #define USBSS_WAKEUP_STAT_OVERCURRENT BIT(4) 72 #define USBSS_WAKEUP_STAT_LINESTATE BIT(3) 73 #define USBSS_WAKEUP_STAT_SESSVALID BIT(2) 74 #define USBSS_WAKEUP_STAT_VBUSVALID BIT(1) 75 #define USBSS_WAKEUP_STAT_CLR BIT(0) 76 77 /* IRQ_MISC_STATUS_RAW register bits */ 78 #define USBSS_IRQ_MISC_RAW_VBUSVALID BIT(22) 79 #define USBSS_IRQ_MISC_RAW_SESSVALID BIT(20) 80 81 /* IRQ_MISC_STATUS register bits */ 82 #define USBSS_IRQ_MISC_VBUSVALID BIT(22) 83 #define USBSS_IRQ_MISC_SESSVALID BIT(20) 84 85 /* IRQ_MISC_ENABLE_SET register bits */ 86 #define USBSS_IRQ_MISC_ENABLE_SET_VBUSVALID BIT(22) 87 #define USBSS_IRQ_MISC_ENABLE_SET_SESSVALID BIT(20) 88 89 /* IRQ_MISC_ENABLE_CLR register bits */ 90 #define USBSS_IRQ_MISC_ENABLE_CLR_VBUSVALID BIT(22) 91 #define USBSS_IRQ_MISC_ENABLE_CLR_SESSVALID BIT(20) 92 93 /* IRQ_MISC_EOI register bits */ 94 #define USBSS_IRQ_MISC_EOI_VECTOR BIT(0) 95 96 /* VBUS_STAT register bits */ 97 #define USBSS_VBUS_STAT_SESSVALID BIT(2) 98 #define USBSS_VBUS_STAT_VBUSVALID BIT(0) 99 100 /* USB_PHY_CTRL register bits in CTRL_MMR */ 101 #define PHY_CORE_VOLTAGE_MASK BIT(31) 102 #define PHY_PLL_REFCLK_MASK GENMASK(3, 0) 103 104 /* USB PHY2 register offsets */ 105 #define USB_PHY_PLL_REG12 0x130 106 #define USB_PHY_PLL_LDO_REF_EN BIT(5) 107 #define USB_PHY_PLL_LDO_REF_EN_EN BIT(4) 108 109 #define DWC3_AM62_AUTOSUSPEND_DELAY 100 110 111 #define USBSS_DEBUG_CFG_OFF 0x0 112 #define USBSS_DEBUG_CFG_DISABLED 0x7 113 114 struct dwc3_am62 { 115 struct device *dev; 116 void __iomem *usbss; 117 struct clk *usb2_refclk; 118 int rate_code; 119 struct regmap *syscon; 120 unsigned int offset; 121 unsigned int vbus_divider; 122 u32 wakeup_stat; 123 void __iomem *phy_regs; 124 }; 125 126 static const int dwc3_ti_rate_table[] = { /* in KHZ */ 127 9600, 128 10000, 129 12000, 130 19200, 131 20000, 132 24000, 133 25000, 134 26000, 135 38400, 136 40000, 137 58000, 138 50000, 139 52000, 140 }; 141 142 static inline u32 dwc3_ti_readl(struct dwc3_am62 *am62, u32 offset) 143 { 144 return readl((am62->usbss) + offset); 145 } 146 147 static inline void dwc3_ti_writel(struct dwc3_am62 *am62, u32 offset, u32 value) 148 { 149 writel(value, (am62->usbss) + offset); 150 } 151 152 static int phy_syscon_pll_refclk(struct dwc3_am62 *am62) 153 { 154 struct device *dev = am62->dev; 155 struct device_node *node = dev->of_node; 156 struct of_phandle_args args; 157 struct regmap *syscon; 158 int ret; 159 160 syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-phy-pll-refclk"); 161 if (IS_ERR(syscon)) { 162 dev_err(dev, "unable to get ti,syscon-phy-pll-refclk regmap\n"); 163 return PTR_ERR(syscon); 164 } 165 166 am62->syscon = syscon; 167 168 ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-phy-pll-refclk", 1, 169 0, &args); 170 if (ret) 171 return ret; 172 173 of_node_put(args.np); 174 am62->offset = args.args[0]; 175 176 /* Core voltage. PHY_CORE_VOLTAGE bit Recommended to be 0 always */ 177 ret = regmap_update_bits(am62->syscon, am62->offset, PHY_CORE_VOLTAGE_MASK, 0); 178 if (ret) { 179 dev_err(dev, "failed to set phy core voltage\n"); 180 return ret; 181 } 182 183 ret = regmap_update_bits(am62->syscon, am62->offset, PHY_PLL_REFCLK_MASK, am62->rate_code); 184 if (ret) { 185 dev_err(dev, "failed to set phy pll reference clock rate\n"); 186 return ret; 187 } 188 189 return 0; 190 } 191 192 static int dwc3_ti_init(struct dwc3_am62 *am62) 193 { 194 int ret; 195 u32 reg; 196 197 /* Read the syscon property and set the rate code */ 198 ret = phy_syscon_pll_refclk(am62); 199 if (ret) 200 return ret; 201 202 /* Workaround Errata i2409 */ 203 if (am62->phy_regs) { 204 reg = readl(am62->phy_regs + USB_PHY_PLL_REG12); 205 reg |= USB_PHY_PLL_LDO_REF_EN | USB_PHY_PLL_LDO_REF_EN_EN; 206 writel(reg, am62->phy_regs + USB_PHY_PLL_REG12); 207 } 208 209 /* VBUS divider select */ 210 reg = dwc3_ti_readl(am62, USBSS_PHY_CONFIG); 211 if (am62->vbus_divider) 212 reg |= 1 << USBSS_PHY_VBUS_SEL_SHIFT; 213 214 dwc3_ti_writel(am62, USBSS_PHY_CONFIG, reg); 215 216 clk_prepare_enable(am62->usb2_refclk); 217 218 /* Set mode valid bit to indicate role is valid */ 219 reg = dwc3_ti_readl(am62, USBSS_MODE_CONTROL); 220 reg |= USBSS_MODE_VALID; 221 dwc3_ti_writel(am62, USBSS_MODE_CONTROL, reg); 222 223 return 0; 224 } 225 226 static int dwc3_ti_probe(struct platform_device *pdev) 227 { 228 struct device *dev = &pdev->dev; 229 struct device_node *node = pdev->dev.of_node; 230 struct dwc3_am62 *am62; 231 unsigned long rate; 232 int i, ret; 233 234 am62 = devm_kzalloc(dev, sizeof(*am62), GFP_KERNEL); 235 if (!am62) 236 return -ENOMEM; 237 238 am62->dev = dev; 239 platform_set_drvdata(pdev, am62); 240 241 am62->usbss = devm_platform_ioremap_resource(pdev, 0); 242 if (IS_ERR(am62->usbss)) { 243 dev_err(dev, "can't map IOMEM resource\n"); 244 return PTR_ERR(am62->usbss); 245 } 246 247 am62->usb2_refclk = devm_clk_get(dev, "ref"); 248 if (IS_ERR(am62->usb2_refclk)) { 249 dev_err(dev, "can't get usb2_refclk\n"); 250 return PTR_ERR(am62->usb2_refclk); 251 } 252 253 /* Calculate the rate code */ 254 rate = clk_get_rate(am62->usb2_refclk); 255 rate /= 1000; // To KHz 256 for (i = 0; i < ARRAY_SIZE(dwc3_ti_rate_table); i++) { 257 if (dwc3_ti_rate_table[i] == rate) 258 break; 259 } 260 261 if (i == ARRAY_SIZE(dwc3_ti_rate_table)) { 262 dev_err(dev, "unsupported usb2_refclk rate: %lu KHz\n", rate); 263 return -EINVAL; 264 } 265 266 am62->rate_code = i; 267 268 am62->phy_regs = devm_platform_ioremap_resource(pdev, 1); 269 if (IS_ERR(am62->phy_regs)) { 270 dev_err(dev, "can't map PHY IOMEM resource. Won't apply i2409 fix.\n"); 271 am62->phy_regs = NULL; 272 } 273 274 am62->vbus_divider = device_property_read_bool(dev, "ti,vbus-divider"); 275 276 ret = dwc3_ti_init(am62); 277 if (ret) 278 return ret; 279 280 pm_runtime_set_active(dev); 281 pm_runtime_enable(dev); 282 /* 283 * Don't ignore its dependencies with its children 284 */ 285 pm_suspend_ignore_children(dev, false); 286 pm_runtime_get_noresume(dev); 287 288 ret = of_platform_populate(node, NULL, NULL, dev); 289 if (ret) { 290 dev_err(dev, "failed to create dwc3 core: %d\n", ret); 291 goto err_pm_disable; 292 } 293 294 /* Device has capability to wakeup system from sleep */ 295 device_set_wakeup_capable(dev, true); 296 ret = device_wakeup_enable(dev); 297 if (ret) 298 dev_err(dev, "couldn't enable device as a wakeup source: %d\n", ret); 299 300 /* Setting up autosuspend */ 301 pm_runtime_set_autosuspend_delay(dev, DWC3_AM62_AUTOSUSPEND_DELAY); 302 pm_runtime_use_autosuspend(dev); 303 pm_runtime_mark_last_busy(dev); 304 pm_runtime_put_autosuspend(dev); 305 return 0; 306 307 err_pm_disable: 308 clk_disable_unprepare(am62->usb2_refclk); 309 pm_runtime_disable(dev); 310 pm_runtime_set_suspended(dev); 311 return ret; 312 } 313 314 static void dwc3_ti_remove(struct platform_device *pdev) 315 { 316 struct device *dev = &pdev->dev; 317 struct dwc3_am62 *am62 = platform_get_drvdata(pdev); 318 u32 reg; 319 320 pm_runtime_get_sync(dev); 321 device_init_wakeup(dev, false); 322 of_platform_depopulate(dev); 323 324 /* Clear mode valid bit */ 325 reg = dwc3_ti_readl(am62, USBSS_MODE_CONTROL); 326 reg &= ~USBSS_MODE_VALID; 327 dwc3_ti_writel(am62, USBSS_MODE_CONTROL, reg); 328 329 pm_runtime_put_sync(dev); 330 pm_runtime_disable(dev); 331 pm_runtime_dont_use_autosuspend(dev); 332 pm_runtime_set_suspended(dev); 333 } 334 335 #ifdef CONFIG_PM 336 static int dwc3_ti_suspend_common(struct device *dev) 337 { 338 struct dwc3_am62 *am62 = dev_get_drvdata(dev); 339 u32 reg, current_prtcap_dir; 340 341 if (device_may_wakeup(dev)) { 342 reg = dwc3_ti_readl(am62, USBSS_CORE_STAT); 343 current_prtcap_dir = (reg & USBSS_CORE_OPERATIONAL_MODE_MASK) 344 >> USBSS_CORE_OPERATIONAL_MODE_SHIFT; 345 /* Set wakeup config enable bits */ 346 reg = dwc3_ti_readl(am62, USBSS_WAKEUP_CONFIG); 347 if (current_prtcap_dir == DWC3_GCTL_PRTCAP_HOST) { 348 reg = USBSS_WAKEUP_CFG_LINESTATE_EN | USBSS_WAKEUP_CFG_OVERCURRENT_EN; 349 } else { 350 reg = USBSS_WAKEUP_CFG_VBUSVALID_EN | USBSS_WAKEUP_CFG_SESSVALID_EN; 351 /* 352 * Enable LINESTATE wake up only if connected to bus 353 * and in U2/L3 state else it causes spurious wake-up. 354 */ 355 } 356 dwc3_ti_writel(am62, USBSS_WAKEUP_CONFIG, reg); 357 /* clear wakeup status so we know what caused the wake up */ 358 dwc3_ti_writel(am62, USBSS_WAKEUP_STAT, USBSS_WAKEUP_STAT_CLR); 359 } 360 361 /* just to track if module resets on suspend */ 362 dwc3_ti_writel(am62, USBSS_DEBUG_CFG, USBSS_DEBUG_CFG_DISABLED); 363 364 clk_disable_unprepare(am62->usb2_refclk); 365 366 return 0; 367 } 368 369 static int dwc3_ti_resume_common(struct device *dev) 370 { 371 struct dwc3_am62 *am62 = dev_get_drvdata(dev); 372 u32 reg; 373 374 reg = dwc3_ti_readl(am62, USBSS_DEBUG_CFG); 375 if (reg != USBSS_DEBUG_CFG_DISABLED) { 376 /* lost power/context */ 377 dwc3_ti_init(am62); 378 } else { 379 dwc3_ti_writel(am62, USBSS_DEBUG_CFG, USBSS_DEBUG_CFG_OFF); 380 clk_prepare_enable(am62->usb2_refclk); 381 } 382 383 if (device_may_wakeup(dev)) { 384 /* Clear wakeup config enable bits */ 385 dwc3_ti_writel(am62, USBSS_WAKEUP_CONFIG, USBSS_WAKEUP_CFG_NONE); 386 } 387 388 reg = dwc3_ti_readl(am62, USBSS_WAKEUP_STAT); 389 am62->wakeup_stat = reg; 390 391 return 0; 392 } 393 394 static UNIVERSAL_DEV_PM_OPS(dwc3_ti_pm_ops, dwc3_ti_suspend_common, 395 dwc3_ti_resume_common, NULL); 396 397 #define DEV_PM_OPS (&dwc3_ti_pm_ops) 398 #else 399 #define DEV_PM_OPS NULL 400 #endif /* CONFIG_PM */ 401 402 static const struct of_device_id dwc3_ti_of_match[] = { 403 { .compatible = "ti,am62-usb"}, 404 {}, 405 }; 406 MODULE_DEVICE_TABLE(of, dwc3_ti_of_match); 407 408 static struct platform_driver dwc3_ti_driver = { 409 .probe = dwc3_ti_probe, 410 .remove = dwc3_ti_remove, 411 .driver = { 412 .name = "dwc3-am62", 413 .pm = DEV_PM_OPS, 414 .of_match_table = dwc3_ti_of_match, 415 }, 416 }; 417 418 module_platform_driver(dwc3_ti_driver); 419 420 MODULE_ALIAS("platform:dwc3-am62"); 421 MODULE_AUTHOR("Aswath Govindraju <a-govindraju@ti.com>"); 422 MODULE_LICENSE("GPL"); 423 MODULE_DESCRIPTION("DesignWare USB3 TI Glue Layer"); 424