1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas USBF USB Function driver
4 *
5 * Copyright 2022 Schneider Electric
6 * Author: Herve Codina <herve.codina@bootlin.com>
7 */
8
9 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/interrupt.h>
12 #include <linux/iopoll.h>
13 #include <linux/kernel.h>
14 #include <linux/kfifo.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/types.h>
19 #include <linux/usb/composite.h>
20 #include <linux/usb/gadget.h>
21 #include <linux/usb/role.h>
22
23 #define USBF_NUM_ENDPOINTS 16
24 #define USBF_EP0_MAX_PCKT_SIZE 64
25
26 /* EPC registers */
27 #define USBF_REG_USB_CONTROL 0x000
28 #define USBF_USB_PUE2 BIT(2)
29 #define USBF_USB_CONNECTB BIT(3)
30 #define USBF_USB_DEFAULT BIT(4)
31 #define USBF_USB_CONF BIT(5)
32 #define USBF_USB_SUSPEND BIT(6)
33 #define USBF_USB_RSUM_IN BIT(7)
34 #define USBF_USB_SOF_RCV BIT(8)
35 #define USBF_USB_FORCEFS BIT(9)
36 #define USBF_USB_INT_SEL BIT(10)
37 #define USBF_USB_SOF_CLK_MODE BIT(11)
38
39 #define USBF_REG_USB_STATUS 0x004
40 #define USBF_USB_RSUM_OUT BIT(1)
41 #define USBF_USB_SPND_OUT BIT(2)
42 #define USBF_USB_USB_RST BIT(3)
43 #define USBF_USB_DEFAULT_ST BIT(4)
44 #define USBF_USB_CONF_ST BIT(5)
45 #define USBF_USB_SPEED_MODE BIT(6)
46 #define USBF_USB_SOF_DELAY_STATUS BIT(31)
47
48 #define USBF_REG_USB_ADDRESS 0x008
49 #define USBF_USB_SOF_STATUS BIT(15)
50 #define USBF_USB_SET_USB_ADDR(_a) ((_a) << 16)
51 #define USBF_USB_GET_FRAME(_r) ((_r) & 0x7FF)
52
53 #define USBF_REG_SETUP_DATA0 0x018
54 #define USBF_REG_SETUP_DATA1 0x01C
55 #define USBF_REG_USB_INT_STA 0x020
56 #define USBF_USB_RSUM_INT BIT(1)
57 #define USBF_USB_SPND_INT BIT(2)
58 #define USBF_USB_USB_RST_INT BIT(3)
59 #define USBF_USB_SOF_INT BIT(4)
60 #define USBF_USB_SOF_ERROR_INT BIT(5)
61 #define USBF_USB_SPEED_MODE_INT BIT(6)
62 #define USBF_USB_EPN_INT(_n) (BIT(8) << (_n)) /* n=0..15 */
63
64 #define USBF_REG_USB_INT_ENA 0x024
65 #define USBF_USB_RSUM_EN BIT(1)
66 #define USBF_USB_SPND_EN BIT(2)
67 #define USBF_USB_USB_RST_EN BIT(3)
68 #define USBF_USB_SOF_EN BIT(4)
69 #define USBF_USB_SOF_ERROR_EN BIT(5)
70 #define USBF_USB_SPEED_MODE_EN BIT(6)
71 #define USBF_USB_EPN_EN(_n) (BIT(8) << (_n)) /* n=0..15 */
72
73 #define USBF_BASE_EP0 0x028
74 /* EP0 registers offsets from Base + USBF_BASE_EP0 (EP0 regs area) */
75 #define USBF_REG_EP0_CONTROL 0x00
76 #define USBF_EP0_ONAK BIT(0)
77 #define USBF_EP0_INAK BIT(1)
78 #define USBF_EP0_STL BIT(2)
79 #define USBF_EP0_PERR_NAK_CLR BIT(3)
80 #define USBF_EP0_INAK_EN BIT(4)
81 #define USBF_EP0_DW_MASK (0x3 << 5)
82 #define USBF_EP0_DW(_s) ((_s) << 5)
83 #define USBF_EP0_DEND BIT(7)
84 #define USBF_EP0_BCLR BIT(8)
85 #define USBF_EP0_PIDCLR BIT(9)
86 #define USBF_EP0_AUTO BIT(16)
87 #define USBF_EP0_OVERSEL BIT(17)
88 #define USBF_EP0_STGSEL BIT(18)
89
90 #define USBF_REG_EP0_STATUS 0x04
91 #define USBF_EP0_SETUP_INT BIT(0)
92 #define USBF_EP0_STG_START_INT BIT(1)
93 #define USBF_EP0_STG_END_INT BIT(2)
94 #define USBF_EP0_STALL_INT BIT(3)
95 #define USBF_EP0_IN_INT BIT(4)
96 #define USBF_EP0_OUT_INT BIT(5)
97 #define USBF_EP0_OUT_OR_INT BIT(6)
98 #define USBF_EP0_OUT_NULL_INT BIT(7)
99 #define USBF_EP0_IN_EMPTY BIT(8)
100 #define USBF_EP0_IN_FULL BIT(9)
101 #define USBF_EP0_IN_DATA BIT(10)
102 #define USBF_EP0_IN_NAK_INT BIT(11)
103 #define USBF_EP0_OUT_EMPTY BIT(12)
104 #define USBF_EP0_OUT_FULL BIT(13)
105 #define USBF_EP0_OUT_NULL BIT(14)
106 #define USBF_EP0_OUT_NAK_INT BIT(15)
107 #define USBF_EP0_PERR_NAK_INT BIT(16)
108 #define USBF_EP0_PERR_NAK BIT(17)
109 #define USBF_EP0_PID BIT(18)
110
111 #define USBF_REG_EP0_INT_ENA 0x08
112 #define USBF_EP0_SETUP_EN BIT(0)
113 #define USBF_EP0_STG_START_EN BIT(1)
114 #define USBF_EP0_STG_END_EN BIT(2)
115 #define USBF_EP0_STALL_EN BIT(3)
116 #define USBF_EP0_IN_EN BIT(4)
117 #define USBF_EP0_OUT_EN BIT(5)
118 #define USBF_EP0_OUT_OR_EN BIT(6)
119 #define USBF_EP0_OUT_NULL_EN BIT(7)
120 #define USBF_EP0_IN_NAK_EN BIT(11)
121 #define USBF_EP0_OUT_NAK_EN BIT(15)
122 #define USBF_EP0_PERR_NAK_EN BIT(16)
123
124 #define USBF_REG_EP0_LENGTH 0x0C
125 #define USBF_EP0_LDATA (0x7FF << 0)
126 #define USBF_REG_EP0_READ 0x10
127 #define USBF_REG_EP0_WRITE 0x14
128
129 #define USBF_BASE_EPN(_n) (0x040 + (_n) * 0x020)
130 /* EPn registers offsets from Base + USBF_BASE_EPN(n-1). n=1..15 */
131 #define USBF_REG_EPN_CONTROL 0x000
132 #define USBF_EPN_ONAK BIT(0)
133 #define USBF_EPN_OSTL BIT(2)
134 #define USBF_EPN_ISTL BIT(3)
135 #define USBF_EPN_OSTL_EN BIT(4)
136 #define USBF_EPN_DW_MASK (0x3 << 5)
137 #define USBF_EPN_DW(_s) ((_s) << 5)
138 #define USBF_EPN_DEND BIT(7)
139 #define USBF_EPN_CBCLR BIT(8)
140 #define USBF_EPN_BCLR BIT(9)
141 #define USBF_EPN_OPIDCLR BIT(10)
142 #define USBF_EPN_IPIDCLR BIT(11)
143 #define USBF_EPN_AUTO BIT(16)
144 #define USBF_EPN_OVERSEL BIT(17)
145 #define USBF_EPN_MODE_MASK (0x3 << 24)
146 #define USBF_EPN_MODE_BULK (0x0 << 24)
147 #define USBF_EPN_MODE_INTR (0x1 << 24)
148 #define USBF_EPN_MODE_ISO (0x2 << 24)
149 #define USBF_EPN_DIR0 BIT(26)
150 #define USBF_EPN_BUF_TYPE_DOUBLE BIT(30)
151 #define USBF_EPN_EN BIT(31)
152
153 #define USBF_REG_EPN_STATUS 0x004
154 #define USBF_EPN_IN_EMPTY BIT(0)
155 #define USBF_EPN_IN_FULL BIT(1)
156 #define USBF_EPN_IN_DATA BIT(2)
157 #define USBF_EPN_IN_INT BIT(3)
158 #define USBF_EPN_IN_STALL_INT BIT(4)
159 #define USBF_EPN_IN_NAK_ERR_INT BIT(5)
160 #define USBF_EPN_IN_END_INT BIT(7)
161 #define USBF_EPN_IPID BIT(10)
162 #define USBF_EPN_OUT_EMPTY BIT(16)
163 #define USBF_EPN_OUT_FULL BIT(17)
164 #define USBF_EPN_OUT_NULL_INT BIT(18)
165 #define USBF_EPN_OUT_INT BIT(19)
166 #define USBF_EPN_OUT_STALL_INT BIT(20)
167 #define USBF_EPN_OUT_NAK_ERR_INT BIT(21)
168 #define USBF_EPN_OUT_OR_INT BIT(22)
169 #define USBF_EPN_OUT_END_INT BIT(23)
170 #define USBF_EPN_ISO_CRC BIT(24)
171 #define USBF_EPN_ISO_OR BIT(26)
172 #define USBF_EPN_OUT_NOTKN BIT(27)
173 #define USBF_EPN_ISO_OPID BIT(28)
174 #define USBF_EPN_ISO_PIDERR BIT(29)
175
176 #define USBF_REG_EPN_INT_ENA 0x008
177 #define USBF_EPN_IN_EN BIT(3)
178 #define USBF_EPN_IN_STALL_EN BIT(4)
179 #define USBF_EPN_IN_NAK_ERR_EN BIT(5)
180 #define USBF_EPN_IN_END_EN BIT(7)
181 #define USBF_EPN_OUT_NULL_EN BIT(18)
182 #define USBF_EPN_OUT_EN BIT(19)
183 #define USBF_EPN_OUT_STALL_EN BIT(20)
184 #define USBF_EPN_OUT_NAK_ERR_EN BIT(21)
185 #define USBF_EPN_OUT_OR_EN BIT(22)
186 #define USBF_EPN_OUT_END_EN BIT(23)
187
188 #define USBF_REG_EPN_DMA_CTRL 0x00C
189 #define USBF_EPN_DMAMODE0 BIT(0)
190 #define USBF_EPN_DMA_EN BIT(4)
191 #define USBF_EPN_STOP_SET BIT(8)
192 #define USBF_EPN_BURST_SET BIT(9)
193 #define USBF_EPN_DEND_SET BIT(10)
194 #define USBF_EPN_STOP_MODE BIT(11)
195
196 #define USBF_REG_EPN_PCKT_ADRS 0x010
197 #define USBF_EPN_MPKT(_l) ((_l) << 0)
198 #define USBF_EPN_BASEAD(_a) ((_a) << 16)
199
200 #define USBF_REG_EPN_LEN_DCNT 0x014
201 #define USBF_EPN_GET_LDATA(_r) ((_r) & 0x7FF)
202 #define USBF_EPN_SET_DMACNT(_c) ((_c) << 16)
203 #define USBF_EPN_GET_DMACNT(_r) (((_r) >> 16) & 0x1ff)
204
205 #define USBF_REG_EPN_READ 0x018
206 #define USBF_REG_EPN_WRITE 0x01C
207
208 /* AHB-EPC Bridge registers */
209 #define USBF_REG_AHBSCTR 0x1000
210 #define USBF_REG_AHBMCTR 0x1004
211 #define USBF_SYS_WBURST_TYPE BIT(2)
212 #define USBF_SYS_ARBITER_CTR BIT(31)
213
214 #define USBF_REG_AHBBINT 0x1008
215 #define USBF_SYS_ERR_MASTER (0x0F << 0)
216 #define USBF_SYS_SBUS_ERRINT0 BIT(4)
217 #define USBF_SYS_SBUS_ERRINT1 BIT(5)
218 #define USBF_SYS_MBUS_ERRINT BIT(6)
219 #define USBF_SYS_VBUS_INT BIT(13)
220 #define USBF_SYS_DMA_ENDINT_EPN(_n) (BIT(16) << (_n)) /* _n=1..15 */
221
222 #define USBF_REG_AHBBINTEN 0x100C
223 #define USBF_SYS_SBUS_ERRINT0EN BIT(4)
224 #define USBF_SYS_SBUS_ERRINT1EN BIT(5)
225 #define USBF_SYS_MBUS_ERRINTEN BIT(6)
226 #define USBF_SYS_VBUS_INTEN BIT(13)
227 #define USBF_SYS_DMA_ENDINTEN_EPN(_n) (BIT(16) << (_n)) /* _n=1..15 */
228
229 #define USBF_REG_EPCTR 0x1010
230 #define USBF_SYS_EPC_RST BIT(0)
231 #define USBF_SYS_PLL_RST BIT(2)
232 #define USBF_SYS_PLL_LOCK BIT(4)
233 #define USBF_SYS_PLL_RESUME BIT(5)
234 #define USBF_SYS_VBUS_LEVEL BIT(8)
235 #define USBF_SYS_DIRPD BIT(12)
236
237 #define USBF_REG_USBSSVER 0x1020
238 #define USBF_REG_USBSSCONF 0x1024
239 #define USBF_SYS_DMA_AVAILABLE(_n) (BIT(0) << (_n)) /* _n=0..15 */
240 #define USBF_SYS_EP_AVAILABLE(_n) (BIT(16) << (_n)) /* _n=0..15 */
241
242 #define USBF_BASE_DMA_EPN(_n) (0x1110 + (_n) * 0x010)
243 /* EPn DMA registers offsets from Base USBF_BASE_DMA_EPN(n-1). n=1..15*/
244 #define USBF_REG_DMA_EPN_DCR1 0x00
245 #define USBF_SYS_EPN_REQEN BIT(0)
246 #define USBF_SYS_EPN_DIR0 BIT(1)
247 #define USBF_SYS_EPN_SET_DMACNT(_c) ((_c) << 16)
248 #define USBF_SYS_EPN_GET_DMACNT(_r) (((_r) >> 16) & 0x0FF)
249
250 #define USBF_REG_DMA_EPN_DCR2 0x04
251 #define USBF_SYS_EPN_MPKT(_s) ((_s) << 0)
252 #define USBF_SYS_EPN_LMPKT(_l) ((_l) << 16)
253
254 #define USBF_REG_DMA_EPN_TADR 0x08
255
256 /* USB request */
257 struct usbf_req {
258 struct usb_request req;
259 struct list_head queue;
260 unsigned int is_zero_sent : 1;
261 unsigned int is_mapped : 1;
262 enum {
263 USBF_XFER_START,
264 USBF_XFER_WAIT_DMA,
265 USBF_XFER_SEND_NULL,
266 USBF_XFER_WAIT_END,
267 USBF_XFER_WAIT_DMA_SHORT,
268 USBF_XFER_WAIT_BRIDGE,
269 } xfer_step;
270 size_t dma_size;
271 };
272
273 /* USB Endpoint */
274 struct usbf_ep {
275 struct usb_ep ep;
276 char name[32];
277 struct list_head queue;
278 unsigned int is_processing : 1;
279 unsigned int is_in : 1;
280 struct usbf_udc *udc;
281 void __iomem *regs;
282 void __iomem *dma_regs;
283 unsigned int id : 8;
284 unsigned int disabled : 1;
285 unsigned int is_wedged : 1;
286 unsigned int delayed_status : 1;
287 u32 status;
288 void (*bridge_on_dma_end)(struct usbf_ep *ep);
289 };
290
291 enum usbf_ep0state {
292 EP0_IDLE,
293 EP0_IN_DATA_PHASE,
294 EP0_OUT_DATA_PHASE,
295 EP0_OUT_STATUS_START_PHASE,
296 EP0_OUT_STATUS_PHASE,
297 EP0_OUT_STATUS_END_PHASE,
298 EP0_IN_STATUS_START_PHASE,
299 EP0_IN_STATUS_PHASE,
300 EP0_IN_STATUS_END_PHASE,
301 };
302
303 struct usbf_udc {
304 struct usb_gadget gadget;
305 struct usb_gadget_driver *driver;
306 struct device *dev;
307 void __iomem *regs;
308 spinlock_t lock;
309 bool is_remote_wakeup;
310 bool is_usb_suspended;
311 struct usbf_ep ep[USBF_NUM_ENDPOINTS];
312 /* for EP0 control messages */
313 enum usbf_ep0state ep0state;
314 struct usbf_req setup_reply;
315 u8 ep0_buf[USBF_EP0_MAX_PCKT_SIZE];
316 };
317
318 struct usbf_ep_info {
319 const char *name;
320 struct usb_ep_caps caps;
321 u16 base_addr;
322 unsigned int is_double : 1;
323 u16 maxpacket_limit;
324 };
325
326 #define USBF_SINGLE_BUFFER 0
327 #define USBF_DOUBLE_BUFFER 1
328 #define USBF_EP_INFO(_name, _caps, _base_addr, _is_double, _maxpacket_limit) \
329 { \
330 .name = _name, \
331 .caps = _caps, \
332 .base_addr = _base_addr, \
333 .is_double = _is_double, \
334 .maxpacket_limit = _maxpacket_limit, \
335 }
336
337 /* This table is computed from the recommended values provided in the SOC
338 * datasheet. The buffer type (single/double) and the endpoint type cannot
339 * be changed. The mapping in internal RAM (base_addr and number of words)
340 * for each endpoints depends on the max packet size and the buffer type.
341 */
342 static const struct usbf_ep_info usbf_ep_info[USBF_NUM_ENDPOINTS] = {
343 /* ep0: buf @0x0000 64 bytes, fixed 32 words */
344 [0] = USBF_EP_INFO("ep0-ctrl",
345 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
346 USB_EP_CAPS_DIR_ALL),
347 0x0000, USBF_SINGLE_BUFFER, USBF_EP0_MAX_PCKT_SIZE),
348 /* ep1: buf @0x0020, 2 buffers 512 bytes -> (512 * 2 / 4) words */
349 [1] = USBF_EP_INFO("ep1-bulk",
350 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
351 USB_EP_CAPS_DIR_ALL),
352 0x0020, USBF_DOUBLE_BUFFER, 512),
353 /* ep2: buf @0x0120, 2 buffers 512 bytes -> (512 * 2 / 4) words */
354 [2] = USBF_EP_INFO("ep2-bulk",
355 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
356 USB_EP_CAPS_DIR_ALL),
357 0x0120, USBF_DOUBLE_BUFFER, 512),
358 /* ep3: buf @0x0220, 1 buffer 512 bytes -> (512 * 2 / 4) words */
359 [3] = USBF_EP_INFO("ep3-bulk",
360 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
361 USB_EP_CAPS_DIR_ALL),
362 0x0220, USBF_SINGLE_BUFFER, 512),
363 /* ep4: buf @0x02A0, 1 buffer 512 bytes -> (512 * 1 / 4) words */
364 [4] = USBF_EP_INFO("ep4-bulk",
365 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
366 USB_EP_CAPS_DIR_ALL),
367 0x02A0, USBF_SINGLE_BUFFER, 512),
368 /* ep5: buf @0x0320, 1 buffer 512 bytes -> (512 * 2 / 4) words */
369 [5] = USBF_EP_INFO("ep5-bulk",
370 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
371 USB_EP_CAPS_DIR_ALL),
372 0x0320, USBF_SINGLE_BUFFER, 512),
373 /* ep6: buf @0x03A0, 1 buffer 1024 bytes -> (1024 * 1 / 4) words */
374 [6] = USBF_EP_INFO("ep6-int",
375 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
376 USB_EP_CAPS_DIR_ALL),
377 0x03A0, USBF_SINGLE_BUFFER, 1024),
378 /* ep7: buf @0x04A0, 1 buffer 1024 bytes -> (1024 * 1 / 4) words */
379 [7] = USBF_EP_INFO("ep7-int",
380 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
381 USB_EP_CAPS_DIR_ALL),
382 0x04A0, USBF_SINGLE_BUFFER, 1024),
383 /* ep8: buf @0x0520, 1 buffer 1024 bytes -> (1024 * 1 / 4) words */
384 [8] = USBF_EP_INFO("ep8-int",
385 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
386 USB_EP_CAPS_DIR_ALL),
387 0x0520, USBF_SINGLE_BUFFER, 1024),
388 /* ep9: buf @0x0620, 1 buffer 1024 bytes -> (1024 * 1 / 4) words */
389 [9] = USBF_EP_INFO("ep9-int",
390 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
391 USB_EP_CAPS_DIR_ALL),
392 0x0620, USBF_SINGLE_BUFFER, 1024),
393 /* ep10: buf @0x0720, 2 buffers 1024 bytes -> (1024 * 2 / 4) words */
394 [10] = USBF_EP_INFO("ep10-iso",
395 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
396 USB_EP_CAPS_DIR_ALL),
397 0x0720, USBF_DOUBLE_BUFFER, 1024),
398 /* ep11: buf @0x0920, 2 buffers 1024 bytes -> (1024 * 2 / 4) words */
399 [11] = USBF_EP_INFO("ep11-iso",
400 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
401 USB_EP_CAPS_DIR_ALL),
402 0x0920, USBF_DOUBLE_BUFFER, 1024),
403 /* ep12: buf @0x0B20, 2 buffers 1024 bytes -> (1024 * 2 / 4) words */
404 [12] = USBF_EP_INFO("ep12-iso",
405 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
406 USB_EP_CAPS_DIR_ALL),
407 0x0B20, USBF_DOUBLE_BUFFER, 1024),
408 /* ep13: buf @0x0D20, 2 buffers 1024 bytes -> (1024 * 2 / 4) words */
409 [13] = USBF_EP_INFO("ep13-iso",
410 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
411 USB_EP_CAPS_DIR_ALL),
412 0x0D20, USBF_DOUBLE_BUFFER, 1024),
413 /* ep14: buf @0x0F20, 2 buffers 1024 bytes -> (1024 * 2 / 4) words */
414 [14] = USBF_EP_INFO("ep14-iso",
415 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
416 USB_EP_CAPS_DIR_ALL),
417 0x0F20, USBF_DOUBLE_BUFFER, 1024),
418 /* ep15: buf @0x1120, 2 buffers 1024 bytes -> (1024 * 2 / 4) words */
419 [15] = USBF_EP_INFO("ep15-iso",
420 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
421 USB_EP_CAPS_DIR_ALL),
422 0x1120, USBF_DOUBLE_BUFFER, 1024),
423 };
424
usbf_reg_readl(struct usbf_udc * udc,uint offset)425 static inline u32 usbf_reg_readl(struct usbf_udc *udc, uint offset)
426 {
427 return readl(udc->regs + offset);
428 }
429
usbf_reg_writel(struct usbf_udc * udc,uint offset,u32 val)430 static inline void usbf_reg_writel(struct usbf_udc *udc, uint offset, u32 val)
431 {
432 writel(val, udc->regs + offset);
433 }
434
usbf_reg_bitset(struct usbf_udc * udc,uint offset,u32 set)435 static inline void usbf_reg_bitset(struct usbf_udc *udc, uint offset, u32 set)
436 {
437 u32 tmp;
438
439 tmp = usbf_reg_readl(udc, offset);
440 tmp |= set;
441 usbf_reg_writel(udc, offset, tmp);
442 }
443
usbf_reg_bitclr(struct usbf_udc * udc,uint offset,u32 clr)444 static inline void usbf_reg_bitclr(struct usbf_udc *udc, uint offset, u32 clr)
445 {
446 u32 tmp;
447
448 tmp = usbf_reg_readl(udc, offset);
449 tmp &= ~clr;
450 usbf_reg_writel(udc, offset, tmp);
451 }
452
usbf_reg_clrset(struct usbf_udc * udc,uint offset,u32 clr,u32 set)453 static inline void usbf_reg_clrset(struct usbf_udc *udc, uint offset,
454 u32 clr, u32 set)
455 {
456 u32 tmp;
457
458 tmp = usbf_reg_readl(udc, offset);
459 tmp &= ~clr;
460 tmp |= set;
461 usbf_reg_writel(udc, offset, tmp);
462 }
463
usbf_ep_reg_readl(struct usbf_ep * ep,uint offset)464 static inline u32 usbf_ep_reg_readl(struct usbf_ep *ep, uint offset)
465 {
466 return readl(ep->regs + offset);
467 }
468
usbf_ep_reg_read_rep(struct usbf_ep * ep,uint offset,void * dst,uint count)469 static inline void usbf_ep_reg_read_rep(struct usbf_ep *ep, uint offset,
470 void *dst, uint count)
471 {
472 readsl(ep->regs + offset, dst, count);
473 }
474
usbf_ep_reg_writel(struct usbf_ep * ep,uint offset,u32 val)475 static inline void usbf_ep_reg_writel(struct usbf_ep *ep, uint offset, u32 val)
476 {
477 writel(val, ep->regs + offset);
478 }
479
usbf_ep_reg_write_rep(struct usbf_ep * ep,uint offset,const void * src,uint count)480 static inline void usbf_ep_reg_write_rep(struct usbf_ep *ep, uint offset,
481 const void *src, uint count)
482 {
483 writesl(ep->regs + offset, src, count);
484 }
485
usbf_ep_reg_bitset(struct usbf_ep * ep,uint offset,u32 set)486 static inline void usbf_ep_reg_bitset(struct usbf_ep *ep, uint offset, u32 set)
487 {
488 u32 tmp;
489
490 tmp = usbf_ep_reg_readl(ep, offset);
491 tmp |= set;
492 usbf_ep_reg_writel(ep, offset, tmp);
493 }
494
usbf_ep_reg_bitclr(struct usbf_ep * ep,uint offset,u32 clr)495 static inline void usbf_ep_reg_bitclr(struct usbf_ep *ep, uint offset, u32 clr)
496 {
497 u32 tmp;
498
499 tmp = usbf_ep_reg_readl(ep, offset);
500 tmp &= ~clr;
501 usbf_ep_reg_writel(ep, offset, tmp);
502 }
503
usbf_ep_reg_clrset(struct usbf_ep * ep,uint offset,u32 clr,u32 set)504 static inline void usbf_ep_reg_clrset(struct usbf_ep *ep, uint offset,
505 u32 clr, u32 set)
506 {
507 u32 tmp;
508
509 tmp = usbf_ep_reg_readl(ep, offset);
510 tmp &= ~clr;
511 tmp |= set;
512 usbf_ep_reg_writel(ep, offset, tmp);
513 }
514
usbf_ep_dma_reg_readl(struct usbf_ep * ep,uint offset)515 static inline u32 usbf_ep_dma_reg_readl(struct usbf_ep *ep, uint offset)
516 {
517 return readl(ep->dma_regs + offset);
518 }
519
usbf_ep_dma_reg_writel(struct usbf_ep * ep,uint offset,u32 val)520 static inline void usbf_ep_dma_reg_writel(struct usbf_ep *ep, uint offset,
521 u32 val)
522 {
523 writel(val, ep->dma_regs + offset);
524 }
525
usbf_ep_dma_reg_bitset(struct usbf_ep * ep,uint offset,u32 set)526 static inline void usbf_ep_dma_reg_bitset(struct usbf_ep *ep, uint offset,
527 u32 set)
528 {
529 u32 tmp;
530
531 tmp = usbf_ep_dma_reg_readl(ep, offset);
532 tmp |= set;
533 usbf_ep_dma_reg_writel(ep, offset, tmp);
534 }
535
usbf_ep_dma_reg_bitclr(struct usbf_ep * ep,uint offset,u32 clr)536 static inline void usbf_ep_dma_reg_bitclr(struct usbf_ep *ep, uint offset,
537 u32 clr)
538 {
539 u32 tmp;
540
541 tmp = usbf_ep_dma_reg_readl(ep, offset);
542 tmp &= ~clr;
543 usbf_ep_dma_reg_writel(ep, offset, tmp);
544 }
545
usbf_ep0_send_null(struct usbf_ep * ep0,bool is_data1)546 static void usbf_ep0_send_null(struct usbf_ep *ep0, bool is_data1)
547 {
548 u32 set;
549
550 set = USBF_EP0_DEND;
551 if (is_data1)
552 set |= USBF_EP0_PIDCLR;
553
554 usbf_ep_reg_bitset(ep0, USBF_REG_EP0_CONTROL, set);
555 }
556
usbf_ep0_pio_in(struct usbf_ep * ep0,struct usbf_req * req)557 static int usbf_ep0_pio_in(struct usbf_ep *ep0, struct usbf_req *req)
558 {
559 unsigned int left;
560 unsigned int nb;
561 const void *buf;
562 u32 ctrl;
563 u32 last;
564
565 left = req->req.length - req->req.actual;
566
567 if (left == 0) {
568 if (!req->is_zero_sent) {
569 if (req->req.length == 0) {
570 dev_dbg(ep0->udc->dev, "ep0 send null\n");
571 usbf_ep0_send_null(ep0, false);
572 req->is_zero_sent = 1;
573 return -EINPROGRESS;
574 }
575 if ((req->req.actual % ep0->ep.maxpacket) == 0) {
576 if (req->req.zero) {
577 dev_dbg(ep0->udc->dev, "ep0 send null\n");
578 usbf_ep0_send_null(ep0, false);
579 req->is_zero_sent = 1;
580 return -EINPROGRESS;
581 }
582 }
583 }
584 return 0;
585 }
586
587 if (left > ep0->ep.maxpacket)
588 left = ep0->ep.maxpacket;
589
590 buf = req->req.buf;
591 buf += req->req.actual;
592
593 nb = left / sizeof(u32);
594 if (nb) {
595 usbf_ep_reg_write_rep(ep0, USBF_REG_EP0_WRITE, buf, nb);
596 buf += (nb * sizeof(u32));
597 req->req.actual += (nb * sizeof(u32));
598 left -= (nb * sizeof(u32));
599 }
600 ctrl = usbf_ep_reg_readl(ep0, USBF_REG_EP0_CONTROL);
601 ctrl &= ~USBF_EP0_DW_MASK;
602 if (left) {
603 memcpy(&last, buf, left);
604 usbf_ep_reg_writel(ep0, USBF_REG_EP0_WRITE, last);
605 ctrl |= USBF_EP0_DW(left);
606 req->req.actual += left;
607 }
608 usbf_ep_reg_writel(ep0, USBF_REG_EP0_CONTROL, ctrl | USBF_EP0_DEND);
609
610 dev_dbg(ep0->udc->dev, "ep0 send %u/%u\n",
611 req->req.actual, req->req.length);
612
613 return -EINPROGRESS;
614 }
615
usbf_ep0_pio_out(struct usbf_ep * ep0,struct usbf_req * req)616 static int usbf_ep0_pio_out(struct usbf_ep *ep0, struct usbf_req *req)
617 {
618 int req_status = 0;
619 unsigned int count;
620 unsigned int recv;
621 unsigned int left;
622 unsigned int nb;
623 void *buf;
624 u32 last;
625
626 if (ep0->status & USBF_EP0_OUT_INT) {
627 recv = usbf_ep_reg_readl(ep0, USBF_REG_EP0_LENGTH) & USBF_EP0_LDATA;
628 count = recv;
629
630 buf = req->req.buf;
631 buf += req->req.actual;
632
633 left = req->req.length - req->req.actual;
634
635 dev_dbg(ep0->udc->dev, "ep0 recv %u, left %u\n", count, left);
636
637 if (left > ep0->ep.maxpacket)
638 left = ep0->ep.maxpacket;
639
640 if (count > left) {
641 req_status = -EOVERFLOW;
642 count = left;
643 }
644
645 if (count) {
646 nb = count / sizeof(u32);
647 if (nb) {
648 usbf_ep_reg_read_rep(ep0, USBF_REG_EP0_READ,
649 buf, nb);
650 buf += (nb * sizeof(u32));
651 req->req.actual += (nb * sizeof(u32));
652 count -= (nb * sizeof(u32));
653 }
654 if (count) {
655 last = usbf_ep_reg_readl(ep0, USBF_REG_EP0_READ);
656 memcpy(buf, &last, count);
657 req->req.actual += count;
658 }
659 }
660 dev_dbg(ep0->udc->dev, "ep0 recv %u/%u\n",
661 req->req.actual, req->req.length);
662
663 if (req_status) {
664 dev_dbg(ep0->udc->dev, "ep0 req.status=%d\n", req_status);
665 req->req.status = req_status;
666 return 0;
667 }
668
669 if (recv < ep0->ep.maxpacket) {
670 dev_dbg(ep0->udc->dev, "ep0 short packet\n");
671 /* This is a short packet -> It is the end */
672 req->req.status = 0;
673 return 0;
674 }
675
676 /* The Data stage of a control transfer from an endpoint to the
677 * host is complete when the endpoint does one of the following:
678 * - Has transferred exactly the expected amount of data
679 * - Transfers a packet with a payload size less than
680 * wMaxPacketSize or transfers a zero-length packet
681 */
682 if (req->req.actual == req->req.length) {
683 req->req.status = 0;
684 return 0;
685 }
686 }
687
688 if (ep0->status & USBF_EP0_OUT_NULL_INT) {
689 /* NULL packet received */
690 dev_dbg(ep0->udc->dev, "ep0 null packet\n");
691 if (req->req.actual != req->req.length) {
692 req->req.status = req->req.short_not_ok ?
693 -EREMOTEIO : 0;
694 } else {
695 req->req.status = 0;
696 }
697 return 0;
698 }
699
700 return -EINPROGRESS;
701 }
702
usbf_ep0_fifo_flush(struct usbf_ep * ep0)703 static void usbf_ep0_fifo_flush(struct usbf_ep *ep0)
704 {
705 u32 sts;
706 int ret;
707
708 usbf_ep_reg_bitset(ep0, USBF_REG_EP0_CONTROL, USBF_EP0_BCLR);
709
710 ret = readl_poll_timeout_atomic(ep0->regs + USBF_REG_EP0_STATUS, sts,
711 (sts & (USBF_EP0_IN_DATA | USBF_EP0_IN_EMPTY)) == USBF_EP0_IN_EMPTY,
712 0, 10000);
713 if (ret)
714 dev_err(ep0->udc->dev, "ep0 flush fifo timed out\n");
715
716 }
717
usbf_epn_send_null(struct usbf_ep * epn)718 static void usbf_epn_send_null(struct usbf_ep *epn)
719 {
720 usbf_ep_reg_bitset(epn, USBF_REG_EPN_CONTROL, USBF_EPN_DEND);
721 }
722
usbf_epn_send_residue(struct usbf_ep * epn,const void * buf,unsigned int size)723 static void usbf_epn_send_residue(struct usbf_ep *epn, const void *buf,
724 unsigned int size)
725 {
726 u32 tmp;
727
728 memcpy(&tmp, buf, size);
729 usbf_ep_reg_writel(epn, USBF_REG_EPN_WRITE, tmp);
730
731 usbf_ep_reg_clrset(epn, USBF_REG_EPN_CONTROL,
732 USBF_EPN_DW_MASK,
733 USBF_EPN_DW(size) | USBF_EPN_DEND);
734 }
735
usbf_epn_pio_in(struct usbf_ep * epn,struct usbf_req * req)736 static int usbf_epn_pio_in(struct usbf_ep *epn, struct usbf_req *req)
737 {
738 unsigned int left;
739 unsigned int nb;
740 const void *buf;
741
742 left = req->req.length - req->req.actual;
743
744 if (left == 0) {
745 if (!req->is_zero_sent) {
746 if (req->req.length == 0) {
747 dev_dbg(epn->udc->dev, "ep%u send_null\n", epn->id);
748 usbf_epn_send_null(epn);
749 req->is_zero_sent = 1;
750 return -EINPROGRESS;
751 }
752 if ((req->req.actual % epn->ep.maxpacket) == 0) {
753 if (req->req.zero) {
754 dev_dbg(epn->udc->dev, "ep%u send_null\n",
755 epn->id);
756 usbf_epn_send_null(epn);
757 req->is_zero_sent = 1;
758 return -EINPROGRESS;
759 }
760 }
761 }
762 return 0;
763 }
764
765 if (left > epn->ep.maxpacket)
766 left = epn->ep.maxpacket;
767
768 buf = req->req.buf;
769 buf += req->req.actual;
770
771 nb = left / sizeof(u32);
772 if (nb) {
773 usbf_ep_reg_write_rep(epn, USBF_REG_EPN_WRITE, buf, nb);
774 buf += (nb * sizeof(u32));
775 req->req.actual += (nb * sizeof(u32));
776 left -= (nb * sizeof(u32));
777 }
778
779 if (left) {
780 usbf_epn_send_residue(epn, buf, left);
781 req->req.actual += left;
782 } else {
783 usbf_ep_reg_clrset(epn, USBF_REG_EPN_CONTROL,
784 USBF_EPN_DW_MASK,
785 USBF_EPN_DEND);
786 }
787
788 dev_dbg(epn->udc->dev, "ep%u send %u/%u\n", epn->id, req->req.actual,
789 req->req.length);
790
791 return -EINPROGRESS;
792 }
793
usbf_epn_enable_in_end_int(struct usbf_ep * epn)794 static void usbf_epn_enable_in_end_int(struct usbf_ep *epn)
795 {
796 usbf_ep_reg_bitset(epn, USBF_REG_EPN_INT_ENA, USBF_EPN_IN_END_EN);
797 }
798
usbf_epn_dma_in(struct usbf_ep * epn,struct usbf_req * req)799 static int usbf_epn_dma_in(struct usbf_ep *epn, struct usbf_req *req)
800 {
801 unsigned int left;
802 u32 npkt;
803 u32 lastpkt;
804 int ret;
805
806 if (!IS_ALIGNED((uintptr_t)req->req.buf, 4)) {
807 dev_dbg(epn->udc->dev, "ep%u buf unaligned -> fallback pio\n",
808 epn->id);
809 return usbf_epn_pio_in(epn, req);
810 }
811
812 left = req->req.length - req->req.actual;
813
814 switch (req->xfer_step) {
815 default:
816 case USBF_XFER_START:
817 if (left == 0) {
818 dev_dbg(epn->udc->dev, "ep%u send null\n", epn->id);
819 usbf_epn_send_null(epn);
820 req->xfer_step = USBF_XFER_WAIT_END;
821 break;
822 }
823 if (left < 4) {
824 dev_dbg(epn->udc->dev, "ep%u send residue %u\n", epn->id,
825 left);
826 usbf_epn_send_residue(epn,
827 req->req.buf + req->req.actual, left);
828 req->req.actual += left;
829 req->xfer_step = USBF_XFER_WAIT_END;
830 break;
831 }
832
833 ret = usb_gadget_map_request(&epn->udc->gadget, &req->req, 1);
834 if (ret < 0) {
835 dev_err(epn->udc->dev, "usb_gadget_map_request failed (%d)\n",
836 ret);
837 return ret;
838 }
839 req->is_mapped = 1;
840
841 npkt = DIV_ROUND_UP(left, epn->ep.maxpacket);
842 lastpkt = (left % epn->ep.maxpacket);
843 if (lastpkt == 0)
844 lastpkt = epn->ep.maxpacket;
845 lastpkt &= ~0x3; /* DMA is done on 32bit units */
846
847 usbf_ep_dma_reg_writel(epn, USBF_REG_DMA_EPN_DCR2,
848 USBF_SYS_EPN_MPKT(epn->ep.maxpacket) | USBF_SYS_EPN_LMPKT(lastpkt));
849 usbf_ep_dma_reg_writel(epn, USBF_REG_DMA_EPN_TADR,
850 req->req.dma);
851 usbf_ep_dma_reg_writel(epn, USBF_REG_DMA_EPN_DCR1,
852 USBF_SYS_EPN_SET_DMACNT(npkt));
853 usbf_ep_dma_reg_bitset(epn, USBF_REG_DMA_EPN_DCR1,
854 USBF_SYS_EPN_REQEN);
855
856 usbf_ep_reg_writel(epn, USBF_REG_EPN_LEN_DCNT, USBF_EPN_SET_DMACNT(npkt));
857
858 usbf_ep_reg_bitset(epn, USBF_REG_EPN_CONTROL, USBF_EPN_AUTO);
859
860 /* The end of DMA transfer at the USBF level needs to be handle
861 * after the detection of the end of DMA transfer at the brige
862 * level.
863 * To force this sequence, EPN_IN_END_EN will be set by the
864 * detection of the end of transfer at bridge level (ie. bridge
865 * interrupt).
866 */
867 usbf_ep_reg_bitclr(epn, USBF_REG_EPN_INT_ENA,
868 USBF_EPN_IN_EN | USBF_EPN_IN_END_EN);
869 epn->bridge_on_dma_end = usbf_epn_enable_in_end_int;
870
871 /* Clear any pending IN_END interrupt */
872 usbf_ep_reg_writel(epn, USBF_REG_EPN_STATUS, ~(u32)USBF_EPN_IN_END_INT);
873
874 usbf_ep_reg_writel(epn, USBF_REG_EPN_DMA_CTRL,
875 USBF_EPN_BURST_SET | USBF_EPN_DMAMODE0);
876 usbf_ep_reg_bitset(epn, USBF_REG_EPN_DMA_CTRL,
877 USBF_EPN_DMA_EN);
878
879 req->dma_size = (npkt - 1) * epn->ep.maxpacket + lastpkt;
880
881 dev_dbg(epn->udc->dev, "ep%u dma xfer %zu\n", epn->id,
882 req->dma_size);
883
884 req->xfer_step = USBF_XFER_WAIT_DMA;
885 break;
886
887 case USBF_XFER_WAIT_DMA:
888 if (!(epn->status & USBF_EPN_IN_END_INT)) {
889 dev_dbg(epn->udc->dev, "ep%u dma not done\n", epn->id);
890 break;
891 }
892 dev_dbg(epn->udc->dev, "ep%u dma done\n", epn->id);
893
894 usb_gadget_unmap_request(&epn->udc->gadget, &req->req, 1);
895 req->is_mapped = 0;
896
897 usbf_ep_reg_bitclr(epn, USBF_REG_EPN_CONTROL, USBF_EPN_AUTO);
898
899 usbf_ep_reg_clrset(epn, USBF_REG_EPN_INT_ENA,
900 USBF_EPN_IN_END_EN,
901 USBF_EPN_IN_EN);
902
903 req->req.actual += req->dma_size;
904
905 left = req->req.length - req->req.actual;
906 if (left) {
907 usbf_ep_reg_writel(epn, USBF_REG_EPN_STATUS, ~(u32)USBF_EPN_IN_INT);
908
909 dev_dbg(epn->udc->dev, "ep%u send residue %u\n", epn->id,
910 left);
911 usbf_epn_send_residue(epn,
912 req->req.buf + req->req.actual, left);
913 req->req.actual += left;
914 req->xfer_step = USBF_XFER_WAIT_END;
915 break;
916 }
917
918 if (req->req.actual % epn->ep.maxpacket) {
919 /* last packet was a short packet. Tell the hardware to
920 * send it right now.
921 */
922 dev_dbg(epn->udc->dev, "ep%u send short\n", epn->id);
923 usbf_ep_reg_writel(epn, USBF_REG_EPN_STATUS,
924 ~(u32)USBF_EPN_IN_INT);
925 usbf_ep_reg_bitset(epn, USBF_REG_EPN_CONTROL,
926 USBF_EPN_DEND);
927
928 req->xfer_step = USBF_XFER_WAIT_END;
929 break;
930 }
931
932 /* Last packet size was a maxpacket size
933 * Send null packet if needed
934 */
935 if (req->req.zero) {
936 req->xfer_step = USBF_XFER_SEND_NULL;
937 break;
938 }
939
940 /* No more action to do. Wait for the end of the USB transfer */
941 req->xfer_step = USBF_XFER_WAIT_END;
942 break;
943
944 case USBF_XFER_SEND_NULL:
945 dev_dbg(epn->udc->dev, "ep%u send null\n", epn->id);
946 usbf_epn_send_null(epn);
947 req->xfer_step = USBF_XFER_WAIT_END;
948 break;
949
950 case USBF_XFER_WAIT_END:
951 if (!(epn->status & USBF_EPN_IN_INT)) {
952 dev_dbg(epn->udc->dev, "ep%u end not done\n", epn->id);
953 break;
954 }
955 dev_dbg(epn->udc->dev, "ep%u send done %u/%u\n", epn->id,
956 req->req.actual, req->req.length);
957 req->xfer_step = USBF_XFER_START;
958 return 0;
959 }
960
961 return -EINPROGRESS;
962 }
963
usbf_epn_recv_residue(struct usbf_ep * epn,void * buf,unsigned int size)964 static void usbf_epn_recv_residue(struct usbf_ep *epn, void *buf,
965 unsigned int size)
966 {
967 u32 last;
968
969 last = usbf_ep_reg_readl(epn, USBF_REG_EPN_READ);
970 memcpy(buf, &last, size);
971 }
972
usbf_epn_pio_out(struct usbf_ep * epn,struct usbf_req * req)973 static int usbf_epn_pio_out(struct usbf_ep *epn, struct usbf_req *req)
974 {
975 int req_status = 0;
976 unsigned int count;
977 unsigned int recv;
978 unsigned int left;
979 unsigned int nb;
980 void *buf;
981
982 if (epn->status & USBF_EPN_OUT_INT) {
983 recv = USBF_EPN_GET_LDATA(
984 usbf_ep_reg_readl(epn, USBF_REG_EPN_LEN_DCNT));
985 count = recv;
986
987 buf = req->req.buf;
988 buf += req->req.actual;
989
990 left = req->req.length - req->req.actual;
991
992 dev_dbg(epn->udc->dev, "ep%u recv %u, left %u, mpkt %u\n", epn->id,
993 recv, left, epn->ep.maxpacket);
994
995 if (left > epn->ep.maxpacket)
996 left = epn->ep.maxpacket;
997
998 if (count > left) {
999 req_status = -EOVERFLOW;
1000 count = left;
1001 }
1002
1003 if (count) {
1004 nb = count / sizeof(u32);
1005 if (nb) {
1006 usbf_ep_reg_read_rep(epn, USBF_REG_EPN_READ,
1007 buf, nb);
1008 buf += (nb * sizeof(u32));
1009 req->req.actual += (nb * sizeof(u32));
1010 count -= (nb * sizeof(u32));
1011 }
1012 if (count) {
1013 usbf_epn_recv_residue(epn, buf, count);
1014 req->req.actual += count;
1015 }
1016 }
1017 dev_dbg(epn->udc->dev, "ep%u recv %u/%u\n", epn->id,
1018 req->req.actual, req->req.length);
1019
1020 if (req_status) {
1021 dev_dbg(epn->udc->dev, "ep%u req.status=%d\n", epn->id,
1022 req_status);
1023 req->req.status = req_status;
1024 return 0;
1025 }
1026
1027 if (recv < epn->ep.maxpacket) {
1028 dev_dbg(epn->udc->dev, "ep%u short packet\n", epn->id);
1029 /* This is a short packet -> It is the end */
1030 req->req.status = 0;
1031 return 0;
1032 }
1033
1034 /* Request full -> complete */
1035 if (req->req.actual == req->req.length) {
1036 req->req.status = 0;
1037 return 0;
1038 }
1039 }
1040
1041 if (epn->status & USBF_EPN_OUT_NULL_INT) {
1042 /* NULL packet received */
1043 dev_dbg(epn->udc->dev, "ep%u null packet\n", epn->id);
1044 if (req->req.actual != req->req.length) {
1045 req->req.status = req->req.short_not_ok ?
1046 -EREMOTEIO : 0;
1047 } else {
1048 req->req.status = 0;
1049 }
1050 return 0;
1051 }
1052
1053 return -EINPROGRESS;
1054 }
1055
usbf_epn_enable_out_end_int(struct usbf_ep * epn)1056 static void usbf_epn_enable_out_end_int(struct usbf_ep *epn)
1057 {
1058 usbf_ep_reg_bitset(epn, USBF_REG_EPN_INT_ENA, USBF_EPN_OUT_END_EN);
1059 }
1060
1061 static void usbf_epn_process_queue(struct usbf_ep *epn);
1062
usbf_epn_dma_out_send_dma(struct usbf_ep * epn,dma_addr_t addr,u32 npkt,bool is_short)1063 static void usbf_epn_dma_out_send_dma(struct usbf_ep *epn, dma_addr_t addr, u32 npkt, bool is_short)
1064 {
1065 usbf_ep_dma_reg_writel(epn, USBF_REG_DMA_EPN_DCR2, USBF_SYS_EPN_MPKT(epn->ep.maxpacket));
1066 usbf_ep_dma_reg_writel(epn, USBF_REG_DMA_EPN_TADR, addr);
1067
1068 if (is_short) {
1069 usbf_ep_dma_reg_writel(epn, USBF_REG_DMA_EPN_DCR1,
1070 USBF_SYS_EPN_SET_DMACNT(1) | USBF_SYS_EPN_DIR0);
1071 usbf_ep_dma_reg_bitset(epn, USBF_REG_DMA_EPN_DCR1,
1072 USBF_SYS_EPN_REQEN);
1073
1074 usbf_ep_reg_writel(epn, USBF_REG_EPN_LEN_DCNT,
1075 USBF_EPN_SET_DMACNT(0));
1076
1077 /* The end of DMA transfer at the USBF level needs to be handled
1078 * after the detection of the end of DMA transfer at the brige
1079 * level.
1080 * To force this sequence, enabling the OUT_END interrupt will
1081 * be donee by the detection of the end of transfer at bridge
1082 * level (ie. bridge interrupt).
1083 */
1084 usbf_ep_reg_bitclr(epn, USBF_REG_EPN_INT_ENA,
1085 USBF_EPN_OUT_EN | USBF_EPN_OUT_NULL_EN | USBF_EPN_OUT_END_EN);
1086 epn->bridge_on_dma_end = usbf_epn_enable_out_end_int;
1087
1088 /* Clear any pending OUT_END interrupt */
1089 usbf_ep_reg_writel(epn, USBF_REG_EPN_STATUS,
1090 ~(u32)USBF_EPN_OUT_END_INT);
1091
1092 usbf_ep_reg_writel(epn, USBF_REG_EPN_DMA_CTRL,
1093 USBF_EPN_STOP_MODE | USBF_EPN_STOP_SET | USBF_EPN_DMAMODE0);
1094 usbf_ep_reg_bitset(epn, USBF_REG_EPN_DMA_CTRL,
1095 USBF_EPN_DMA_EN);
1096 return;
1097 }
1098
1099 usbf_ep_dma_reg_writel(epn, USBF_REG_DMA_EPN_DCR1,
1100 USBF_SYS_EPN_SET_DMACNT(npkt) | USBF_SYS_EPN_DIR0);
1101 usbf_ep_dma_reg_bitset(epn, USBF_REG_DMA_EPN_DCR1,
1102 USBF_SYS_EPN_REQEN);
1103
1104 usbf_ep_reg_writel(epn, USBF_REG_EPN_LEN_DCNT,
1105 USBF_EPN_SET_DMACNT(npkt));
1106
1107 /* Here, the bridge may or may not generate an interrupt to signal the
1108 * end of DMA transfer.
1109 * Keep only OUT_END interrupt and let handle the bridge later during
1110 * the OUT_END processing.
1111 */
1112 usbf_ep_reg_clrset(epn, USBF_REG_EPN_INT_ENA,
1113 USBF_EPN_OUT_EN | USBF_EPN_OUT_NULL_EN,
1114 USBF_EPN_OUT_END_EN);
1115
1116 /* Disable bridge interrupt. It will be renabled later */
1117 usbf_reg_bitclr(epn->udc, USBF_REG_AHBBINTEN,
1118 USBF_SYS_DMA_ENDINTEN_EPN(epn->id));
1119
1120 /* Clear any pending DMA_END interrupt at bridge level */
1121 usbf_reg_writel(epn->udc, USBF_REG_AHBBINT,
1122 USBF_SYS_DMA_ENDINT_EPN(epn->id));
1123
1124 /* Clear any pending OUT_END interrupt */
1125 usbf_ep_reg_writel(epn, USBF_REG_EPN_STATUS,
1126 ~(u32)USBF_EPN_OUT_END_INT);
1127
1128 usbf_ep_reg_writel(epn, USBF_REG_EPN_DMA_CTRL,
1129 USBF_EPN_STOP_MODE | USBF_EPN_STOP_SET | USBF_EPN_DMAMODE0 | USBF_EPN_BURST_SET);
1130 usbf_ep_reg_bitset(epn, USBF_REG_EPN_DMA_CTRL,
1131 USBF_EPN_DMA_EN);
1132 }
1133
usbf_epn_dma_out_complete_dma(struct usbf_ep * epn,bool is_short)1134 static size_t usbf_epn_dma_out_complete_dma(struct usbf_ep *epn, bool is_short)
1135 {
1136 u32 dmacnt;
1137 u32 tmp;
1138 int ret;
1139
1140 /* Restore interrupt mask */
1141 usbf_ep_reg_clrset(epn, USBF_REG_EPN_INT_ENA,
1142 USBF_EPN_OUT_END_EN,
1143 USBF_EPN_OUT_EN | USBF_EPN_OUT_NULL_EN);
1144
1145 if (is_short) {
1146 /* Nothing more to do when the DMA was for a short packet */
1147 return 0;
1148 }
1149
1150 /* Enable the bridge interrupt */
1151 usbf_reg_bitset(epn->udc, USBF_REG_AHBBINTEN,
1152 USBF_SYS_DMA_ENDINTEN_EPN(epn->id));
1153
1154 tmp = usbf_ep_reg_readl(epn, USBF_REG_EPN_LEN_DCNT);
1155 dmacnt = USBF_EPN_GET_DMACNT(tmp);
1156
1157 if (dmacnt) {
1158 /* Some packet were not received (halted by a short or a null
1159 * packet.
1160 * The bridge never raises an interrupt in this case.
1161 * Wait for the end of transfer at bridge level
1162 */
1163 ret = readl_poll_timeout_atomic(
1164 epn->dma_regs + USBF_REG_DMA_EPN_DCR1,
1165 tmp, (USBF_SYS_EPN_GET_DMACNT(tmp) == dmacnt),
1166 0, 10000);
1167 if (ret) {
1168 dev_err(epn->udc->dev, "ep%u wait bridge timed out\n",
1169 epn->id);
1170 }
1171
1172 usbf_ep_dma_reg_bitclr(epn, USBF_REG_DMA_EPN_DCR1,
1173 USBF_SYS_EPN_REQEN);
1174
1175 /* The dmacnt value tells how many packet were not transferred
1176 * from the maximum number of packet we set for the DMA transfer.
1177 * Compute the left DMA size based on this value.
1178 */
1179 return dmacnt * epn->ep.maxpacket;
1180 }
1181
1182 return 0;
1183 }
1184
usbf_epn_dma_out(struct usbf_ep * epn,struct usbf_req * req)1185 static int usbf_epn_dma_out(struct usbf_ep *epn, struct usbf_req *req)
1186 {
1187 unsigned int dma_left;
1188 unsigned int count;
1189 unsigned int recv;
1190 unsigned int left;
1191 u32 npkt;
1192 int ret;
1193
1194 if (!IS_ALIGNED((uintptr_t)req->req.buf, 4)) {
1195 dev_dbg(epn->udc->dev, "ep%u buf unaligned -> fallback pio\n",
1196 epn->id);
1197 return usbf_epn_pio_out(epn, req);
1198 }
1199
1200 switch (req->xfer_step) {
1201 default:
1202 case USBF_XFER_START:
1203 if (epn->status & USBF_EPN_OUT_NULL_INT) {
1204 dev_dbg(epn->udc->dev, "ep%u null packet\n", epn->id);
1205 if (req->req.actual != req->req.length) {
1206 req->req.status = req->req.short_not_ok ?
1207 -EREMOTEIO : 0;
1208 } else {
1209 req->req.status = 0;
1210 }
1211 return 0;
1212 }
1213
1214 if (!(epn->status & USBF_EPN_OUT_INT)) {
1215 dev_dbg(epn->udc->dev, "ep%u OUT_INT not set -> spurious\n",
1216 epn->id);
1217 break;
1218 }
1219
1220 recv = USBF_EPN_GET_LDATA(
1221 usbf_ep_reg_readl(epn, USBF_REG_EPN_LEN_DCNT));
1222 if (!recv) {
1223 dev_dbg(epn->udc->dev, "ep%u recv = 0 -> spurious\n",
1224 epn->id);
1225 break;
1226 }
1227
1228 left = req->req.length - req->req.actual;
1229
1230 dev_dbg(epn->udc->dev, "ep%u recv %u, left %u, mpkt %u\n", epn->id,
1231 recv, left, epn->ep.maxpacket);
1232
1233 if (recv > left) {
1234 dev_err(epn->udc->dev, "ep%u overflow (%u/%u)\n",
1235 epn->id, recv, left);
1236 req->req.status = -EOVERFLOW;
1237 return -EOVERFLOW;
1238 }
1239
1240 if (recv < epn->ep.maxpacket) {
1241 /* Short packet received */
1242 dev_dbg(epn->udc->dev, "ep%u short packet\n", epn->id);
1243 if (recv <= 3) {
1244 usbf_epn_recv_residue(epn,
1245 req->req.buf + req->req.actual, recv);
1246 req->req.actual += recv;
1247
1248 dev_dbg(epn->udc->dev, "ep%u recv done %u/%u\n",
1249 epn->id, req->req.actual, req->req.length);
1250
1251 req->xfer_step = USBF_XFER_START;
1252 return 0;
1253 }
1254
1255 ret = usb_gadget_map_request(&epn->udc->gadget, &req->req, 0);
1256 if (ret < 0) {
1257 dev_err(epn->udc->dev, "map request failed (%d)\n",
1258 ret);
1259 return ret;
1260 }
1261 req->is_mapped = 1;
1262
1263 usbf_epn_dma_out_send_dma(epn,
1264 req->req.dma + req->req.actual,
1265 1, true);
1266 req->dma_size = recv & ~0x3;
1267
1268 dev_dbg(epn->udc->dev, "ep%u dma short xfer %zu\n", epn->id,
1269 req->dma_size);
1270
1271 req->xfer_step = USBF_XFER_WAIT_DMA_SHORT;
1272 break;
1273 }
1274
1275 ret = usb_gadget_map_request(&epn->udc->gadget, &req->req, 0);
1276 if (ret < 0) {
1277 dev_err(epn->udc->dev, "map request failed (%d)\n",
1278 ret);
1279 return ret;
1280 }
1281 req->is_mapped = 1;
1282
1283 /* Use the maximum DMA size according to the request buffer.
1284 * We will adjust the received size later at the end of the DMA
1285 * transfer with the left size computed from
1286 * usbf_epn_dma_out_complete_dma().
1287 */
1288 npkt = left / epn->ep.maxpacket;
1289 usbf_epn_dma_out_send_dma(epn,
1290 req->req.dma + req->req.actual,
1291 npkt, false);
1292 req->dma_size = npkt * epn->ep.maxpacket;
1293
1294 dev_dbg(epn->udc->dev, "ep%u dma xfer %zu (%u)\n", epn->id,
1295 req->dma_size, npkt);
1296
1297 req->xfer_step = USBF_XFER_WAIT_DMA;
1298 break;
1299
1300 case USBF_XFER_WAIT_DMA_SHORT:
1301 if (!(epn->status & USBF_EPN_OUT_END_INT)) {
1302 dev_dbg(epn->udc->dev, "ep%u dma short not done\n", epn->id);
1303 break;
1304 }
1305 dev_dbg(epn->udc->dev, "ep%u dma short done\n", epn->id);
1306
1307 usbf_epn_dma_out_complete_dma(epn, true);
1308
1309 usb_gadget_unmap_request(&epn->udc->gadget, &req->req, 0);
1310 req->is_mapped = 0;
1311
1312 req->req.actual += req->dma_size;
1313
1314 recv = USBF_EPN_GET_LDATA(
1315 usbf_ep_reg_readl(epn, USBF_REG_EPN_LEN_DCNT));
1316
1317 count = recv & 0x3;
1318 if (count) {
1319 dev_dbg(epn->udc->dev, "ep%u recv residue %u\n", epn->id,
1320 count);
1321 usbf_epn_recv_residue(epn,
1322 req->req.buf + req->req.actual, count);
1323 req->req.actual += count;
1324 }
1325
1326 dev_dbg(epn->udc->dev, "ep%u recv done %u/%u\n", epn->id,
1327 req->req.actual, req->req.length);
1328
1329 req->xfer_step = USBF_XFER_START;
1330 return 0;
1331
1332 case USBF_XFER_WAIT_DMA:
1333 if (!(epn->status & USBF_EPN_OUT_END_INT)) {
1334 dev_dbg(epn->udc->dev, "ep%u dma not done\n", epn->id);
1335 break;
1336 }
1337 dev_dbg(epn->udc->dev, "ep%u dma done\n", epn->id);
1338
1339 dma_left = usbf_epn_dma_out_complete_dma(epn, false);
1340 if (dma_left) {
1341 /* Adjust the final DMA size with */
1342 count = req->dma_size - dma_left;
1343
1344 dev_dbg(epn->udc->dev, "ep%u dma xfer done %u\n", epn->id,
1345 count);
1346
1347 req->req.actual += count;
1348
1349 if (epn->status & USBF_EPN_OUT_NULL_INT) {
1350 /* DMA was stopped by a null packet reception */
1351 dev_dbg(epn->udc->dev, "ep%u dma stopped by null pckt\n",
1352 epn->id);
1353 usb_gadget_unmap_request(&epn->udc->gadget,
1354 &req->req, 0);
1355 req->is_mapped = 0;
1356
1357 usbf_ep_reg_writel(epn, USBF_REG_EPN_STATUS,
1358 ~(u32)USBF_EPN_OUT_NULL_INT);
1359
1360 if (req->req.actual != req->req.length) {
1361 req->req.status = req->req.short_not_ok ?
1362 -EREMOTEIO : 0;
1363 } else {
1364 req->req.status = 0;
1365 }
1366 dev_dbg(epn->udc->dev, "ep%u recv done %u/%u\n",
1367 epn->id, req->req.actual, req->req.length);
1368 req->xfer_step = USBF_XFER_START;
1369 return 0;
1370 }
1371
1372 recv = USBF_EPN_GET_LDATA(
1373 usbf_ep_reg_readl(epn, USBF_REG_EPN_LEN_DCNT));
1374 left = req->req.length - req->req.actual;
1375 if (recv > left) {
1376 dev_err(epn->udc->dev,
1377 "ep%u overflow (%u/%u)\n", epn->id,
1378 recv, left);
1379 req->req.status = -EOVERFLOW;
1380 usb_gadget_unmap_request(&epn->udc->gadget,
1381 &req->req, 0);
1382 req->is_mapped = 0;
1383
1384 req->xfer_step = USBF_XFER_START;
1385 return -EOVERFLOW;
1386 }
1387
1388 if (recv > 3) {
1389 usbf_epn_dma_out_send_dma(epn,
1390 req->req.dma + req->req.actual,
1391 1, true);
1392 req->dma_size = recv & ~0x3;
1393
1394 dev_dbg(epn->udc->dev, "ep%u dma short xfer %zu\n",
1395 epn->id, req->dma_size);
1396
1397 req->xfer_step = USBF_XFER_WAIT_DMA_SHORT;
1398 break;
1399 }
1400
1401 usb_gadget_unmap_request(&epn->udc->gadget, &req->req, 0);
1402 req->is_mapped = 0;
1403
1404 count = recv & 0x3;
1405 if (count) {
1406 dev_dbg(epn->udc->dev, "ep%u recv residue %u\n",
1407 epn->id, count);
1408 usbf_epn_recv_residue(epn,
1409 req->req.buf + req->req.actual, count);
1410 req->req.actual += count;
1411 }
1412
1413 dev_dbg(epn->udc->dev, "ep%u recv done %u/%u\n", epn->id,
1414 req->req.actual, req->req.length);
1415
1416 req->xfer_step = USBF_XFER_START;
1417 return 0;
1418 }
1419
1420 /* Process queue at bridge interrupt only */
1421 usbf_ep_reg_bitclr(epn, USBF_REG_EPN_INT_ENA,
1422 USBF_EPN_OUT_END_EN | USBF_EPN_OUT_EN | USBF_EPN_OUT_NULL_EN);
1423 epn->status = 0;
1424 epn->bridge_on_dma_end = usbf_epn_process_queue;
1425
1426 req->xfer_step = USBF_XFER_WAIT_BRIDGE;
1427 break;
1428
1429 case USBF_XFER_WAIT_BRIDGE:
1430 dev_dbg(epn->udc->dev, "ep%u bridge transfers done\n", epn->id);
1431
1432 /* Restore interrupt mask */
1433 usbf_ep_reg_clrset(epn, USBF_REG_EPN_INT_ENA,
1434 USBF_EPN_OUT_END_EN,
1435 USBF_EPN_OUT_EN | USBF_EPN_OUT_NULL_EN);
1436
1437 usb_gadget_unmap_request(&epn->udc->gadget, &req->req, 0);
1438 req->is_mapped = 0;
1439
1440 req->req.actual += req->dma_size;
1441
1442 req->xfer_step = USBF_XFER_START;
1443 left = req->req.length - req->req.actual;
1444 if (!left) {
1445 /* No more data can be added to the buffer */
1446 dev_dbg(epn->udc->dev, "ep%u recv done %u/%u\n", epn->id,
1447 req->req.actual, req->req.length);
1448 return 0;
1449 }
1450 dev_dbg(epn->udc->dev, "ep%u recv done %u/%u, wait more data\n",
1451 epn->id, req->req.actual, req->req.length);
1452 break;
1453 }
1454
1455 return -EINPROGRESS;
1456 }
1457
usbf_epn_dma_stop(struct usbf_ep * epn)1458 static void usbf_epn_dma_stop(struct usbf_ep *epn)
1459 {
1460 usbf_ep_dma_reg_bitclr(epn, USBF_REG_DMA_EPN_DCR1, USBF_SYS_EPN_REQEN);
1461
1462 /* In the datasheet:
1463 * If EP[m]_REQEN = 0b is set during DMA transfer, AHB-EPC stops DMA
1464 * after 1 packet transfer completed.
1465 * Therefore, wait sufficient time for ensuring DMA transfer
1466 * completion. The WAIT time depends on the system, especially AHB
1467 * bus activity
1468 * So arbitrary 10ms would be sufficient.
1469 */
1470 mdelay(10);
1471
1472 usbf_ep_reg_bitclr(epn, USBF_REG_EPN_DMA_CTRL, USBF_EPN_DMA_EN);
1473 }
1474
usbf_epn_dma_abort(struct usbf_ep * epn,struct usbf_req * req)1475 static void usbf_epn_dma_abort(struct usbf_ep *epn, struct usbf_req *req)
1476 {
1477 dev_dbg(epn->udc->dev, "ep%u %s dma abort\n", epn->id,
1478 epn->is_in ? "in" : "out");
1479
1480 epn->bridge_on_dma_end = NULL;
1481
1482 usbf_epn_dma_stop(epn);
1483
1484 usb_gadget_unmap_request(&epn->udc->gadget, &req->req,
1485 epn->is_in ? 1 : 0);
1486 req->is_mapped = 0;
1487
1488 usbf_ep_reg_bitclr(epn, USBF_REG_EPN_CONTROL, USBF_EPN_AUTO);
1489
1490 if (epn->is_in) {
1491 usbf_ep_reg_clrset(epn, USBF_REG_EPN_INT_ENA,
1492 USBF_EPN_IN_END_EN,
1493 USBF_EPN_IN_EN);
1494 } else {
1495 usbf_ep_reg_clrset(epn, USBF_REG_EPN_INT_ENA,
1496 USBF_EPN_OUT_END_EN,
1497 USBF_EPN_OUT_EN | USBF_EPN_OUT_NULL_EN);
1498 }
1499
1500 /* As dma is stopped, be sure that no DMA interrupt are pending */
1501 usbf_ep_reg_writel(epn, USBF_REG_EPN_STATUS,
1502 USBF_EPN_IN_END_INT | USBF_EPN_OUT_END_INT);
1503
1504 usbf_reg_writel(epn->udc, USBF_REG_AHBBINT, USBF_SYS_DMA_ENDINT_EPN(epn->id));
1505
1506 /* Enable DMA interrupt the bridge level */
1507 usbf_reg_bitset(epn->udc, USBF_REG_AHBBINTEN,
1508 USBF_SYS_DMA_ENDINTEN_EPN(epn->id));
1509
1510 /* Reset transfer step */
1511 req->xfer_step = USBF_XFER_START;
1512 }
1513
usbf_epn_fifo_flush(struct usbf_ep * epn)1514 static void usbf_epn_fifo_flush(struct usbf_ep *epn)
1515 {
1516 u32 ctrl;
1517 u32 sts;
1518 int ret;
1519
1520 dev_dbg(epn->udc->dev, "ep%u %s fifo flush\n", epn->id,
1521 epn->is_in ? "in" : "out");
1522
1523 ctrl = usbf_ep_reg_readl(epn, USBF_REG_EPN_CONTROL);
1524 usbf_ep_reg_writel(epn, USBF_REG_EPN_CONTROL, ctrl | USBF_EPN_BCLR);
1525
1526 if (ctrl & USBF_EPN_DIR0)
1527 return;
1528
1529 ret = readl_poll_timeout_atomic(epn->regs + USBF_REG_EPN_STATUS, sts,
1530 (sts & (USBF_EPN_IN_DATA | USBF_EPN_IN_EMPTY)) == USBF_EPN_IN_EMPTY,
1531 0, 10000);
1532 if (ret)
1533 dev_err(epn->udc->dev, "ep%u flush fifo timed out\n", epn->id);
1534 }
1535
usbf_ep_req_done(struct usbf_ep * ep,struct usbf_req * req,int status)1536 static void usbf_ep_req_done(struct usbf_ep *ep, struct usbf_req *req,
1537 int status)
1538 {
1539 list_del_init(&req->queue);
1540
1541 if (status) {
1542 req->req.status = status;
1543 } else {
1544 if (req->req.status == -EINPROGRESS)
1545 req->req.status = status;
1546 }
1547
1548 dev_dbg(ep->udc->dev, "ep%u %s req done length %u/%u, status=%d\n", ep->id,
1549 ep->is_in ? "in" : "out",
1550 req->req.actual, req->req.length, req->req.status);
1551
1552 if (req->is_mapped)
1553 usbf_epn_dma_abort(ep, req);
1554
1555 spin_unlock(&ep->udc->lock);
1556 usb_gadget_giveback_request(&ep->ep, &req->req);
1557 spin_lock(&ep->udc->lock);
1558 }
1559
usbf_ep_nuke(struct usbf_ep * ep,int status)1560 static void usbf_ep_nuke(struct usbf_ep *ep, int status)
1561 {
1562 struct usbf_req *req;
1563
1564 dev_dbg(ep->udc->dev, "ep%u %s nuke status %d\n", ep->id,
1565 ep->is_in ? "in" : "out",
1566 status);
1567
1568 while (!list_empty(&ep->queue)) {
1569 req = list_first_entry(&ep->queue, struct usbf_req, queue);
1570 usbf_ep_req_done(ep, req, status);
1571 }
1572
1573 if (ep->id == 0)
1574 usbf_ep0_fifo_flush(ep);
1575 else
1576 usbf_epn_fifo_flush(ep);
1577 }
1578
usbf_ep_is_stalled(struct usbf_ep * ep)1579 static bool usbf_ep_is_stalled(struct usbf_ep *ep)
1580 {
1581 u32 ctrl;
1582
1583 if (ep->id == 0) {
1584 ctrl = usbf_ep_reg_readl(ep, USBF_REG_EP0_CONTROL);
1585 return (ctrl & USBF_EP0_STL) ? true : false;
1586 }
1587
1588 ctrl = usbf_ep_reg_readl(ep, USBF_REG_EPN_CONTROL);
1589 if (ep->is_in)
1590 return (ctrl & USBF_EPN_ISTL) ? true : false;
1591
1592 return (ctrl & USBF_EPN_OSTL) ? true : false;
1593 }
1594
usbf_epn_start_queue(struct usbf_ep * epn)1595 static int usbf_epn_start_queue(struct usbf_ep *epn)
1596 {
1597 struct usbf_req *req;
1598 int ret;
1599
1600 if (usbf_ep_is_stalled(epn))
1601 return 0;
1602
1603 req = list_first_entry_or_null(&epn->queue, struct usbf_req, queue);
1604
1605 if (epn->is_in) {
1606 if (req && !epn->is_processing) {
1607 ret = epn->dma_regs ?
1608 usbf_epn_dma_in(epn, req) :
1609 usbf_epn_pio_in(epn, req);
1610 if (ret != -EINPROGRESS) {
1611 dev_err(epn->udc->dev,
1612 "queued next request not in progress\n");
1613 /* The request cannot be completed (ie
1614 * ret == 0) on the first call.
1615 * stall and nuke the endpoint
1616 */
1617 return ret ? ret : -EIO;
1618 }
1619 }
1620 } else {
1621 if (req) {
1622 /* Clear ONAK to accept OUT tokens */
1623 usbf_ep_reg_bitclr(epn, USBF_REG_EPN_CONTROL,
1624 USBF_EPN_ONAK);
1625
1626 /* Enable interrupts */
1627 usbf_ep_reg_bitset(epn, USBF_REG_EPN_INT_ENA,
1628 USBF_EPN_OUT_INT | USBF_EPN_OUT_NULL_INT);
1629 } else {
1630 /* Disable incoming data and interrupt.
1631 * They will be enable on next usb_eb_queue call
1632 */
1633 usbf_ep_reg_bitset(epn, USBF_REG_EPN_CONTROL,
1634 USBF_EPN_ONAK);
1635 usbf_ep_reg_bitclr(epn, USBF_REG_EPN_INT_ENA,
1636 USBF_EPN_OUT_INT | USBF_EPN_OUT_NULL_INT);
1637 }
1638 }
1639 return 0;
1640 }
1641
usbf_ep_process_queue(struct usbf_ep * ep)1642 static int usbf_ep_process_queue(struct usbf_ep *ep)
1643 {
1644 int (*usbf_ep_xfer)(struct usbf_ep *ep, struct usbf_req *req);
1645 struct usbf_req *req;
1646 int is_processing;
1647 int ret;
1648
1649 if (ep->is_in) {
1650 usbf_ep_xfer = usbf_ep0_pio_in;
1651 if (ep->id) {
1652 usbf_ep_xfer = ep->dma_regs ?
1653 usbf_epn_dma_in : usbf_epn_pio_in;
1654 }
1655 } else {
1656 usbf_ep_xfer = usbf_ep0_pio_out;
1657 if (ep->id) {
1658 usbf_ep_xfer = ep->dma_regs ?
1659 usbf_epn_dma_out : usbf_epn_pio_out;
1660 }
1661 }
1662
1663 req = list_first_entry_or_null(&ep->queue, struct usbf_req, queue);
1664 if (!req) {
1665 dev_err(ep->udc->dev,
1666 "no request available for ep%u %s process\n", ep->id,
1667 ep->is_in ? "in" : "out");
1668 return -ENOENT;
1669 }
1670
1671 do {
1672 /* Were going to read the FIFO for this current request.
1673 * NAK any other incoming data to avoid a race condition if no
1674 * more request are available.
1675 */
1676 if (!ep->is_in && ep->id != 0) {
1677 usbf_ep_reg_bitset(ep, USBF_REG_EPN_CONTROL,
1678 USBF_EPN_ONAK);
1679 }
1680
1681 ret = usbf_ep_xfer(ep, req);
1682 if (ret == -EINPROGRESS) {
1683 if (!ep->is_in && ep->id != 0) {
1684 /* The current request needs more data.
1685 * Allow incoming data
1686 */
1687 usbf_ep_reg_bitclr(ep, USBF_REG_EPN_CONTROL,
1688 USBF_EPN_ONAK);
1689 }
1690 return ret;
1691 }
1692
1693 is_processing = ep->is_processing;
1694 ep->is_processing = 1;
1695 usbf_ep_req_done(ep, req, ret);
1696 ep->is_processing = is_processing;
1697
1698 if (ret) {
1699 /* An error was detected during the request transfer.
1700 * Any pending DMA transfers were aborted by the
1701 * usbf_ep_req_done() call.
1702 * It's time to flush the fifo
1703 */
1704 if (ep->id == 0)
1705 usbf_ep0_fifo_flush(ep);
1706 else
1707 usbf_epn_fifo_flush(ep);
1708 }
1709
1710 req = list_first_entry_or_null(&ep->queue, struct usbf_req,
1711 queue);
1712
1713 if (ep->is_in)
1714 continue;
1715
1716 if (ep->id != 0) {
1717 if (req) {
1718 /* An other request is available.
1719 * Allow incoming data
1720 */
1721 usbf_ep_reg_bitclr(ep, USBF_REG_EPN_CONTROL,
1722 USBF_EPN_ONAK);
1723 } else {
1724 /* No request queued. Disable interrupts.
1725 * They will be enabled on usb_ep_queue
1726 */
1727 usbf_ep_reg_bitclr(ep, USBF_REG_EPN_INT_ENA,
1728 USBF_EPN_OUT_INT | USBF_EPN_OUT_NULL_INT);
1729 }
1730 }
1731 /* Do not recall usbf_ep_xfer() */
1732 return req ? -EINPROGRESS : 0;
1733
1734 } while (req);
1735
1736 return 0;
1737 }
1738
usbf_ep_stall(struct usbf_ep * ep,bool stall)1739 static void usbf_ep_stall(struct usbf_ep *ep, bool stall)
1740 {
1741 struct usbf_req *first;
1742
1743 dev_dbg(ep->udc->dev, "ep%u %s %s\n", ep->id,
1744 ep->is_in ? "in" : "out",
1745 stall ? "stall" : "unstall");
1746
1747 if (ep->id == 0) {
1748 if (stall)
1749 usbf_ep_reg_bitset(ep, USBF_REG_EP0_CONTROL, USBF_EP0_STL);
1750 else
1751 usbf_ep_reg_bitclr(ep, USBF_REG_EP0_CONTROL, USBF_EP0_STL);
1752 return;
1753 }
1754
1755 if (stall) {
1756 if (ep->is_in)
1757 usbf_ep_reg_bitset(ep, USBF_REG_EPN_CONTROL,
1758 USBF_EPN_ISTL);
1759 else
1760 usbf_ep_reg_bitset(ep, USBF_REG_EPN_CONTROL,
1761 USBF_EPN_OSTL | USBF_EPN_OSTL_EN);
1762 } else {
1763 first = list_first_entry_or_null(&ep->queue, struct usbf_req, queue);
1764 if (first && first->is_mapped) {
1765 /* This can appear if the host halts an endpoint using
1766 * SET_FEATURE and then un-halts the endpoint
1767 */
1768 usbf_epn_dma_abort(ep, first);
1769 }
1770 usbf_epn_fifo_flush(ep);
1771 if (ep->is_in) {
1772 usbf_ep_reg_clrset(ep, USBF_REG_EPN_CONTROL,
1773 USBF_EPN_ISTL,
1774 USBF_EPN_IPIDCLR);
1775 } else {
1776 usbf_ep_reg_clrset(ep, USBF_REG_EPN_CONTROL,
1777 USBF_EPN_OSTL,
1778 USBF_EPN_OSTL_EN | USBF_EPN_OPIDCLR);
1779 }
1780 usbf_epn_start_queue(ep);
1781 }
1782 }
1783
usbf_ep0_enable(struct usbf_ep * ep0)1784 static void usbf_ep0_enable(struct usbf_ep *ep0)
1785 {
1786 usbf_ep_reg_writel(ep0, USBF_REG_EP0_CONTROL, USBF_EP0_INAK_EN | USBF_EP0_BCLR);
1787
1788 usbf_ep_reg_writel(ep0, USBF_REG_EP0_INT_ENA,
1789 USBF_EP0_SETUP_EN | USBF_EP0_STG_START_EN | USBF_EP0_STG_END_EN |
1790 USBF_EP0_OUT_EN | USBF_EP0_OUT_NULL_EN | USBF_EP0_IN_EN);
1791
1792 ep0->udc->ep0state = EP0_IDLE;
1793 ep0->disabled = 0;
1794
1795 /* enable interrupts for the ep0 */
1796 usbf_reg_bitset(ep0->udc, USBF_REG_USB_INT_ENA, USBF_USB_EPN_EN(0));
1797 }
1798
usbf_epn_enable(struct usbf_ep * epn)1799 static int usbf_epn_enable(struct usbf_ep *epn)
1800 {
1801 u32 base_addr;
1802 u32 ctrl;
1803
1804 base_addr = usbf_ep_info[epn->id].base_addr;
1805 usbf_ep_reg_writel(epn, USBF_REG_EPN_PCKT_ADRS,
1806 USBF_EPN_BASEAD(base_addr) | USBF_EPN_MPKT(epn->ep.maxpacket));
1807
1808 /* OUT transfer interrupt are enabled during usb_ep_queue */
1809 if (epn->is_in) {
1810 /* Will be changed in DMA processing */
1811 usbf_ep_reg_writel(epn, USBF_REG_EPN_INT_ENA, USBF_EPN_IN_EN);
1812 }
1813
1814 /* Clear, set endpoint direction, set IN/OUT STL, and enable
1815 * Send NAK for Data out as request are not queued yet
1816 */
1817 ctrl = USBF_EPN_EN | USBF_EPN_BCLR;
1818 if (epn->is_in)
1819 ctrl |= USBF_EPN_OSTL | USBF_EPN_OSTL_EN;
1820 else
1821 ctrl |= USBF_EPN_DIR0 | USBF_EPN_ISTL | USBF_EPN_OSTL_EN | USBF_EPN_ONAK;
1822 usbf_ep_reg_writel(epn, USBF_REG_EPN_CONTROL, ctrl);
1823
1824 return 0;
1825 }
1826
usbf_ep_enable(struct usb_ep * _ep,const struct usb_endpoint_descriptor * desc)1827 static int usbf_ep_enable(struct usb_ep *_ep,
1828 const struct usb_endpoint_descriptor *desc)
1829 {
1830 struct usbf_ep *ep = container_of(_ep, struct usbf_ep, ep);
1831 struct usbf_udc *udc = ep->udc;
1832 unsigned long flags;
1833 int ret;
1834
1835 if (ep->id == 0)
1836 return -EINVAL;
1837
1838 if (!desc || desc->bDescriptorType != USB_DT_ENDPOINT)
1839 return -EINVAL;
1840
1841 dev_dbg(ep->udc->dev, "ep%u %s mpkts %d\n", ep->id,
1842 usb_endpoint_dir_in(desc) ? "in" : "out",
1843 usb_endpoint_maxp(desc));
1844
1845 spin_lock_irqsave(&ep->udc->lock, flags);
1846 ep->is_in = usb_endpoint_dir_in(desc);
1847 ep->ep.maxpacket = usb_endpoint_maxp(desc);
1848
1849 ret = usbf_epn_enable(ep);
1850 if (ret)
1851 goto end;
1852
1853 ep->disabled = 0;
1854
1855 /* enable interrupts for this endpoint */
1856 usbf_reg_bitset(udc, USBF_REG_USB_INT_ENA, USBF_USB_EPN_EN(ep->id));
1857
1858 /* enable DMA interrupt at bridge level if DMA is used */
1859 if (ep->dma_regs) {
1860 ep->bridge_on_dma_end = NULL;
1861 usbf_reg_bitset(udc, USBF_REG_AHBBINTEN,
1862 USBF_SYS_DMA_ENDINTEN_EPN(ep->id));
1863 }
1864
1865 ret = 0;
1866 end:
1867 spin_unlock_irqrestore(&ep->udc->lock, flags);
1868 return ret;
1869 }
1870
usbf_epn_disable(struct usbf_ep * epn)1871 static int usbf_epn_disable(struct usbf_ep *epn)
1872 {
1873 /* Disable interrupts */
1874 usbf_ep_reg_writel(epn, USBF_REG_EPN_INT_ENA, 0);
1875
1876 /* Disable endpoint */
1877 usbf_ep_reg_bitclr(epn, USBF_REG_EPN_CONTROL, USBF_EPN_EN);
1878
1879 /* remove anything that was pending */
1880 usbf_ep_nuke(epn, -ESHUTDOWN);
1881
1882 return 0;
1883 }
1884
usbf_ep_disable(struct usb_ep * _ep)1885 static int usbf_ep_disable(struct usb_ep *_ep)
1886 {
1887 struct usbf_ep *ep = container_of(_ep, struct usbf_ep, ep);
1888 struct usbf_udc *udc = ep->udc;
1889 unsigned long flags;
1890 int ret;
1891
1892 if (ep->id == 0)
1893 return -EINVAL;
1894
1895 dev_dbg(ep->udc->dev, "ep%u %s mpkts %d\n", ep->id,
1896 ep->is_in ? "in" : "out", ep->ep.maxpacket);
1897
1898 spin_lock_irqsave(&ep->udc->lock, flags);
1899 ep->disabled = 1;
1900 /* Disable DMA interrupt */
1901 if (ep->dma_regs) {
1902 usbf_reg_bitclr(udc, USBF_REG_AHBBINTEN,
1903 USBF_SYS_DMA_ENDINTEN_EPN(ep->id));
1904 ep->bridge_on_dma_end = NULL;
1905 }
1906 /* disable interrupts for this endpoint */
1907 usbf_reg_bitclr(udc, USBF_REG_USB_INT_ENA, USBF_USB_EPN_EN(ep->id));
1908 /* and the endpoint itself */
1909 ret = usbf_epn_disable(ep);
1910 spin_unlock_irqrestore(&ep->udc->lock, flags);
1911
1912 return ret;
1913 }
1914
usbf_ep0_queue(struct usbf_ep * ep0,struct usbf_req * req,gfp_t gfp_flags)1915 static int usbf_ep0_queue(struct usbf_ep *ep0, struct usbf_req *req,
1916 gfp_t gfp_flags)
1917 {
1918 int ret;
1919
1920 req->req.actual = 0;
1921 req->req.status = -EINPROGRESS;
1922 req->is_zero_sent = 0;
1923
1924 list_add_tail(&req->queue, &ep0->queue);
1925
1926 if (ep0->udc->ep0state == EP0_IN_STATUS_START_PHASE)
1927 return 0;
1928
1929 if (!ep0->is_in)
1930 return 0;
1931
1932 if (ep0->udc->ep0state == EP0_IN_STATUS_PHASE) {
1933 if (req->req.length) {
1934 dev_err(ep0->udc->dev,
1935 "request lng %u for ep0 in status phase\n",
1936 req->req.length);
1937 return -EINVAL;
1938 }
1939 ep0->delayed_status = 0;
1940 }
1941 if (!ep0->is_processing) {
1942 ret = usbf_ep0_pio_in(ep0, req);
1943 if (ret != -EINPROGRESS) {
1944 dev_err(ep0->udc->dev,
1945 "queued request not in progress\n");
1946 /* The request cannot be completed (ie
1947 * ret == 0) on the first call
1948 */
1949 return ret ? ret : -EIO;
1950 }
1951 }
1952
1953 return 0;
1954 }
1955
usbf_epn_queue(struct usbf_ep * ep,struct usbf_req * req,gfp_t gfp_flags)1956 static int usbf_epn_queue(struct usbf_ep *ep, struct usbf_req *req,
1957 gfp_t gfp_flags)
1958 {
1959 int was_empty;
1960 int ret;
1961
1962 if (ep->disabled) {
1963 dev_err(ep->udc->dev, "ep%u request queue while disable\n",
1964 ep->id);
1965 return -ESHUTDOWN;
1966 }
1967
1968 req->req.actual = 0;
1969 req->req.status = -EINPROGRESS;
1970 req->is_zero_sent = 0;
1971 req->xfer_step = USBF_XFER_START;
1972
1973 was_empty = list_empty(&ep->queue);
1974 list_add_tail(&req->queue, &ep->queue);
1975 if (was_empty) {
1976 ret = usbf_epn_start_queue(ep);
1977 if (ret)
1978 return ret;
1979 }
1980 return 0;
1981 }
1982
usbf_ep_queue(struct usb_ep * _ep,struct usb_request * _req,gfp_t gfp_flags)1983 static int usbf_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
1984 gfp_t gfp_flags)
1985 {
1986 struct usbf_req *req = container_of(_req, struct usbf_req, req);
1987 struct usbf_ep *ep = container_of(_ep, struct usbf_ep, ep);
1988 struct usbf_udc *udc = ep->udc;
1989 unsigned long flags;
1990 int ret;
1991
1992 if (!_req || !_req->buf)
1993 return -EINVAL;
1994
1995 if (!udc || !udc->driver)
1996 return -EINVAL;
1997
1998 dev_dbg(ep->udc->dev, "ep%u %s req queue length %u, zero %u, short_not_ok %u\n",
1999 ep->id, ep->is_in ? "in" : "out",
2000 req->req.length, req->req.zero, req->req.short_not_ok);
2001
2002 spin_lock_irqsave(&ep->udc->lock, flags);
2003 if (ep->id == 0)
2004 ret = usbf_ep0_queue(ep, req, gfp_flags);
2005 else
2006 ret = usbf_epn_queue(ep, req, gfp_flags);
2007 spin_unlock_irqrestore(&ep->udc->lock, flags);
2008 return ret;
2009 }
2010
usbf_ep_dequeue(struct usb_ep * _ep,struct usb_request * _req)2011 static int usbf_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
2012 {
2013 struct usbf_req *req = container_of(_req, struct usbf_req, req);
2014 struct usbf_ep *ep = container_of(_ep, struct usbf_ep, ep);
2015 unsigned long flags;
2016 int is_processing;
2017 int first;
2018 int ret;
2019
2020 spin_lock_irqsave(&ep->udc->lock, flags);
2021
2022 dev_dbg(ep->udc->dev, "ep%u %s req dequeue length %u/%u\n",
2023 ep->id, ep->is_in ? "in" : "out",
2024 req->req.actual, req->req.length);
2025
2026 first = list_is_first(&req->queue, &ep->queue);
2027
2028 /* Complete the request but avoid any operation that could be done
2029 * if a new request is queued during the request completion
2030 */
2031 is_processing = ep->is_processing;
2032 ep->is_processing = 1;
2033 usbf_ep_req_done(ep, req, -ECONNRESET);
2034 ep->is_processing = is_processing;
2035
2036 if (first) {
2037 /* The first item in the list was dequeued.
2038 * This item could already be submitted to the hardware.
2039 * So, flush the fifo
2040 */
2041 if (ep->id)
2042 usbf_epn_fifo_flush(ep);
2043 else
2044 usbf_ep0_fifo_flush(ep);
2045 }
2046
2047 if (ep->id == 0) {
2048 /* We dequeue a request on ep0. On this endpoint, we can have
2049 * 1 request related to the data stage and/or 1 request
2050 * related to the status stage.
2051 * We dequeue one of them and so the USB control transaction
2052 * is no more coherent. The simple way to be consistent after
2053 * dequeuing is to stall and nuke the endpoint and wait the
2054 * next SETUP packet.
2055 */
2056 usbf_ep_stall(ep, true);
2057 usbf_ep_nuke(ep, -ECONNRESET);
2058 ep->udc->ep0state = EP0_IDLE;
2059 goto end;
2060 }
2061
2062 if (!first)
2063 goto end;
2064
2065 ret = usbf_epn_start_queue(ep);
2066 if (ret) {
2067 usbf_ep_stall(ep, true);
2068 usbf_ep_nuke(ep, -EIO);
2069 }
2070 end:
2071 spin_unlock_irqrestore(&ep->udc->lock, flags);
2072 return 0;
2073 }
2074
usbf_ep_alloc_request(struct usb_ep * _ep,gfp_t gfp_flags)2075 static struct usb_request *usbf_ep_alloc_request(struct usb_ep *_ep,
2076 gfp_t gfp_flags)
2077 {
2078 struct usbf_req *req;
2079
2080 if (!_ep)
2081 return NULL;
2082
2083 req = kzalloc_obj(*req, gfp_flags);
2084 if (!req)
2085 return NULL;
2086
2087 INIT_LIST_HEAD(&req->queue);
2088
2089 return &req->req;
2090 }
2091
usbf_ep_free_request(struct usb_ep * _ep,struct usb_request * _req)2092 static void usbf_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
2093 {
2094 struct usbf_req *req;
2095 unsigned long flags;
2096 struct usbf_ep *ep;
2097
2098 if (!_ep || !_req)
2099 return;
2100
2101 req = container_of(_req, struct usbf_req, req);
2102 ep = container_of(_ep, struct usbf_ep, ep);
2103
2104 spin_lock_irqsave(&ep->udc->lock, flags);
2105 list_del_init(&req->queue);
2106 spin_unlock_irqrestore(&ep->udc->lock, flags);
2107 kfree(req);
2108 }
2109
usbf_ep_set_halt(struct usb_ep * _ep,int halt)2110 static int usbf_ep_set_halt(struct usb_ep *_ep, int halt)
2111 {
2112 struct usbf_ep *ep = container_of(_ep, struct usbf_ep, ep);
2113 unsigned long flags;
2114 int ret;
2115
2116 if (ep->id == 0)
2117 return -EINVAL;
2118
2119 spin_lock_irqsave(&ep->udc->lock, flags);
2120
2121 if (!list_empty(&ep->queue)) {
2122 ret = -EAGAIN;
2123 goto end;
2124 }
2125
2126 usbf_ep_stall(ep, halt);
2127 if (!halt)
2128 ep->is_wedged = 0;
2129
2130 ret = 0;
2131 end:
2132 spin_unlock_irqrestore(&ep->udc->lock, flags);
2133
2134 return ret;
2135 }
2136
usbf_ep_set_wedge(struct usb_ep * _ep)2137 static int usbf_ep_set_wedge(struct usb_ep *_ep)
2138 {
2139 struct usbf_ep *ep = container_of(_ep, struct usbf_ep, ep);
2140 unsigned long flags;
2141 int ret;
2142
2143 if (ep->id == 0)
2144 return -EINVAL;
2145
2146 spin_lock_irqsave(&ep->udc->lock, flags);
2147 if (!list_empty(&ep->queue)) {
2148 ret = -EAGAIN;
2149 goto end;
2150 }
2151 usbf_ep_stall(ep, 1);
2152 ep->is_wedged = 1;
2153
2154 ret = 0;
2155 end:
2156 spin_unlock_irqrestore(&ep->udc->lock, flags);
2157 return ret;
2158 }
2159
2160 static struct usb_ep_ops usbf_ep_ops = {
2161 .enable = usbf_ep_enable,
2162 .disable = usbf_ep_disable,
2163 .queue = usbf_ep_queue,
2164 .dequeue = usbf_ep_dequeue,
2165 .set_halt = usbf_ep_set_halt,
2166 .set_wedge = usbf_ep_set_wedge,
2167 .alloc_request = usbf_ep_alloc_request,
2168 .free_request = usbf_ep_free_request,
2169 };
2170
usbf_ep0_req_complete(struct usb_ep * _ep,struct usb_request * _req)2171 static void usbf_ep0_req_complete(struct usb_ep *_ep, struct usb_request *_req)
2172 {
2173 }
2174
usbf_ep0_fill_req(struct usbf_ep * ep0,struct usbf_req * req,void * buf,unsigned int length,void (* complete)(struct usb_ep * _ep,struct usb_request * _req))2175 static void usbf_ep0_fill_req(struct usbf_ep *ep0, struct usbf_req *req,
2176 void *buf, unsigned int length,
2177 void (*complete)(struct usb_ep *_ep,
2178 struct usb_request *_req))
2179 {
2180 if (buf && length)
2181 memcpy(ep0->udc->ep0_buf, buf, length);
2182
2183 req->req.buf = ep0->udc->ep0_buf;
2184 req->req.length = length;
2185 req->req.dma = 0;
2186 req->req.zero = true;
2187 req->req.complete = complete ? complete : usbf_ep0_req_complete;
2188 req->req.status = -EINPROGRESS;
2189 req->req.context = NULL;
2190 req->req.actual = 0;
2191 }
2192
usbf_get_ep_by_addr(struct usbf_udc * udc,u8 address)2193 static struct usbf_ep *usbf_get_ep_by_addr(struct usbf_udc *udc, u8 address)
2194 {
2195 struct usbf_ep *ep;
2196 unsigned int i;
2197
2198 if ((address & USB_ENDPOINT_NUMBER_MASK) == 0)
2199 return &udc->ep[0];
2200
2201 for (i = 1; i < ARRAY_SIZE(udc->ep); i++) {
2202 ep = &udc->ep[i];
2203
2204 if (!ep->ep.desc)
2205 continue;
2206
2207 if (ep->ep.desc->bEndpointAddress == address)
2208 return ep;
2209 }
2210
2211 return NULL;
2212 }
2213
usbf_req_delegate(struct usbf_udc * udc,const struct usb_ctrlrequest * ctrlrequest)2214 static int usbf_req_delegate(struct usbf_udc *udc,
2215 const struct usb_ctrlrequest *ctrlrequest)
2216 {
2217 int ret;
2218
2219 spin_unlock(&udc->lock);
2220 ret = udc->driver->setup(&udc->gadget, ctrlrequest);
2221 spin_lock(&udc->lock);
2222 if (ret < 0) {
2223 dev_dbg(udc->dev, "udc driver setup failed %d\n", ret);
2224 return ret;
2225 }
2226 if (ret == USB_GADGET_DELAYED_STATUS) {
2227 dev_dbg(udc->dev, "delayed status set\n");
2228 udc->ep[0].delayed_status = 1;
2229 return 0;
2230 }
2231 return ret;
2232 }
2233
usbf_req_get_status(struct usbf_udc * udc,const struct usb_ctrlrequest * ctrlrequest)2234 static int usbf_req_get_status(struct usbf_udc *udc,
2235 const struct usb_ctrlrequest *ctrlrequest)
2236 {
2237 struct usbf_ep *ep;
2238 u16 status_data;
2239 u16 wLength;
2240 u16 wValue;
2241 u16 wIndex;
2242
2243 wValue = le16_to_cpu(ctrlrequest->wValue);
2244 wLength = le16_to_cpu(ctrlrequest->wLength);
2245 wIndex = le16_to_cpu(ctrlrequest->wIndex);
2246
2247 switch (ctrlrequest->bRequestType) {
2248 case USB_DIR_IN | USB_RECIP_DEVICE | USB_TYPE_STANDARD:
2249 if ((wValue != 0) || (wIndex != 0) || (wLength != 2))
2250 goto delegate;
2251
2252 status_data = 0;
2253 if (udc->gadget.is_selfpowered)
2254 status_data |= BIT(USB_DEVICE_SELF_POWERED);
2255
2256 if (udc->is_remote_wakeup)
2257 status_data |= BIT(USB_DEVICE_REMOTE_WAKEUP);
2258
2259 break;
2260
2261 case USB_DIR_IN | USB_RECIP_ENDPOINT | USB_TYPE_STANDARD:
2262 if ((wValue != 0) || (wLength != 2))
2263 goto delegate;
2264
2265 ep = usbf_get_ep_by_addr(udc, wIndex);
2266 if (!ep)
2267 return -EINVAL;
2268
2269 status_data = 0;
2270 if (usbf_ep_is_stalled(ep))
2271 status_data |= cpu_to_le16(1);
2272 break;
2273
2274 case USB_DIR_IN | USB_RECIP_INTERFACE | USB_TYPE_STANDARD:
2275 if ((wValue != 0) || (wLength != 2))
2276 goto delegate;
2277 status_data = 0;
2278 break;
2279
2280 default:
2281 goto delegate;
2282 }
2283
2284 usbf_ep0_fill_req(&udc->ep[0], &udc->setup_reply, &status_data,
2285 sizeof(status_data), NULL);
2286 usbf_ep0_queue(&udc->ep[0], &udc->setup_reply, GFP_ATOMIC);
2287
2288 return 0;
2289
2290 delegate:
2291 return usbf_req_delegate(udc, ctrlrequest);
2292 }
2293
usbf_req_clear_set_feature(struct usbf_udc * udc,const struct usb_ctrlrequest * ctrlrequest,bool is_set)2294 static int usbf_req_clear_set_feature(struct usbf_udc *udc,
2295 const struct usb_ctrlrequest *ctrlrequest,
2296 bool is_set)
2297 {
2298 struct usbf_ep *ep;
2299 u16 wLength;
2300 u16 wValue;
2301 u16 wIndex;
2302
2303 wValue = le16_to_cpu(ctrlrequest->wValue);
2304 wLength = le16_to_cpu(ctrlrequest->wLength);
2305 wIndex = le16_to_cpu(ctrlrequest->wIndex);
2306
2307 switch (ctrlrequest->bRequestType) {
2308 case USB_DIR_OUT | USB_RECIP_DEVICE:
2309 if ((wIndex != 0) || (wLength != 0))
2310 goto delegate;
2311
2312 if (wValue != cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
2313 goto delegate;
2314
2315 udc->is_remote_wakeup = is_set;
2316 break;
2317
2318 case USB_DIR_OUT | USB_RECIP_ENDPOINT:
2319 if (wLength != 0)
2320 goto delegate;
2321
2322 ep = usbf_get_ep_by_addr(udc, wIndex);
2323 if (!ep)
2324 return -EINVAL;
2325
2326 if ((ep->id == 0) && is_set) {
2327 /* Endpoint 0 cannot be halted (stalled)
2328 * Returning an error code leads to a STALL on this ep0
2329 * but keep the automate in a consistent state.
2330 */
2331 return -EINVAL;
2332 }
2333 if (ep->is_wedged && !is_set) {
2334 /* Ignore CLEAR_FEATURE(HALT ENDPOINT) when the
2335 * endpoint is wedged
2336 */
2337 break;
2338 }
2339 usbf_ep_stall(ep, is_set);
2340 break;
2341
2342 default:
2343 goto delegate;
2344 }
2345
2346 return 0;
2347
2348 delegate:
2349 return usbf_req_delegate(udc, ctrlrequest);
2350 }
2351
usbf_ep0_req_set_address_complete(struct usb_ep * _ep,struct usb_request * _req)2352 static void usbf_ep0_req_set_address_complete(struct usb_ep *_ep,
2353 struct usb_request *_req)
2354 {
2355 struct usbf_ep *ep = container_of(_ep, struct usbf_ep, ep);
2356
2357 /* The status phase of the SET_ADDRESS request is completed ... */
2358 if (_req->status == 0) {
2359 /* ... without any errors -> Signaled the state to the core. */
2360 usb_gadget_set_state(&ep->udc->gadget, USB_STATE_ADDRESS);
2361 }
2362
2363 /* In case of request failure, there is no need to revert the address
2364 * value set to the hardware as the hardware will take care of the
2365 * value only if the status stage is completed normally.
2366 */
2367 }
2368
usbf_req_set_address(struct usbf_udc * udc,const struct usb_ctrlrequest * ctrlrequest)2369 static int usbf_req_set_address(struct usbf_udc *udc,
2370 const struct usb_ctrlrequest *ctrlrequest)
2371 {
2372 u16 wLength;
2373 u16 wValue;
2374 u16 wIndex;
2375 u32 addr;
2376
2377 wValue = le16_to_cpu(ctrlrequest->wValue);
2378 wLength = le16_to_cpu(ctrlrequest->wLength);
2379 wIndex = le16_to_cpu(ctrlrequest->wIndex);
2380
2381 if (ctrlrequest->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
2382 goto delegate;
2383
2384 if ((wIndex != 0) || (wLength != 0) || (wValue > 127))
2385 return -EINVAL;
2386
2387 addr = wValue;
2388 /* The hardware will take care of this USB address after the status
2389 * stage of the SET_ADDRESS request is completed normally.
2390 * It is safe to write it now
2391 */
2392 usbf_reg_writel(udc, USBF_REG_USB_ADDRESS, USBF_USB_SET_USB_ADDR(addr));
2393
2394 /* Queued the status request */
2395 usbf_ep0_fill_req(&udc->ep[0], &udc->setup_reply, NULL, 0,
2396 usbf_ep0_req_set_address_complete);
2397 usbf_ep0_queue(&udc->ep[0], &udc->setup_reply, GFP_ATOMIC);
2398
2399 return 0;
2400
2401 delegate:
2402 return usbf_req_delegate(udc, ctrlrequest);
2403 }
2404
usbf_req_set_configuration(struct usbf_udc * udc,const struct usb_ctrlrequest * ctrlrequest)2405 static int usbf_req_set_configuration(struct usbf_udc *udc,
2406 const struct usb_ctrlrequest *ctrlrequest)
2407 {
2408 u16 wLength;
2409 u16 wValue;
2410 u16 wIndex;
2411 int ret;
2412
2413 ret = usbf_req_delegate(udc, ctrlrequest);
2414 if (ret)
2415 return ret;
2416
2417 wValue = le16_to_cpu(ctrlrequest->wValue);
2418 wLength = le16_to_cpu(ctrlrequest->wLength);
2419 wIndex = le16_to_cpu(ctrlrequest->wIndex);
2420
2421 if ((ctrlrequest->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE)) ||
2422 (wIndex != 0) || (wLength != 0)) {
2423 /* No error detected by driver->setup() but it is not an USB2.0
2424 * Ch9 SET_CONFIGURATION.
2425 * Nothing more to do
2426 */
2427 return 0;
2428 }
2429
2430 if (wValue & 0x00FF) {
2431 usbf_reg_bitset(udc, USBF_REG_USB_CONTROL, USBF_USB_CONF);
2432 } else {
2433 usbf_reg_bitclr(udc, USBF_REG_USB_CONTROL, USBF_USB_CONF);
2434 /* Go back to Address State */
2435 spin_unlock(&udc->lock);
2436 usb_gadget_set_state(&udc->gadget, USB_STATE_ADDRESS);
2437 spin_lock(&udc->lock);
2438 }
2439
2440 return 0;
2441 }
2442
usbf_handle_ep0_setup(struct usbf_ep * ep0)2443 static int usbf_handle_ep0_setup(struct usbf_ep *ep0)
2444 {
2445 union {
2446 struct usb_ctrlrequest ctrlreq;
2447 u32 raw[2];
2448 } crq;
2449 struct usbf_udc *udc = ep0->udc;
2450 int ret;
2451
2452 /* Read setup data (ie the USB control request) */
2453 crq.raw[0] = usbf_reg_readl(udc, USBF_REG_SETUP_DATA0);
2454 crq.raw[1] = usbf_reg_readl(udc, USBF_REG_SETUP_DATA1);
2455
2456 dev_dbg(ep0->udc->dev,
2457 "ep0 req%02x.%02x, wValue 0x%04x, wIndex 0x%04x, wLength 0x%04x\n",
2458 crq.ctrlreq.bRequestType, crq.ctrlreq.bRequest,
2459 crq.ctrlreq.wValue, crq.ctrlreq.wIndex, crq.ctrlreq.wLength);
2460
2461 /* Set current EP0 state according to the received request */
2462 if (crq.ctrlreq.wLength) {
2463 if (crq.ctrlreq.bRequestType & USB_DIR_IN) {
2464 udc->ep0state = EP0_IN_DATA_PHASE;
2465 usbf_ep_reg_clrset(ep0, USBF_REG_EP0_CONTROL,
2466 USBF_EP0_INAK,
2467 USBF_EP0_INAK_EN);
2468 ep0->is_in = 1;
2469 } else {
2470 udc->ep0state = EP0_OUT_DATA_PHASE;
2471 usbf_ep_reg_bitclr(ep0, USBF_REG_EP0_CONTROL,
2472 USBF_EP0_ONAK);
2473 ep0->is_in = 0;
2474 }
2475 } else {
2476 udc->ep0state = EP0_IN_STATUS_START_PHASE;
2477 ep0->is_in = 1;
2478 }
2479
2480 /* We starts a new control transfer -> Clear the delayed status flag */
2481 ep0->delayed_status = 0;
2482
2483 if ((crq.ctrlreq.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD) {
2484 /* This is not a USB standard request -> delegate */
2485 goto delegate;
2486 }
2487
2488 switch (crq.ctrlreq.bRequest) {
2489 case USB_REQ_GET_STATUS:
2490 ret = usbf_req_get_status(udc, &crq.ctrlreq);
2491 break;
2492
2493 case USB_REQ_CLEAR_FEATURE:
2494 ret = usbf_req_clear_set_feature(udc, &crq.ctrlreq, false);
2495 break;
2496
2497 case USB_REQ_SET_FEATURE:
2498 ret = usbf_req_clear_set_feature(udc, &crq.ctrlreq, true);
2499 break;
2500
2501 case USB_REQ_SET_ADDRESS:
2502 ret = usbf_req_set_address(udc, &crq.ctrlreq);
2503 break;
2504
2505 case USB_REQ_SET_CONFIGURATION:
2506 ret = usbf_req_set_configuration(udc, &crq.ctrlreq);
2507 break;
2508
2509 default:
2510 goto delegate;
2511 }
2512
2513 return ret;
2514
2515 delegate:
2516 return usbf_req_delegate(udc, &crq.ctrlreq);
2517 }
2518
usbf_handle_ep0_data_status(struct usbf_ep * ep0,const char * ep0state_name,enum usbf_ep0state next_ep0state)2519 static int usbf_handle_ep0_data_status(struct usbf_ep *ep0,
2520 const char *ep0state_name,
2521 enum usbf_ep0state next_ep0state)
2522 {
2523 struct usbf_udc *udc = ep0->udc;
2524 int ret;
2525
2526 ret = usbf_ep_process_queue(ep0);
2527 switch (ret) {
2528 case -ENOENT:
2529 dev_err(udc->dev,
2530 "no request available for ep0 %s phase\n",
2531 ep0state_name);
2532 break;
2533 case -EINPROGRESS:
2534 /* More data needs to be processed */
2535 ret = 0;
2536 break;
2537 case 0:
2538 /* All requests in the queue are processed */
2539 udc->ep0state = next_ep0state;
2540 break;
2541 default:
2542 dev_err(udc->dev,
2543 "process queue failed for ep0 %s phase (%d)\n",
2544 ep0state_name, ret);
2545 break;
2546 }
2547 return ret;
2548 }
2549
usbf_handle_ep0_out_status_start(struct usbf_ep * ep0)2550 static int usbf_handle_ep0_out_status_start(struct usbf_ep *ep0)
2551 {
2552 struct usbf_udc *udc = ep0->udc;
2553 struct usbf_req *req;
2554
2555 usbf_ep_reg_clrset(ep0, USBF_REG_EP0_CONTROL,
2556 USBF_EP0_ONAK,
2557 USBF_EP0_PIDCLR);
2558 ep0->is_in = 0;
2559
2560 req = list_first_entry_or_null(&ep0->queue, struct usbf_req, queue);
2561 if (!req) {
2562 usbf_ep0_fill_req(ep0, &udc->setup_reply, NULL, 0, NULL);
2563 usbf_ep0_queue(ep0, &udc->setup_reply, GFP_ATOMIC);
2564 } else {
2565 if (req->req.length) {
2566 dev_err(udc->dev,
2567 "queued request length %u for ep0 out status phase\n",
2568 req->req.length);
2569 }
2570 }
2571 udc->ep0state = EP0_OUT_STATUS_PHASE;
2572 return 0;
2573 }
2574
usbf_handle_ep0_in_status_start(struct usbf_ep * ep0)2575 static int usbf_handle_ep0_in_status_start(struct usbf_ep *ep0)
2576 {
2577 struct usbf_udc *udc = ep0->udc;
2578 struct usbf_req *req;
2579 int ret;
2580
2581 usbf_ep_reg_clrset(ep0, USBF_REG_EP0_CONTROL,
2582 USBF_EP0_INAK,
2583 USBF_EP0_INAK_EN | USBF_EP0_PIDCLR);
2584 ep0->is_in = 1;
2585
2586 /* Queue request for status if needed */
2587 req = list_first_entry_or_null(&ep0->queue, struct usbf_req, queue);
2588 if (!req) {
2589 if (ep0->delayed_status) {
2590 dev_dbg(ep0->udc->dev,
2591 "EP0_IN_STATUS_START_PHASE ep0->delayed_status set\n");
2592 udc->ep0state = EP0_IN_STATUS_PHASE;
2593 return 0;
2594 }
2595
2596 usbf_ep0_fill_req(ep0, &udc->setup_reply, NULL,
2597 0, NULL);
2598 usbf_ep0_queue(ep0, &udc->setup_reply,
2599 GFP_ATOMIC);
2600
2601 req = list_first_entry_or_null(&ep0->queue, struct usbf_req, queue);
2602 } else {
2603 if (req->req.length) {
2604 dev_err(udc->dev,
2605 "queued request length %u for ep0 in status phase\n",
2606 req->req.length);
2607 }
2608 }
2609
2610 ret = usbf_ep0_pio_in(ep0, req);
2611 if (ret != -EINPROGRESS) {
2612 usbf_ep_req_done(ep0, req, ret);
2613 udc->ep0state = EP0_IN_STATUS_END_PHASE;
2614 return 0;
2615 }
2616
2617 udc->ep0state = EP0_IN_STATUS_PHASE;
2618 return 0;
2619 }
2620
usbf_ep0_interrupt(struct usbf_ep * ep0)2621 static void usbf_ep0_interrupt(struct usbf_ep *ep0)
2622 {
2623 struct usbf_udc *udc = ep0->udc;
2624 u32 sts, prev_sts;
2625 int prev_ep0state;
2626 int ret;
2627
2628 ep0->status = usbf_ep_reg_readl(ep0, USBF_REG_EP0_STATUS);
2629 usbf_ep_reg_writel(ep0, USBF_REG_EP0_STATUS, ~ep0->status);
2630
2631 dev_dbg(ep0->udc->dev, "ep0 status=0x%08x, enable=%08x\n, ctrl=0x%08x\n",
2632 ep0->status,
2633 usbf_ep_reg_readl(ep0, USBF_REG_EP0_INT_ENA),
2634 usbf_ep_reg_readl(ep0, USBF_REG_EP0_CONTROL));
2635
2636 sts = ep0->status & (USBF_EP0_SETUP_INT | USBF_EP0_IN_INT | USBF_EP0_OUT_INT |
2637 USBF_EP0_OUT_NULL_INT | USBF_EP0_STG_START_INT |
2638 USBF_EP0_STG_END_INT);
2639
2640 ret = 0;
2641 do {
2642 dev_dbg(ep0->udc->dev, "udc->ep0state=%d\n", udc->ep0state);
2643
2644 prev_sts = sts;
2645 prev_ep0state = udc->ep0state;
2646 switch (udc->ep0state) {
2647 case EP0_IDLE:
2648 if (!(sts & USBF_EP0_SETUP_INT))
2649 break;
2650
2651 sts &= ~USBF_EP0_SETUP_INT;
2652 dev_dbg(ep0->udc->dev, "ep0 handle setup\n");
2653 ret = usbf_handle_ep0_setup(ep0);
2654 break;
2655
2656 case EP0_IN_DATA_PHASE:
2657 if (!(sts & USBF_EP0_IN_INT))
2658 break;
2659
2660 sts &= ~USBF_EP0_IN_INT;
2661 dev_dbg(ep0->udc->dev, "ep0 handle in data phase\n");
2662 ret = usbf_handle_ep0_data_status(ep0,
2663 "in data", EP0_OUT_STATUS_START_PHASE);
2664 break;
2665
2666 case EP0_OUT_STATUS_START_PHASE:
2667 if (!(sts & USBF_EP0_STG_START_INT))
2668 break;
2669
2670 sts &= ~USBF_EP0_STG_START_INT;
2671 dev_dbg(ep0->udc->dev, "ep0 handle out status start phase\n");
2672 ret = usbf_handle_ep0_out_status_start(ep0);
2673 break;
2674
2675 case EP0_OUT_STATUS_PHASE:
2676 if (!(sts & (USBF_EP0_OUT_INT | USBF_EP0_OUT_NULL_INT)))
2677 break;
2678
2679 sts &= ~(USBF_EP0_OUT_INT | USBF_EP0_OUT_NULL_INT);
2680 dev_dbg(ep0->udc->dev, "ep0 handle out status phase\n");
2681 ret = usbf_handle_ep0_data_status(ep0,
2682 "out status",
2683 EP0_OUT_STATUS_END_PHASE);
2684 break;
2685
2686 case EP0_OUT_STATUS_END_PHASE:
2687 if (!(sts & (USBF_EP0_STG_END_INT | USBF_EP0_SETUP_INT)))
2688 break;
2689
2690 sts &= ~USBF_EP0_STG_END_INT;
2691 dev_dbg(ep0->udc->dev, "ep0 handle out status end phase\n");
2692 udc->ep0state = EP0_IDLE;
2693 break;
2694
2695 case EP0_OUT_DATA_PHASE:
2696 if (!(sts & (USBF_EP0_OUT_INT | USBF_EP0_OUT_NULL_INT)))
2697 break;
2698
2699 sts &= ~(USBF_EP0_OUT_INT | USBF_EP0_OUT_NULL_INT);
2700 dev_dbg(ep0->udc->dev, "ep0 handle out data phase\n");
2701 ret = usbf_handle_ep0_data_status(ep0,
2702 "out data", EP0_IN_STATUS_START_PHASE);
2703 break;
2704
2705 case EP0_IN_STATUS_START_PHASE:
2706 if (!(sts & USBF_EP0_STG_START_INT))
2707 break;
2708
2709 sts &= ~USBF_EP0_STG_START_INT;
2710 dev_dbg(ep0->udc->dev, "ep0 handle in status start phase\n");
2711 ret = usbf_handle_ep0_in_status_start(ep0);
2712 break;
2713
2714 case EP0_IN_STATUS_PHASE:
2715 if (!(sts & USBF_EP0_IN_INT))
2716 break;
2717
2718 sts &= ~USBF_EP0_IN_INT;
2719 dev_dbg(ep0->udc->dev, "ep0 handle in status phase\n");
2720 ret = usbf_handle_ep0_data_status(ep0,
2721 "in status", EP0_IN_STATUS_END_PHASE);
2722 break;
2723
2724 case EP0_IN_STATUS_END_PHASE:
2725 if (!(sts & (USBF_EP0_STG_END_INT | USBF_EP0_SETUP_INT)))
2726 break;
2727
2728 sts &= ~USBF_EP0_STG_END_INT;
2729 dev_dbg(ep0->udc->dev, "ep0 handle in status end\n");
2730 udc->ep0state = EP0_IDLE;
2731 break;
2732
2733 default:
2734 udc->ep0state = EP0_IDLE;
2735 break;
2736 }
2737
2738 if (ret) {
2739 dev_dbg(ep0->udc->dev, "ep0 failed (%d)\n", ret);
2740 /* Failure -> stall.
2741 * This stall state will be automatically cleared when
2742 * the IP receives the next SETUP packet
2743 */
2744 usbf_ep_stall(ep0, true);
2745
2746 /* Remove anything that was pending */
2747 usbf_ep_nuke(ep0, -EPROTO);
2748
2749 udc->ep0state = EP0_IDLE;
2750 break;
2751 }
2752
2753 } while ((prev_ep0state != udc->ep0state) || (prev_sts != sts));
2754
2755 dev_dbg(ep0->udc->dev, "ep0 done udc->ep0state=%d, status=0x%08x. next=0x%08x\n",
2756 udc->ep0state, sts,
2757 usbf_ep_reg_readl(ep0, USBF_REG_EP0_STATUS));
2758 }
2759
usbf_epn_process_queue(struct usbf_ep * epn)2760 static void usbf_epn_process_queue(struct usbf_ep *epn)
2761 {
2762 int ret;
2763
2764 ret = usbf_ep_process_queue(epn);
2765 switch (ret) {
2766 case -ENOENT:
2767 dev_warn(epn->udc->dev, "ep%u %s, no request available\n",
2768 epn->id, epn->is_in ? "in" : "out");
2769 break;
2770 case -EINPROGRESS:
2771 /* More data needs to be processed */
2772 ret = 0;
2773 break;
2774 case 0:
2775 /* All requests in the queue are processed */
2776 break;
2777 default:
2778 dev_err(epn->udc->dev, "ep%u %s, process queue failed (%d)\n",
2779 epn->id, epn->is_in ? "in" : "out", ret);
2780 break;
2781 }
2782
2783 if (ret) {
2784 dev_dbg(epn->udc->dev, "ep%u %s failed (%d)\n", epn->id,
2785 epn->is_in ? "in" : "out", ret);
2786 usbf_ep_stall(epn, true);
2787 usbf_ep_nuke(epn, ret);
2788 }
2789 }
2790
usbf_epn_interrupt(struct usbf_ep * epn)2791 static void usbf_epn_interrupt(struct usbf_ep *epn)
2792 {
2793 u32 sts;
2794 u32 ena;
2795
2796 epn->status = usbf_ep_reg_readl(epn, USBF_REG_EPN_STATUS);
2797 ena = usbf_ep_reg_readl(epn, USBF_REG_EPN_INT_ENA);
2798 usbf_ep_reg_writel(epn, USBF_REG_EPN_STATUS, ~(epn->status & ena));
2799
2800 dev_dbg(epn->udc->dev, "ep%u %s status=0x%08x, enable=%08x\n, ctrl=0x%08x\n",
2801 epn->id, epn->is_in ? "in" : "out", epn->status, ena,
2802 usbf_ep_reg_readl(epn, USBF_REG_EPN_CONTROL));
2803
2804 if (epn->disabled) {
2805 dev_warn(epn->udc->dev, "ep%u %s, interrupt while disabled\n",
2806 epn->id, epn->is_in ? "in" : "out");
2807 return;
2808 }
2809
2810 sts = epn->status & ena;
2811
2812 if (sts & (USBF_EPN_IN_END_INT | USBF_EPN_IN_INT)) {
2813 sts &= ~(USBF_EPN_IN_END_INT | USBF_EPN_IN_INT);
2814 dev_dbg(epn->udc->dev, "ep%u %s process queue (in interrupts)\n",
2815 epn->id, epn->is_in ? "in" : "out");
2816 usbf_epn_process_queue(epn);
2817 }
2818
2819 if (sts & (USBF_EPN_OUT_END_INT | USBF_EPN_OUT_INT | USBF_EPN_OUT_NULL_INT)) {
2820 sts &= ~(USBF_EPN_OUT_END_INT | USBF_EPN_OUT_INT | USBF_EPN_OUT_NULL_INT);
2821 dev_dbg(epn->udc->dev, "ep%u %s process queue (out interrupts)\n",
2822 epn->id, epn->is_in ? "in" : "out");
2823 usbf_epn_process_queue(epn);
2824 }
2825
2826 dev_dbg(epn->udc->dev, "ep%u %s done status=0x%08x. next=0x%08x\n",
2827 epn->id, epn->is_in ? "in" : "out",
2828 sts, usbf_ep_reg_readl(epn, USBF_REG_EPN_STATUS));
2829 }
2830
usbf_ep_reset(struct usbf_ep * ep)2831 static void usbf_ep_reset(struct usbf_ep *ep)
2832 {
2833 ep->status = 0;
2834 /* Remove anything that was pending */
2835 usbf_ep_nuke(ep, -ESHUTDOWN);
2836 }
2837
usbf_reset(struct usbf_udc * udc)2838 static void usbf_reset(struct usbf_udc *udc)
2839 {
2840 int i;
2841
2842 for (i = 0; i < ARRAY_SIZE(udc->ep); i++) {
2843 if (udc->ep[i].disabled)
2844 continue;
2845
2846 usbf_ep_reset(&udc->ep[i]);
2847 }
2848
2849 if (usbf_reg_readl(udc, USBF_REG_USB_STATUS) & USBF_USB_SPEED_MODE)
2850 udc->gadget.speed = USB_SPEED_HIGH;
2851 else
2852 udc->gadget.speed = USB_SPEED_FULL;
2853
2854 /* Remote wakeup feature must be disabled on USB bus reset */
2855 udc->is_remote_wakeup = false;
2856
2857 /* Enable endpoint zero */
2858 usbf_ep0_enable(&udc->ep[0]);
2859
2860 if (udc->driver) {
2861 /* Signal the reset */
2862 spin_unlock(&udc->lock);
2863 usb_gadget_udc_reset(&udc->gadget, udc->driver);
2864 spin_lock(&udc->lock);
2865 }
2866 }
2867
usbf_driver_suspend(struct usbf_udc * udc)2868 static void usbf_driver_suspend(struct usbf_udc *udc)
2869 {
2870 if (udc->is_usb_suspended) {
2871 dev_dbg(udc->dev, "already suspended\n");
2872 return;
2873 }
2874
2875 dev_dbg(udc->dev, "do usb suspend\n");
2876 udc->is_usb_suspended = true;
2877
2878 if (udc->driver && udc->driver->suspend) {
2879 spin_unlock(&udc->lock);
2880 udc->driver->suspend(&udc->gadget);
2881 spin_lock(&udc->lock);
2882
2883 /* The datasheet tells to set the USB_CONTROL register SUSPEND
2884 * bit when the USB bus suspend is detected.
2885 * This bit stops the clocks (clocks for EPC, SIE, USBPHY) but
2886 * these clocks seems not used only by the USB device. Some
2887 * UARTs can be lost ...
2888 * So, do not set the USB_CONTROL register SUSPEND bit.
2889 */
2890 }
2891 }
2892
usbf_driver_resume(struct usbf_udc * udc)2893 static void usbf_driver_resume(struct usbf_udc *udc)
2894 {
2895 if (!udc->is_usb_suspended)
2896 return;
2897
2898 dev_dbg(udc->dev, "do usb resume\n");
2899 udc->is_usb_suspended = false;
2900
2901 if (udc->driver && udc->driver->resume) {
2902 spin_unlock(&udc->lock);
2903 udc->driver->resume(&udc->gadget);
2904 spin_lock(&udc->lock);
2905 }
2906 }
2907
usbf_epc_irq(int irq,void * _udc)2908 static irqreturn_t usbf_epc_irq(int irq, void *_udc)
2909 {
2910 struct usbf_udc *udc = (struct usbf_udc *)_udc;
2911 unsigned long flags;
2912 struct usbf_ep *ep;
2913 u32 int_sts;
2914 u32 int_en;
2915 int i;
2916
2917 spin_lock_irqsave(&udc->lock, flags);
2918
2919 int_en = usbf_reg_readl(udc, USBF_REG_USB_INT_ENA);
2920 int_sts = usbf_reg_readl(udc, USBF_REG_USB_INT_STA) & int_en;
2921 usbf_reg_writel(udc, USBF_REG_USB_INT_STA, ~int_sts);
2922
2923 dev_dbg(udc->dev, "int_sts=0x%08x\n", int_sts);
2924
2925 if (int_sts & USBF_USB_RSUM_INT) {
2926 dev_dbg(udc->dev, "handle resume\n");
2927 usbf_driver_resume(udc);
2928 }
2929
2930 if (int_sts & USBF_USB_USB_RST_INT) {
2931 dev_dbg(udc->dev, "handle bus reset\n");
2932 usbf_driver_resume(udc);
2933 usbf_reset(udc);
2934 }
2935
2936 if (int_sts & USBF_USB_SPEED_MODE_INT) {
2937 if (usbf_reg_readl(udc, USBF_REG_USB_STATUS) & USBF_USB_SPEED_MODE)
2938 udc->gadget.speed = USB_SPEED_HIGH;
2939 else
2940 udc->gadget.speed = USB_SPEED_FULL;
2941 dev_dbg(udc->dev, "handle speed change (%s)\n",
2942 udc->gadget.speed == USB_SPEED_HIGH ? "High" : "Full");
2943 }
2944
2945 if (int_sts & USBF_USB_EPN_INT(0)) {
2946 usbf_driver_resume(udc);
2947 usbf_ep0_interrupt(&udc->ep[0]);
2948 }
2949
2950 for (i = 1; i < ARRAY_SIZE(udc->ep); i++) {
2951 ep = &udc->ep[i];
2952
2953 if (int_sts & USBF_USB_EPN_INT(i)) {
2954 usbf_driver_resume(udc);
2955 usbf_epn_interrupt(ep);
2956 }
2957 }
2958
2959 if (int_sts & USBF_USB_SPND_INT) {
2960 dev_dbg(udc->dev, "handle suspend\n");
2961 usbf_driver_suspend(udc);
2962 }
2963
2964 spin_unlock_irqrestore(&udc->lock, flags);
2965
2966 return IRQ_HANDLED;
2967 }
2968
usbf_ahb_epc_irq(int irq,void * _udc)2969 static irqreturn_t usbf_ahb_epc_irq(int irq, void *_udc)
2970 {
2971 struct usbf_udc *udc = (struct usbf_udc *)_udc;
2972 unsigned long flags;
2973 struct usbf_ep *epn;
2974 u32 sysbint;
2975 void (*ep_action)(struct usbf_ep *epn);
2976 int i;
2977
2978 spin_lock_irqsave(&udc->lock, flags);
2979
2980 /* Read and ack interrupts */
2981 sysbint = usbf_reg_readl(udc, USBF_REG_AHBBINT);
2982 usbf_reg_writel(udc, USBF_REG_AHBBINT, sysbint);
2983
2984 if ((sysbint & USBF_SYS_VBUS_INT) == USBF_SYS_VBUS_INT) {
2985 if (usbf_reg_readl(udc, USBF_REG_EPCTR) & USBF_SYS_VBUS_LEVEL) {
2986 dev_dbg(udc->dev, "handle vbus (1)\n");
2987 spin_unlock(&udc->lock);
2988 usb_udc_vbus_handler(&udc->gadget, true);
2989 usb_gadget_set_state(&udc->gadget, USB_STATE_POWERED);
2990 spin_lock(&udc->lock);
2991 } else {
2992 dev_dbg(udc->dev, "handle vbus (0)\n");
2993 udc->is_usb_suspended = false;
2994 spin_unlock(&udc->lock);
2995 usb_udc_vbus_handler(&udc->gadget, false);
2996 usb_gadget_set_state(&udc->gadget,
2997 USB_STATE_NOTATTACHED);
2998 spin_lock(&udc->lock);
2999 }
3000 }
3001
3002 for (i = 1; i < ARRAY_SIZE(udc->ep); i++) {
3003 if (sysbint & USBF_SYS_DMA_ENDINT_EPN(i)) {
3004 epn = &udc->ep[i];
3005 dev_dbg(epn->udc->dev,
3006 "ep%u handle DMA complete. action=%ps\n",
3007 epn->id, epn->bridge_on_dma_end);
3008 ep_action = epn->bridge_on_dma_end;
3009 if (ep_action) {
3010 epn->bridge_on_dma_end = NULL;
3011 ep_action(epn);
3012 }
3013 }
3014 }
3015
3016 spin_unlock_irqrestore(&udc->lock, flags);
3017
3018 return IRQ_HANDLED;
3019 }
3020
usbf_udc_start(struct usb_gadget * gadget,struct usb_gadget_driver * driver)3021 static int usbf_udc_start(struct usb_gadget *gadget,
3022 struct usb_gadget_driver *driver)
3023 {
3024 struct usbf_udc *udc = container_of(gadget, struct usbf_udc, gadget);
3025 unsigned long flags;
3026
3027 dev_info(udc->dev, "start (driver '%s')\n", driver->driver.name);
3028
3029 spin_lock_irqsave(&udc->lock, flags);
3030
3031 /* hook up the driver */
3032 udc->driver = driver;
3033
3034 /* Enable VBUS interrupt */
3035 usbf_reg_writel(udc, USBF_REG_AHBBINTEN, USBF_SYS_VBUS_INTEN);
3036
3037 spin_unlock_irqrestore(&udc->lock, flags);
3038
3039 return 0;
3040 }
3041
usbf_udc_stop(struct usb_gadget * gadget)3042 static int usbf_udc_stop(struct usb_gadget *gadget)
3043 {
3044 struct usbf_udc *udc = container_of(gadget, struct usbf_udc, gadget);
3045 unsigned long flags;
3046
3047 spin_lock_irqsave(&udc->lock, flags);
3048
3049 /* Disable VBUS interrupt */
3050 usbf_reg_writel(udc, USBF_REG_AHBBINTEN, 0);
3051
3052 udc->driver = NULL;
3053
3054 spin_unlock_irqrestore(&udc->lock, flags);
3055
3056 dev_info(udc->dev, "stopped\n");
3057
3058 return 0;
3059 }
3060
usbf_get_frame(struct usb_gadget * gadget)3061 static int usbf_get_frame(struct usb_gadget *gadget)
3062 {
3063 struct usbf_udc *udc = container_of(gadget, struct usbf_udc, gadget);
3064
3065 return USBF_USB_GET_FRAME(usbf_reg_readl(udc, USBF_REG_USB_ADDRESS));
3066 }
3067
usbf_attach(struct usbf_udc * udc)3068 static void usbf_attach(struct usbf_udc *udc)
3069 {
3070 /* Enable USB signal to Function PHY
3071 * D+ signal Pull-up
3072 * Disable endpoint 0, it will be automatically enable when a USB reset
3073 * is received.
3074 * Disable the other endpoints
3075 */
3076 usbf_reg_clrset(udc, USBF_REG_USB_CONTROL,
3077 USBF_USB_CONNECTB | USBF_USB_DEFAULT | USBF_USB_CONF,
3078 USBF_USB_PUE2);
3079
3080 /* Enable reset and mode change interrupts */
3081 usbf_reg_bitset(udc, USBF_REG_USB_INT_ENA,
3082 USBF_USB_USB_RST_EN | USBF_USB_SPEED_MODE_EN | USBF_USB_RSUM_EN | USBF_USB_SPND_EN);
3083 }
3084
usbf_detach(struct usbf_udc * udc)3085 static void usbf_detach(struct usbf_udc *udc)
3086 {
3087 int i;
3088
3089 /* Disable interrupts */
3090 usbf_reg_writel(udc, USBF_REG_USB_INT_ENA, 0);
3091
3092 for (i = 0; i < ARRAY_SIZE(udc->ep); i++) {
3093 if (udc->ep[i].disabled)
3094 continue;
3095
3096 usbf_ep_reset(&udc->ep[i]);
3097 }
3098
3099 /* Disable USB signal to Function PHY
3100 * Do not Pull-up D+ signal
3101 * Disable endpoint 0
3102 * Disable the other endpoints
3103 */
3104 usbf_reg_clrset(udc, USBF_REG_USB_CONTROL,
3105 USBF_USB_PUE2 | USBF_USB_DEFAULT | USBF_USB_CONF,
3106 USBF_USB_CONNECTB);
3107 }
3108
usbf_pullup(struct usb_gadget * gadget,int is_on)3109 static int usbf_pullup(struct usb_gadget *gadget, int is_on)
3110 {
3111 struct usbf_udc *udc = container_of(gadget, struct usbf_udc, gadget);
3112 unsigned long flags;
3113
3114 dev_dbg(udc->dev, "pullup %d\n", is_on);
3115
3116 spin_lock_irqsave(&udc->lock, flags);
3117 if (is_on)
3118 usbf_attach(udc);
3119 else
3120 usbf_detach(udc);
3121 spin_unlock_irqrestore(&udc->lock, flags);
3122
3123 return 0;
3124 }
3125
usbf_udc_set_selfpowered(struct usb_gadget * gadget,int is_selfpowered)3126 static int usbf_udc_set_selfpowered(struct usb_gadget *gadget,
3127 int is_selfpowered)
3128 {
3129 struct usbf_udc *udc = container_of(gadget, struct usbf_udc, gadget);
3130 unsigned long flags;
3131
3132 spin_lock_irqsave(&udc->lock, flags);
3133 gadget->is_selfpowered = (is_selfpowered != 0);
3134 spin_unlock_irqrestore(&udc->lock, flags);
3135
3136 return 0;
3137 }
3138
usbf_udc_wakeup(struct usb_gadget * gadget)3139 static int usbf_udc_wakeup(struct usb_gadget *gadget)
3140 {
3141 struct usbf_udc *udc = container_of(gadget, struct usbf_udc, gadget);
3142 unsigned long flags;
3143 int ret;
3144
3145 spin_lock_irqsave(&udc->lock, flags);
3146
3147 if (!udc->is_remote_wakeup) {
3148 dev_dbg(udc->dev, "remote wakeup not allowed\n");
3149 ret = -EINVAL;
3150 goto end;
3151 }
3152
3153 dev_dbg(udc->dev, "do wakeup\n");
3154
3155 /* Send the resume signal */
3156 usbf_reg_bitset(udc, USBF_REG_USB_CONTROL, USBF_USB_RSUM_IN);
3157 usbf_reg_bitclr(udc, USBF_REG_USB_CONTROL, USBF_USB_RSUM_IN);
3158
3159 ret = 0;
3160 end:
3161 spin_unlock_irqrestore(&udc->lock, flags);
3162 return ret;
3163 }
3164
3165 static struct usb_gadget_ops usbf_gadget_ops = {
3166 .get_frame = usbf_get_frame,
3167 .pullup = usbf_pullup,
3168 .udc_start = usbf_udc_start,
3169 .udc_stop = usbf_udc_stop,
3170 .set_selfpowered = usbf_udc_set_selfpowered,
3171 .wakeup = usbf_udc_wakeup,
3172 };
3173
usbf_epn_check(struct usbf_ep * epn)3174 static int usbf_epn_check(struct usbf_ep *epn)
3175 {
3176 const char *type_txt;
3177 const char *buf_txt;
3178 int ret = 0;
3179 u32 ctrl;
3180
3181 ctrl = usbf_ep_reg_readl(epn, USBF_REG_EPN_CONTROL);
3182
3183 switch (ctrl & USBF_EPN_MODE_MASK) {
3184 case USBF_EPN_MODE_BULK:
3185 type_txt = "bulk";
3186 if (epn->ep.caps.type_control || epn->ep.caps.type_iso ||
3187 !epn->ep.caps.type_bulk || epn->ep.caps.type_int) {
3188 dev_err(epn->udc->dev,
3189 "ep%u caps mismatch, bulk expected\n", epn->id);
3190 ret = -EINVAL;
3191 }
3192 break;
3193 case USBF_EPN_MODE_INTR:
3194 type_txt = "intr";
3195 if (epn->ep.caps.type_control || epn->ep.caps.type_iso ||
3196 epn->ep.caps.type_bulk || !epn->ep.caps.type_int) {
3197 dev_err(epn->udc->dev,
3198 "ep%u caps mismatch, int expected\n", epn->id);
3199 ret = -EINVAL;
3200 }
3201 break;
3202 case USBF_EPN_MODE_ISO:
3203 type_txt = "iso";
3204 if (epn->ep.caps.type_control || !epn->ep.caps.type_iso ||
3205 epn->ep.caps.type_bulk || epn->ep.caps.type_int) {
3206 dev_err(epn->udc->dev,
3207 "ep%u caps mismatch, iso expected\n", epn->id);
3208 ret = -EINVAL;
3209 }
3210 break;
3211 default:
3212 type_txt = "unknown";
3213 dev_err(epn->udc->dev, "ep%u unknown type\n", epn->id);
3214 ret = -EINVAL;
3215 break;
3216 }
3217
3218 if (ctrl & USBF_EPN_BUF_TYPE_DOUBLE) {
3219 buf_txt = "double";
3220 if (!usbf_ep_info[epn->id].is_double) {
3221 dev_err(epn->udc->dev,
3222 "ep%u buffer mismatch, double expected\n",
3223 epn->id);
3224 ret = -EINVAL;
3225 }
3226 } else {
3227 buf_txt = "single";
3228 if (usbf_ep_info[epn->id].is_double) {
3229 dev_err(epn->udc->dev,
3230 "ep%u buffer mismatch, single expected\n",
3231 epn->id);
3232 ret = -EINVAL;
3233 }
3234 }
3235
3236 dev_dbg(epn->udc->dev, "ep%u (%s) %s, %s buffer %u, checked %s\n",
3237 epn->id, epn->ep.name, type_txt, buf_txt,
3238 epn->ep.maxpacket_limit, ret ? "failed" : "ok");
3239
3240 return ret;
3241 }
3242
usbf_probe(struct platform_device * pdev)3243 static int usbf_probe(struct platform_device *pdev)
3244 {
3245 struct device *dev = &pdev->dev;
3246 struct usbf_udc *udc;
3247 struct usbf_ep *ep;
3248 unsigned int i;
3249 int irq;
3250 int ret;
3251
3252 udc = devm_kzalloc(dev, sizeof(*udc), GFP_KERNEL);
3253 if (!udc)
3254 return -ENOMEM;
3255 platform_set_drvdata(pdev, udc);
3256
3257 udc->dev = dev;
3258 spin_lock_init(&udc->lock);
3259
3260 udc->regs = devm_platform_ioremap_resource(pdev, 0);
3261 if (IS_ERR(udc->regs))
3262 return PTR_ERR(udc->regs);
3263
3264 ret = devm_pm_runtime_enable(&pdev->dev);
3265 if (ret)
3266 return ret;
3267 ret = pm_runtime_resume_and_get(&pdev->dev);
3268 if (ret < 0)
3269 return ret;
3270
3271 dev_info(dev, "USBF version: %08x\n",
3272 usbf_reg_readl(udc, USBF_REG_USBSSVER));
3273
3274 /* Resetting the PLL is handled via the clock driver as it has common
3275 * registers with USB Host
3276 */
3277 usbf_reg_bitclr(udc, USBF_REG_EPCTR, USBF_SYS_EPC_RST);
3278
3279 /* modify in register gadget process */
3280 udc->gadget.speed = USB_SPEED_FULL;
3281 udc->gadget.max_speed = USB_SPEED_HIGH;
3282 udc->gadget.ops = &usbf_gadget_ops;
3283
3284 udc->gadget.name = dev->driver->name;
3285 udc->gadget.dev.parent = dev;
3286 udc->gadget.ep0 = &udc->ep[0].ep;
3287
3288 /* The hardware DMA controller needs dma addresses aligned on 32bit.
3289 * A fallback to pio is done if DMA addresses are not aligned.
3290 */
3291 udc->gadget.quirk_avoids_skb_reserve = 1;
3292
3293 INIT_LIST_HEAD(&udc->gadget.ep_list);
3294 /* we have a canned request structure to allow sending packets as reply
3295 * to get_status requests
3296 */
3297 INIT_LIST_HEAD(&udc->setup_reply.queue);
3298
3299 for (i = 0; i < ARRAY_SIZE(udc->ep); i++) {
3300 ep = &udc->ep[i];
3301
3302 if (!(usbf_reg_readl(udc, USBF_REG_USBSSCONF) &
3303 USBF_SYS_EP_AVAILABLE(i))) {
3304 continue;
3305 }
3306
3307 INIT_LIST_HEAD(&ep->queue);
3308
3309 ep->id = i;
3310 ep->disabled = 1;
3311 ep->udc = udc;
3312 ep->ep.ops = &usbf_ep_ops;
3313 ep->ep.name = usbf_ep_info[i].name;
3314 ep->ep.caps = usbf_ep_info[i].caps;
3315 usb_ep_set_maxpacket_limit(&ep->ep,
3316 usbf_ep_info[i].maxpacket_limit);
3317
3318 if (ep->id == 0) {
3319 ep->regs = ep->udc->regs + USBF_BASE_EP0;
3320 } else {
3321 ep->regs = ep->udc->regs + USBF_BASE_EPN(ep->id - 1);
3322 ret = usbf_epn_check(ep);
3323 if (ret)
3324 return ret;
3325 if (usbf_reg_readl(udc, USBF_REG_USBSSCONF) &
3326 USBF_SYS_DMA_AVAILABLE(i)) {
3327 ep->dma_regs = ep->udc->regs +
3328 USBF_BASE_DMA_EPN(ep->id - 1);
3329 }
3330 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
3331 }
3332 }
3333
3334 irq = platform_get_irq(pdev, 0);
3335 if (irq < 0)
3336 return irq;
3337 ret = devm_request_irq(dev, irq, usbf_epc_irq, 0, "usbf-epc", udc);
3338 if (ret) {
3339 dev_err(dev, "cannot request irq %d err %d\n", irq, ret);
3340 return ret;
3341 }
3342
3343 irq = platform_get_irq(pdev, 1);
3344 if (irq < 0)
3345 return irq;
3346 ret = devm_request_irq(dev, irq, usbf_ahb_epc_irq, 0, "usbf-ahb-epc", udc);
3347 if (ret) {
3348 dev_err(dev, "cannot request irq %d err %d\n", irq, ret);
3349 return ret;
3350 }
3351
3352 usbf_reg_bitset(udc, USBF_REG_AHBMCTR, USBF_SYS_WBURST_TYPE);
3353
3354 usbf_reg_bitset(udc, USBF_REG_USB_CONTROL,
3355 USBF_USB_INT_SEL | USBF_USB_SOF_RCV | USBF_USB_SOF_CLK_MODE);
3356
3357 ret = usb_add_gadget_udc(dev, &udc->gadget);
3358 if (ret)
3359 return ret;
3360
3361 return 0;
3362 }
3363
usbf_remove(struct platform_device * pdev)3364 static void usbf_remove(struct platform_device *pdev)
3365 {
3366 struct usbf_udc *udc = platform_get_drvdata(pdev);
3367
3368 usb_del_gadget_udc(&udc->gadget);
3369
3370 pm_runtime_put(&pdev->dev);
3371 }
3372
3373 static const struct of_device_id usbf_match[] = {
3374 { .compatible = "renesas,rzn1-usbf" },
3375 {} /* sentinel */
3376 };
3377 MODULE_DEVICE_TABLE(of, usbf_match);
3378
3379 static struct platform_driver udc_driver = {
3380 .driver = {
3381 .name = "usbf_renesas",
3382 .of_match_table = usbf_match,
3383 },
3384 .probe = usbf_probe,
3385 .remove = usbf_remove,
3386 };
3387
3388 module_platform_driver(udc_driver);
3389
3390 MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>");
3391 MODULE_DESCRIPTION("Renesas R-Car Gen3 & RZ/N1 USB Function driver");
3392 MODULE_LICENSE("GPL");
3393