1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef _XE_GT_REGS_H_ 7 #define _XE_GT_REGS_H_ 8 9 #include "regs/xe_reg_defs.h" 10 11 /* 12 * The GSI register range [0x0 - 0x40000) is replicated at a higher offset 13 * for the media GT. xe_mmio and xe_gt_mcr functions will automatically 14 * translate offsets by MEDIA_GT_GSI_OFFSET when operating on the media GT. 15 */ 16 #define MEDIA_GT_GSI_OFFSET 0x380000 17 #define MEDIA_GT_GSI_LENGTH 0x40000 18 19 /* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */ 20 #define MTL_MIRROR_TARGET_WP1 XE_REG(0xc60) 21 #define MTL_CAGF_MASK REG_GENMASK(8, 0) 22 #define MTL_CC_MASK REG_GENMASK(12, 9) 23 24 /* RPM unit config (Gen8+) */ 25 #define RPM_CONFIG0 XE_REG(0xd00) 26 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3) 27 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 28 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1 29 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2 30 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3 31 #define RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1) 32 33 #define FORCEWAKE_ACK_MEDIA_VDBOX(n) XE_REG(0xd50 + (n) * 4) 34 #define FORCEWAKE_ACK_MEDIA_VEBOX(n) XE_REG(0xd70 + (n) * 4) 35 #define FORCEWAKE_ACK_RENDER XE_REG(0xd84) 36 37 #define GMD_ID XE_REG(0xd8c) 38 #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) 39 #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) 40 /* 41 * Spec defines these bits as "Reserved", but then make them assume some 42 * meaning that depends on the ARCH. To avoid any confusion, call them 43 * SUBIP_FLAG_MASK. 44 */ 45 #define GMD_ID_SUBIP_FLAG_MASK REG_GENMASK(13, 6) 46 #define GMD_ID_REVID REG_GENMASK(5, 0) 47 48 #define FORCEWAKE_ACK_GSC XE_REG(0xdf8) 49 #define FORCEWAKE_ACK_GT_MTL XE_REG(0xdfc) 50 51 #define STEER_SEMAPHORE XE_REG(0xfd0) 52 #define MTL_MCR_SELECTOR XE_REG(0xfd4) 53 #define SF_MCR_SELECTOR XE_REG(0xfd8) 54 #define MCR_SELECTOR XE_REG(0xfdc) 55 #define GAM_MCR_SELECTOR XE_REG(0xfe0) 56 #define MCR_MULTICAST REG_BIT(31) 57 #define MCR_SLICE_MASK REG_GENMASK(30, 27) 58 #define MCR_SLICE(slice) REG_FIELD_PREP(MCR_SLICE_MASK, slice) 59 #define MCR_SUBSLICE_MASK REG_GENMASK(26, 24) 60 #define MCR_SUBSLICE(subslice) REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice) 61 #define MTL_MCR_GROUPID REG_GENMASK(11, 8) 62 #define MTL_MCR_INSTANCEID REG_GENMASK(3, 0) 63 64 #define PS_INVOCATION_COUNT XE_REG(0x2348) 65 66 #define XELP_GLOBAL_MOCS(i) XE_REG(0x4000 + (i) * 4) 67 #define XEHP_GLOBAL_MOCS(i) XE_REG_MCR(0x4000 + (i) * 4) 68 #define LE_SSE_MASK REG_GENMASK(18, 17) 69 #define LE_SSE(value) REG_FIELD_PREP(LE_SSE_MASK, value) 70 #define LE_COS_MASK REG_GENMASK(16, 15) 71 #define LE_SCF_MASK REG_BIT(14) 72 #define LE_SCF(value) REG_FIELD_PREP(LE_SCF_MASK, value) 73 #define LE_PFM_MASK REG_GENMASK(13, 11) 74 #define LE_PFM(value) REG_FIELD_PREP(LE_PFM_MASK, value) 75 #define LE_SCC_MASK REG_GENMASK(10, 8) 76 #define LE_SCC(value) REG_FIELD_PREP(LE_SCC_MASK, value) 77 #define LE_RSC_MASK REG_BIT(7) 78 #define LE_RSC(value) REG_FIELD_PREP(LE_RSC_MASK, value) 79 #define LE_AOM_MASK REG_BIT(6) 80 #define LE_AOM(value) REG_FIELD_PREP(LE_AOM_MASK, value) 81 #define LE_LRUM_MASK REG_GENMASK(5, 4) 82 #define LE_LRUM(value) REG_FIELD_PREP(LE_LRUM_MASK, value) 83 #define LE_TGT_CACHE_MASK REG_GENMASK(3, 2) 84 #define LE_TGT_CACHE(value) REG_FIELD_PREP(LE_TGT_CACHE_MASK, value) 85 #define LE_CACHEABILITY_MASK REG_GENMASK(1, 0) 86 #define LE_CACHEABILITY(value) REG_FIELD_PREP(LE_CACHEABILITY_MASK, value) 87 88 #define STATELESS_COMPRESSION_CTRL XE_REG_MCR(0x4148) 89 #define UNIFIED_COMPRESSION_FORMAT REG_GENMASK(3, 0) 90 91 #define XE2_GAMREQSTRM_CTRL XE_REG_MCR(0x4194) 92 #define EN_CMP_1WCOH REG_BIT(15) 93 #define CG_DIS_CNTLBUS REG_BIT(6) 94 95 #define CCS_AUX_INV XE_REG(0x4208) 96 97 #define VD0_AUX_INV XE_REG(0x4218) 98 #define VE0_AUX_INV XE_REG(0x4238) 99 100 #define VE1_AUX_INV XE_REG(0x42b8) 101 #define AUX_INV REG_BIT(0) 102 103 #define XE2_LMEM_CFG XE_REG(0x48b0) 104 105 #define XE2_GAMWALK_CTRL 0x47e4 106 #define XE2_GAMWALK_CTRL_MEDIA XE_REG(XE2_GAMWALK_CTRL + MEDIA_GT_GSI_OFFSET) 107 #define XE2_GAMWALK_CTRL_3D XE_REG_MCR(XE2_GAMWALK_CTRL) 108 #define EN_CMP_1WCOH_GW REG_BIT(14) 109 110 #define XEHP_FLAT_CCS_BASE_ADDR XE_REG_MCR(0x4910) 111 #define XEHP_FLAT_CCS_PTR REG_GENMASK(31, 8) 112 113 #define WM_CHICKEN3 XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED) 114 #define HIZ_PLANE_COMPRESSION_DIS REG_BIT(10) 115 116 #define CHICKEN_RASTER_1 XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED) 117 #define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8) 118 #define DIS_CLIP_NEGATIVE_BOUNDING_BOX REG_BIT(6) 119 120 #define CHICKEN_RASTER_2 XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED) 121 #define TBIMR_FAST_CLIP REG_BIT(5) 122 123 #define FF_MODE XE_REG_MCR(0x6210) 124 #define DIS_TE_AUTOSTRIP REG_BIT(31) 125 #define VS_HIT_MAX_VALUE_MASK REG_GENMASK(25, 20) 126 #define DIS_MESH_PARTIAL_AUTOSTRIP REG_BIT(16) 127 #define DIS_MESH_AUTOSTRIP REG_BIT(15) 128 129 #define VFLSKPD XE_REG_MCR(0x62a8, XE_REG_OPTION_MASKED) 130 #define DIS_PARTIAL_AUTOSTRIP REG_BIT(9) 131 #define DIS_AUTOSTRIP REG_BIT(6) 132 #define DIS_OVER_FETCH_CACHE REG_BIT(1) 133 #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0) 134 135 #define FF_MODE2 XE_REG(0x6604) 136 #define XEHP_FF_MODE2 XE_REG_MCR(0x6604) 137 #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) 138 #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224) 139 #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16) 140 #define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4) 141 142 #define XEHPG_INSTDONE_GEOM_SVGUNIT XE_REG_MCR(0x666c) 143 144 #define CACHE_MODE_1 XE_REG(0x7004, XE_REG_OPTION_MASKED) 145 #define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11) 146 147 #define COMMON_SLICE_CHICKEN1 XE_REG(0x7010, XE_REG_OPTION_MASKED) 148 #define DISABLE_BOTTOM_CLIP_RECTANGLE_TEST REG_BIT(14) 149 150 #define HIZ_CHICKEN XE_REG(0x7018, XE_REG_OPTION_MASKED) 151 #define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14) 152 #define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13) 153 154 #define XEHP_PSS_MODE2 XE_REG_MCR(0x703c, XE_REG_OPTION_MASKED) 155 #define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) 156 157 #define XEHP_PSS_CHICKEN XE_REG_MCR(0x7044, XE_REG_OPTION_MASKED) 158 #define FLSH_IGNORES_PSD REG_BIT(10) 159 #define FD_END_COLLECT REG_BIT(5) 160 161 #define SC_INSTDONE XE_REG(0x7100) 162 #define SC_INSTDONE_EXTRA XE_REG(0x7104) 163 #define SC_INSTDONE_EXTRA2 XE_REG(0x7108) 164 165 #define XEHPG_SC_INSTDONE XE_REG_MCR(0x7100) 166 #define XEHPG_SC_INSTDONE_EXTRA XE_REG_MCR(0x7104) 167 #define XEHPG_SC_INSTDONE_EXTRA2 XE_REG_MCR(0x7108) 168 169 #define COMMON_SLICE_CHICKEN4 XE_REG(0x7300, XE_REG_OPTION_MASKED) 170 #define SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE REG_BIT(12) 171 #define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6) 172 173 #define COMMON_SLICE_CHICKEN3 XE_REG(0x7304, XE_REG_OPTION_MASKED) 174 #define XEHP_COMMON_SLICE_CHICKEN3 XE_REG_MCR(0x7304, XE_REG_OPTION_MASKED) 175 #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12) 176 #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12) 177 #define BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11) 178 #define DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9) 179 180 #define XEHP_SLICE_COMMON_ECO_CHICKEN1 XE_REG_MCR(0x731c, XE_REG_OPTION_MASKED) 181 #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14) 182 #define FAST_CLEAR_VALIGN_FIX REG_BIT(13) 183 184 #define XE2LPM_CCCHKNREG1 XE_REG(0x82a8) 185 186 #define VF_PREEMPTION XE_REG(0x83a4, XE_REG_OPTION_MASKED) 187 #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0) 188 189 #define VF_SCRATCHPAD XE_REG(0x83a8, XE_REG_OPTION_MASKED) 190 #define XE2_VFG_TED_CREDIT_INTERFACE_DISABLE REG_BIT(13) 191 192 #define VFG_PREEMPTION_CHICKEN XE_REG(0x83b4, XE_REG_OPTION_MASKED) 193 #define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4) 194 195 #define SQCNT1 XE_REG_MCR(0x8718) 196 #define XELPMP_SQCNT1 XE_REG(0x8718) 197 #define SQCNT1_PMON_ENABLE REG_BIT(30) 198 #define SQCNT1_OABPC REG_BIT(29) 199 #define ENFORCE_RAR REG_BIT(23) 200 201 #define XEHP_SQCM XE_REG_MCR(0x8724) 202 #define EN_32B_ACCESS REG_BIT(30) 203 204 #define XE2_FLAT_CCS_BASE_RANGE_LOWER XE_REG_MCR(0x8800) 205 #define XE2_FLAT_CCS_ENABLE REG_BIT(0) 206 #define XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK REG_GENMASK(31, 6) 207 208 #define XE2_FLAT_CCS_BASE_RANGE_UPPER XE_REG_MCR(0x8804) 209 #define XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK REG_GENMASK(7, 0) 210 211 #define GSCPSMI_BASE XE_REG(0x880c) 212 213 #define CCCHKNREG1 XE_REG_MCR(0x8828) 214 #define L3CMPCTRL REG_BIT(23) 215 #define ENCOMPPERFFIX REG_BIT(18) 216 217 /* Fuse readout registers for GT */ 218 #define XEHP_FUSE4 XE_REG(0x9114) 219 #define CFEG_WMTP_DISABLE REG_BIT(20) 220 #define CCS_EN_MASK REG_GENMASK(19, 16) 221 #define GT_L3_EXC_MASK REG_GENMASK(6, 4) 222 223 #define MIRROR_FUSE3 XE_REG(0x9118) 224 #define XE2_NODE_ENABLE_MASK REG_GENMASK(31, 16) 225 #define L3BANK_PAIR_COUNT 4 226 #define XEHPC_GT_L3_MODE_MASK REG_GENMASK(7, 4) 227 #define XE2_GT_L3_MODE_MASK REG_GENMASK(7, 4) 228 #define L3BANK_MASK REG_GENMASK(3, 0) 229 #define XELP_GT_L3_MODE_MASK REG_GENMASK(7, 0) 230 /* on Xe_HP the same fuses indicates mslices instead of L3 banks */ 231 #define MAX_MSLICES 4 232 #define MEML3_EN_MASK REG_GENMASK(3, 0) 233 234 #define MIRROR_FUSE1 XE_REG(0x911c) 235 236 #define FUSE2 XE_REG(0x9120) 237 #define PRODUCTION_HW REG_BIT(2) 238 239 #define MIRROR_L3BANK_ENABLE XE_REG(0x9130) 240 #define XE3_L3BANK_ENABLE REG_GENMASK(31, 0) 241 242 #define XELP_EU_ENABLE XE_REG(0x9134) /* "_DISABLE" on Xe_LP */ 243 #define XELP_EU_MASK REG_GENMASK(7, 0) 244 #define XELP_GT_SLICE_ENABLE XE_REG(0x9138) 245 #define XELP_GT_GEOMETRY_DSS_ENABLE XE_REG(0x913c) 246 247 #define GT_VEBOX_VDBOX_DISABLE XE_REG(0x9140) 248 #define GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16) 249 #define GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0) 250 251 #define XEHP_GT_COMPUTE_DSS_ENABLE XE_REG(0x9144) 252 #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT XE_REG(0x9148) 253 #define XE2_GT_COMPUTE_DSS_2 XE_REG(0x914c) 254 #define XE2_GT_GEOMETRY_DSS_1 XE_REG(0x9150) 255 #define XE2_GT_GEOMETRY_DSS_2 XE_REG(0x9154) 256 257 #define SERVICE_COPY_ENABLE XE_REG(0x9170) 258 #define FUSE_SERVICE_COPY_ENABLE_MASK REG_GENMASK(7, 0) 259 260 #define GDRST XE_REG(0x941c) 261 #define GRDOM_GUC REG_BIT(3) 262 #define GRDOM_FULL REG_BIT(0) 263 264 #define MISCCPCTL XE_REG(0x9424) 265 #define DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1) 266 267 #define UNSLCGCTL9430 XE_REG(0x9430) 268 #define MSQDUNIT_CLKGATE_DIS REG_BIT(3) 269 270 #define UNSLICE_UNIT_LEVEL_CLKGATE XE_REG(0x9434) 271 #define VFUNIT_CLKGATE_DIS REG_BIT(20) 272 #define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */ 273 #define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */ 274 #define GAMEDIA_CLKGATE_DIS REG_BIT(11) 275 #define HSUNIT_CLKGATE_DIS REG_BIT(8) 276 #define VSUNIT_CLKGATE_DIS REG_BIT(3) 277 278 #define UNSLCGCTL9440 XE_REG(0x9440) 279 #define GAMTLBOACS_CLKGATE_DIS REG_BIT(28) 280 #define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27) 281 #define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26) 282 #define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24) 283 #define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23) 284 #define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22) 285 #define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21) 286 #define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17) 287 #define GAMTLBKCR_CLKGATE_DIS REG_BIT(16) 288 #define GAMTLBGUC_CLKGATE_DIS REG_BIT(15) 289 #define GAMTLBBLT_CLKGATE_DIS REG_BIT(14) 290 #define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6) 291 292 #define UNSLCGCTL9444 XE_REG(0x9444) 293 #define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30) 294 #define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29) 295 #define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28) 296 #define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27) 297 #define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26) 298 #define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25) 299 #define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24) 300 #define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23) 301 #define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22) 302 #define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21) 303 #define GAMTLBMERT_CLKGATE_DIS REG_BIT(20) 304 #define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19) 305 #define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18) 306 #define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17) 307 #define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16) 308 #define LTCDD_CLKGATE_DIS REG_BIT(10) 309 310 #define UNSLCGCTL9454 XE_REG(0x9454) 311 #define LSCFE_CLKGATE_DIS REG_BIT(4) 312 313 #define XEHP_SLICE_UNIT_LEVEL_CLKGATE XE_REG_MCR(0x94d4) 314 #define L3_CR2X_CLKGATE_DIS REG_BIT(17) 315 #define L3_CLKGATE_DIS REG_BIT(16) 316 #define NODEDSS_CLKGATE_DIS REG_BIT(12) 317 #define MSCUNIT_CLKGATE_DIS REG_BIT(10) 318 #define RCCUNIT_CLKGATE_DIS REG_BIT(7) 319 #define SARBUNIT_CLKGATE_DIS REG_BIT(5) 320 #define SBEUNIT_CLKGATE_DIS REG_BIT(4) 321 322 #define UNSLICE_UNIT_LEVEL_CLKGATE2 XE_REG(0x94e4) 323 #define VSUNIT_CLKGATE2_DIS REG_BIT(19) 324 325 #define SUBSLICE_UNIT_LEVEL_CLKGATE XE_REG_MCR(0x9524) 326 #define DSS_ROUTER_CLKGATE_DIS REG_BIT(28) 327 #define GWUNIT_CLKGATE_DIS REG_BIT(16) 328 329 #define SUBSLICE_UNIT_LEVEL_CLKGATE2 XE_REG_MCR(0x9528) 330 #define CPSSUNIT_CLKGATE_DIS REG_BIT(9) 331 332 #define SSMCGCTL9530 XE_REG_MCR(0x9530) 333 #define RTFUNIT_CLKGATE_DIS REG_BIT(18) 334 335 #define DFR_RATIO_EN_AND_CHICKEN XE_REG_MCR(0x9550) 336 #define DFR_DISABLE REG_BIT(9) 337 338 #define RPNSWREQ XE_REG(0xa008) 339 #define REQ_RATIO_MASK REG_GENMASK(31, 23) 340 341 #define RP_CONTROL XE_REG(0xa024) 342 #define RPSWCTL_MASK REG_GENMASK(10, 9) 343 #define RPSWCTL_ENABLE REG_FIELD_PREP(RPSWCTL_MASK, 2) 344 #define RPSWCTL_DISABLE REG_FIELD_PREP(RPSWCTL_MASK, 0) 345 #define RC_CONTROL XE_REG(0xa090) 346 #define RC_CTL_HW_ENABLE REG_BIT(31) 347 #define RC_CTL_TO_MODE REG_BIT(28) 348 #define RC_CTL_RC6_ENABLE REG_BIT(18) 349 #define RC_STATE XE_REG(0xa094) 350 #define RC_IDLE_HYSTERSIS XE_REG(0xa0ac) 351 #define MEDIA_POWERGATE_IDLE_HYSTERESIS XE_REG(0xa0c4) 352 #define RENDER_POWERGATE_IDLE_HYSTERESIS XE_REG(0xa0c8) 353 354 #define PMINTRMSK XE_REG(0xa168) 355 #define PMINTR_DISABLE_REDIRECT_TO_GUC REG_BIT(31) 356 #define ARAT_EXPIRED_INTRMSK REG_BIT(9) 357 358 #define FORCEWAKE_GT XE_REG(0xa188) 359 360 #define POWERGATE_ENABLE XE_REG(0xa210) 361 #define RENDER_POWERGATE_ENABLE REG_BIT(0) 362 #define MEDIA_POWERGATE_ENABLE REG_BIT(1) 363 #define MEDIA_SAMPLERS_POWERGATE_ENABLE REG_BIT(2) 364 #define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n)) 365 #define VDN_MFXVDENC_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n)) 366 367 #define FORCEWAKE_RENDER XE_REG(0xa278) 368 369 #define POWERGATE_DOMAIN_STATUS XE_REG(0xa2a0) 370 #define MEDIA_SLICE3_AWAKE_STATUS REG_BIT(4) 371 #define MEDIA_SLICE2_AWAKE_STATUS REG_BIT(3) 372 #define MEDIA_SLICE1_AWAKE_STATUS REG_BIT(2) 373 #define RENDER_AWAKE_STATUS REG_BIT(1) 374 #define MEDIA_SLICE0_AWAKE_STATUS REG_BIT(0) 375 376 #define MISC_STATUS_0 XE_REG(0xa500) 377 378 #define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4) 379 #define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4) 380 #define FORCEWAKE_GSC XE_REG(0xa618) 381 382 #define XELP_GARBCNTL XE_REG(0xb004) 383 #define XELP_BUS_HASH_CTL_BIT_EXC REG_BIT(7) 384 385 #define XEHPC_LNCFMISCCFGREG0 XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED) 386 #define XEHPC_OVRLSCCC REG_BIT(0) 387 388 #define LNCFCMOCS_REG_COUNT 32 389 #define XELP_LNCFCMOCS(i) XE_REG(0xb020 + (i) * 4) 390 #define XEHP_LNCFCMOCS(i) XE_REG_MCR(0xb020 + (i) * 4) 391 #define L3_UPPER_LKUP_MASK REG_BIT(23) 392 #define L3_UPPER_GLBGO_MASK REG_BIT(22) 393 #define L3_UPPER_IDX_CACHEABILITY_MASK REG_GENMASK(21, 20) 394 #define L3_UPPER_IDX_SCC_MASK REG_GENMASK(19, 17) 395 #define L3_UPPER_IDX_ESC_MASK REG_BIT(16) 396 #define L3_LKUP_MASK REG_BIT(7) 397 #define L3_LKUP(value) REG_FIELD_PREP(L3_LKUP_MASK, value) 398 #define L3_GLBGO_MASK REG_BIT(6) 399 #define L3_GLBGO(value) REG_FIELD_PREP(L3_GLBGO_MASK, value) 400 #define L3_CACHEABILITY_MASK REG_GENMASK(5, 4) 401 #define L3_CACHEABILITY(value) REG_FIELD_PREP(L3_CACHEABILITY_MASK, value) 402 #define L3_SCC_MASK REG_GENMASK(3, 1) 403 #define L3_SCC(value) REG_FIELD_PREP(L3_SCC_MASK, value) 404 #define L3_ESC_MASK REG_BIT(0) 405 #define L3_ESC(value) REG_FIELD_PREP(L3_ESC_MASK, value) 406 407 #define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4) 408 #define XEHP_LNESPARE REG_BIT(19) 409 410 #define LSN_VC_REG2 XE_REG_MCR(0xb0c8) 411 #define LSN_LNI_WGT_MASK REG_GENMASK(31, 28) 412 #define LSN_LNI_WGT(value) REG_FIELD_PREP(LSN_LNI_WGT_MASK, value) 413 #define LSN_LNE_WGT_MASK REG_GENMASK(27, 24) 414 #define LSN_LNE_WGT(value) REG_FIELD_PREP(LSN_LNE_WGT_MASK, value) 415 #define LSN_DIM_X_WGT_MASK REG_GENMASK(23, 20) 416 #define LSN_DIM_X_WGT(value) REG_FIELD_PREP(LSN_DIM_X_WGT_MASK, value) 417 #define LSN_DIM_Y_WGT_MASK REG_GENMASK(19, 16) 418 #define LSN_DIM_Y_WGT(value) REG_FIELD_PREP(LSN_DIM_Y_WGT_MASK, value) 419 #define LSN_DIM_Z_WGT_MASK REG_GENMASK(15, 12) 420 #define LSN_DIM_Z_WGT(value) REG_FIELD_PREP(LSN_DIM_Z_WGT_MASK, value) 421 422 #define L3SQCREG2 XE_REG_MCR(0xb104) 423 #define COMPMEMRD256BOVRFETCHEN REG_BIT(20) 424 425 #define L3SQCREG3 XE_REG_MCR(0xb108) 426 #define COMPPWOVERFETCHEN REG_BIT(28) 427 428 #define SCRATCH3_LBCF XE_REG_MCR(0xb154) 429 #define RWFLUSHALLEN REG_BIT(17) 430 431 #define XEHP_L3SQCREG5 XE_REG_MCR(0xb158) 432 #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0) 433 434 #define XEHP_L3SCQREG7 XE_REG_MCR(0xb188) 435 #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3) 436 437 #define XEHPC_L3CLOS_MASK(i) XE_REG_MCR(0xb194 + (i) * 8) 438 439 #define XE2_GLOBAL_INVAL XE_REG(0xb404) 440 441 #define XE2LPM_L3SQCREG2 XE_REG_MCR(0xb604) 442 443 #define XE2LPM_L3SQCREG3 XE_REG_MCR(0xb608) 444 445 #define XE2LPM_SCRATCH3_LBCF XE_REG_MCR(0xb654) 446 447 #define XE2LPM_L3SQCREG5 XE_REG_MCR(0xb658) 448 449 #define XE2_TDF_CTRL XE_REG(0xb418) 450 #define TRANSIENT_FLUSH_REQUEST REG_BIT(0) 451 452 #define XEHP_MERT_MOD_CTRL XE_REG_MCR(0xcf28) 453 #define RENDER_MOD_CTRL XE_REG_MCR(0xcf2c) 454 #define COMP_MOD_CTRL XE_REG_MCR(0xcf30) 455 #define XEHP_VDBX_MOD_CTRL XE_REG_MCR(0xcf34) 456 #define XELPMP_VDBX_MOD_CTRL XE_REG(0xcf34) 457 #define XEHP_VEBX_MOD_CTRL XE_REG_MCR(0xcf38) 458 #define XELPMP_VEBX_MOD_CTRL XE_REG(0xcf38) 459 #define FORCE_MISS_FTLB REG_BIT(3) 460 461 #define XEHP_GAMSTLB_CTRL XE_REG_MCR(0xcf4c) 462 #define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12) 463 #define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11) 464 #define TAG_BLOCK_CLKGATE_DIS REG_BIT(7) 465 466 #define XEHP_GAMCNTRL_CTRL XE_REG_MCR(0xcf54) 467 #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12) 468 #define GLOBAL_INVALIDATION_MODE REG_BIT(2) 469 470 #define LMEM_CFG XE_REG(0xcf58) 471 #define LMEM_EN REG_BIT(31) 472 #define LMTT_DIR_PTR REG_GENMASK(30, 0) /* in multiples of 64KB */ 473 474 #define HALF_SLICE_CHICKEN5 XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED) 475 #define DISABLE_SAMPLE_G_PERFORMANCE REG_BIT(0) 476 477 #define SAMPLER_INSTDONE XE_REG_MCR(0xe160) 478 #define ROW_INSTDONE XE_REG_MCR(0xe164) 479 480 #define SAMPLER_MODE XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED) 481 #define ENABLE_SMALLPL REG_BIT(15) 482 #define SMP_WAIT_FETCH_MERGING_COUNTER REG_GENMASK(11, 10) 483 #define SMP_FORCE_128B_OVERFETCH REG_FIELD_PREP(SMP_WAIT_FETCH_MERGING_COUNTER, 1) 484 #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) 485 #define SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) 486 #define INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0) 487 488 #define HALF_SLICE_CHICKEN7 XE_REG_MCR(0xe194, XE_REG_OPTION_MASKED) 489 #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15) 490 #define CLEAR_OPTIMIZATION_DISABLE REG_BIT(6) 491 492 #define CACHE_MODE_SS XE_REG_MCR(0xe420, XE_REG_OPTION_MASKED) 493 #define DISABLE_ECC REG_BIT(5) 494 #define ENABLE_PREFETCH_INTO_IC REG_BIT(3) 495 496 #define ROW_CHICKEN4 XE_REG_MCR(0xe48c, XE_REG_OPTION_MASKED) 497 #define DISABLE_GRF_CLEAR REG_BIT(13) 498 #define XEHP_DIS_BBL_SYSPIPE REG_BIT(11) 499 #define DISABLE_TDL_PUSH REG_BIT(9) 500 #define DIS_PICK_2ND_EU REG_BIT(7) 501 #define DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4) 502 #define THREAD_EX_ARB_MODE REG_GENMASK(3, 2) 503 #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2) 504 505 #define ROW_CHICKEN3 XE_REG_MCR(0xe49c, XE_REG_OPTION_MASKED) 506 #define XE2_EUPEND_CHK_FLUSH_DIS REG_BIT(14) 507 #define DIS_FIX_EOT1_FLUSH REG_BIT(9) 508 509 #define TDL_TSL_CHICKEN XE_REG_MCR(0xe4c4, XE_REG_OPTION_MASKED) 510 #define STK_ID_RESTRICT REG_BIT(12) 511 #define SLM_WMTP_RESTORE REG_BIT(11) 512 #define RES_CHK_SPR_DIS REG_BIT(6) 513 514 #define ROW_CHICKEN XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED) 515 #define UGM_BACKUP_MODE REG_BIT(13) 516 #define MDQ_ARBITRATION_MODE REG_BIT(12) 517 #define STALL_DOP_GATING_DISABLE REG_BIT(5) 518 #define EARLY_EOT_DIS REG_BIT(1) 519 520 #define ROW_CHICKEN2 XE_REG_MCR(0xe4f4, XE_REG_OPTION_MASKED) 521 #define DISABLE_READ_SUPPRESSION REG_BIT(15) 522 #define DISABLE_EARLY_READ REG_BIT(14) 523 #define ENABLE_LARGE_GRF_MODE REG_BIT(12) 524 #define PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8) 525 #define DISABLE_TDL_SVHS_GATING REG_BIT(1) 526 #define DISABLE_DOP_GATING REG_BIT(0) 527 528 #define RT_CTRL XE_REG_MCR(0xe530) 529 #define DIS_NULL_QUERY REG_BIT(10) 530 531 #define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK XE_REG_MCR(0xe534) 532 #define EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT REG_BIT(31) 533 534 #define XEHP_HDC_CHICKEN0 XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED) 535 #define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11) 536 #define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3) 537 538 #define TDL_CHICKEN XE_REG_MCR(0xe5f4, XE_REG_OPTION_MASKED) 539 #define QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE REG_BIT(12) 540 #define EUSTALL_PERF_SAMPLING_DISABLE REG_BIT(5) 541 542 #define LSC_CHICKEN_BIT_0 XE_REG_MCR(0xe7c8) 543 #define DISABLE_D8_D16_COASLESCE REG_BIT(30) 544 #define WR_REQ_CHAINING_DIS REG_BIT(26) 545 #define TGM_WRITE_EOM_FORCE REG_BIT(17) 546 #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) 547 #define SEQUENTIAL_ACCESS_UPGRADE_DISABLE REG_BIT(13) 548 549 #define LSC_CHICKEN_BIT_0_UDW XE_REG_MCR(0xe7c8 + 4) 550 #define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32) 551 #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32) 552 #define XE2_ALLOC_DPA_STARVE_FIX_DIS REG_BIT(47 - 32) 553 #define ENABLE_SMP_LD_RENDER_SURFACE_CONTROL REG_BIT(44 - 32) 554 #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32) 555 #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32) 556 #define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32) 557 #define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32) 558 559 #define SARB_CHICKEN1 XE_REG_MCR(0xe90c) 560 #define COMP_CKN_IN REG_GENMASK(30, 29) 561 562 #define MAIN_GAMCTRL_MODE XE_REG(0xef00) 563 #define MAIN_GAMCTRL_QUEUE_SELECT REG_BIT(0) 564 565 #define RCU_MODE XE_REG(0x14800, XE_REG_OPTION_MASKED) 566 #define RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1) 567 #define RCU_MODE_CCS_ENABLE REG_BIT(0) 568 569 /* 570 * Total of 4 cslices, where each cslice is in the form: 571 * [0-3] CCS ID 572 * [4-6] RSVD 573 * [7] Disabled 574 */ 575 #define CCS_MODE XE_REG(0x14804, XE_REG_OPTION_MASKED) 576 #define CCS_MODE_CSLICE_0_3_MASK REG_GENMASK(11, 0) /* 3 bits per cslice */ 577 #define CCS_MODE_CSLICE_MASK 0x7 /* CCS0-3 + rsvd */ 578 #define CCS_MODE_CSLICE_WIDTH ilog2(CCS_MODE_CSLICE_MASK + 1) 579 #define CCS_MODE_CSLICE(cslice, ccs) \ 580 ((ccs) << ((cslice) * CCS_MODE_CSLICE_WIDTH)) 581 582 #define FORCEWAKE_ACK_GT XE_REG(0x130044) 583 584 /* Applicable for all FORCEWAKE_DOMAIN and FORCEWAKE_ACK_DOMAIN regs */ 585 #define FORCEWAKE_KERNEL 0 586 #define FORCEWAKE_MT(bit) BIT(bit) 587 #define FORCEWAKE_MT_MASK(bit) BIT((bit) + 16) 588 589 #define MTL_MEDIA_PERF_LIMIT_REASONS XE_REG(0x138030) 590 #define MTL_MEDIA_MC6 XE_REG(0x138048) 591 592 #define GT_CORE_STATUS XE_REG(0x138060) 593 #define RCN_MASK REG_GENMASK(2, 0) 594 #define GT_C0 0 595 #define GT_C6 3 596 597 #define GT_GFX_RC6_LOCKED XE_REG(0x138104) 598 #define GT_GFX_RC6 XE_REG(0x138108) 599 600 #define GT0_PERF_LIMIT_REASONS XE_REG(0x1381a8) 601 /* Common performance limit reason bits - available on all platforms */ 602 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 603 #define PROCHOT_MASK REG_BIT(0) 604 #define THERMAL_LIMIT_MASK REG_BIT(1) 605 #define RATL_MASK REG_BIT(5) 606 #define VR_THERMALERT_MASK REG_BIT(6) 607 #define VR_TDC_MASK REG_BIT(7) 608 #define POWER_LIMIT_4_MASK REG_BIT(8) 609 #define POWER_LIMIT_1_MASK REG_BIT(10) 610 #define POWER_LIMIT_2_MASK REG_BIT(11) 611 /* Platform-specific performance limit reason bits - for Crescent Island */ 612 #define CRI_PERF_LIMIT_REASONS_MASK 0xfdff 613 #define SOC_THERMAL_LIMIT_MASK REG_BIT(1) 614 #define MEM_THERMAL_MASK REG_BIT(2) 615 #define VR_THERMAL_MASK REG_BIT(3) 616 #define ICCMAX_MASK REG_BIT(4) 617 #define SOC_AVG_THERMAL_MASK REG_BIT(6) 618 #define FASTVMODE_MASK REG_BIT(7) 619 #define PSYS_PL1_MASK REG_BIT(12) 620 #define PSYS_PL2_MASK REG_BIT(13) 621 #define P0_FREQ_MASK REG_BIT(14) 622 #define PSYS_CRIT_MASK REG_BIT(15) 623 624 #define GT_PERF_STATUS XE_REG(0x1381b4) 625 #define VOLTAGE_MASK REG_GENMASK(10, 0) 626 627 #define SFC_DONE(n) XE_REG(0x1cc000 + (n) * 0x1000) 628 629 #endif 630