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Searched refs:UNORD_DISPATCH (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dcikd.h1526 #define UNORD_DISPATCH (1 << 28) macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v11_0.c1479 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); in mes_v11_0_mqd_init()
H A Dmes_v12_1.c1324 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); in mes_v12_1_mqd_init()
H A Dmes_v12_0.c1548 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); in mes_v12_0_mqd_init()
H A Dgfx_v9_4_3.c1845 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v9_4_3_xcc_mqd_init()
H A Dgfx_v12_1.c2511 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v12_1_compute_mqd_init()
H A Dgfx_v12_0.c3249 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); in gfx_v12_0_compute_mqd_init()
H A Dgfx_v8_0.c4472 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v8_0_mqd_init()
H A Dgfx_v9_0.c3636 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v9_0_mqd_init()
H A Dgfx_v11_0.c4408 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); in gfx_v11_0_compute_mqd_init()
H A Dgfx_v10_0.c6991 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); in gfx_v10_0_compute_mqd_init()