1 /* 2 * Copyright (C) 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _cyan_skillfish_ip_offset_HEADER 22 #define _cyan_skillfish_ip_offset_HEADER 23 24 #define MAX_INSTANCE 6 25 #define MAX_SEGMENT 5 26 27 28 struct IP_BASE_INSTANCE { 29 unsigned int segment[MAX_SEGMENT]; 30 } __maybe_unused; 31 32 struct IP_BASE { 33 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 34 } __maybe_unused; 35 36 37 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0, 0, 0, 0 } }, 38 { { 0, 0, 0, 0, 0 } }, 39 { { 0, 0, 0, 0, 0 } }, 40 { { 0, 0, 0, 0, 0 } }, 41 { { 0, 0, 0, 0, 0 } }, 42 { { 0, 0, 0, 0, 0 } } } }; 43 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0, 0, 0, 0 } }, 44 { { 0x00016E00, 0, 0, 0, 0 } }, 45 { { 0x00017000, 0, 0, 0, 0 } }, 46 { { 0x00017200, 0, 0, 0, 0 } }, 47 { { 0x00017E00, 0, 0, 0, 0 } }, 48 { { 0x0001B000, 0, 0, 0, 0 } } } }; 49 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0 } }, 50 { { 0, 0, 0, 0, 0 } }, 51 { { 0, 0, 0, 0, 0 } }, 52 { { 0, 0, 0, 0, 0 } }, 53 { { 0, 0, 0, 0, 0 } }, 54 { { 0, 0, 0, 0, 0 } } } }; 55 static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0 } }, 56 { { 0, 0, 0, 0, 0 } }, 57 { { 0, 0, 0, 0, 0 } }, 58 { { 0, 0, 0, 0, 0 } }, 59 { { 0, 0, 0, 0, 0 } }, 60 { { 0, 0, 0, 0, 0 } } } }; 61 static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0, 0 } }, 62 { { 0, 0, 0, 0, 0 } }, 63 { { 0, 0, 0, 0, 0 } }, 64 { { 0, 0, 0, 0, 0 } }, 65 { { 0, 0, 0, 0, 0 } }, 66 { { 0, 0, 0, 0, 0 } } } }; 67 static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0, 0, 0 } }, 68 { { 0, 0, 0, 0, 0 } }, 69 { { 0, 0, 0, 0, 0 } }, 70 { { 0, 0, 0, 0, 0 } }, 71 { { 0, 0, 0, 0, 0 } }, 72 { { 0, 0, 0, 0, 0 } } } }; 73 static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0, 0, 0, 0 } }, 74 { { 0, 0, 0, 0, 0 } }, 75 { { 0, 0, 0, 0, 0 } }, 76 { { 0, 0, 0, 0, 0 } }, 77 { { 0, 0, 0, 0, 0 } }, 78 { { 0, 0, 0, 0, 0 } } } }; 79 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0 } }, 80 { { 0, 0, 0, 0, 0 } }, 81 { { 0, 0, 0, 0, 0 } }, 82 { { 0, 0, 0, 0, 0 } }, 83 { { 0, 0, 0, 0, 0 } }, 84 { { 0, 0, 0, 0, 0 } } } }; 85 static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0 } }, 86 { { 0, 0, 0, 0, 0 } }, 87 { { 0, 0, 0, 0, 0 } }, 88 { { 0, 0, 0, 0, 0 } }, 89 { { 0, 0, 0, 0, 0 } }, 90 { { 0, 0, 0, 0, 0 } } } }; 91 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0 } }, 92 { { 0, 0, 0, 0, 0 } }, 93 { { 0, 0, 0, 0, 0 } }, 94 { { 0, 0, 0, 0, 0 } }, 95 { { 0, 0, 0, 0, 0 } }, 96 { { 0, 0, 0, 0, 0 } } } }; 97 static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, 98 { { 0, 0, 0, 0, 0 } }, 99 { { 0, 0, 0, 0, 0 } }, 100 { { 0, 0, 0, 0, 0 } }, 101 { { 0, 0, 0, 0, 0 } }, 102 { { 0, 0, 0, 0, 0 } } } }; 103 static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0 } }, 104 { { 0, 0, 0, 0, 0 } }, 105 { { 0, 0, 0, 0, 0 } }, 106 { { 0, 0, 0, 0, 0 } }, 107 { { 0, 0, 0, 0, 0 } }, 108 { { 0, 0, 0, 0, 0 } } } }; 109 static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0 } }, 110 { { 0, 0, 0, 0, 0 } }, 111 { { 0, 0, 0, 0, 0 } }, 112 { { 0, 0, 0, 0, 0 } }, 113 { { 0, 0, 0, 0, 0 } }, 114 { { 0, 0, 0, 0, 0 } } } }; 115 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0 } }, 116 { { 0, 0, 0, 0, 0 } }, 117 { { 0, 0, 0, 0, 0 } }, 118 { { 0, 0, 0, 0, 0 } }, 119 { { 0, 0, 0, 0, 0 } }, 120 { { 0, 0, 0, 0, 0 } } } }; 121 static const struct IP_BASE UMC0_BASE ={ { { { 0x00014000, 0, 0, 0, 0 } }, 122 { { 0, 0, 0, 0, 0 } }, 123 { { 0, 0, 0, 0, 0 } }, 124 { { 0, 0, 0, 0, 0 } }, 125 { { 0, 0, 0, 0, 0 } }, 126 { { 0, 0, 0, 0, 0 } } } }; 127 static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, 128 { { 0, 0, 0, 0, 0 } }, 129 { { 0, 0, 0, 0, 0 } }, 130 { { 0, 0, 0, 0, 0 } }, 131 { { 0, 0, 0, 0, 0 } }, 132 { { 0, 0, 0, 0, 0 } } } }; 133 134 135 #define ATHUB_BASE__INST0_SEG0 0x00000C00 136 #define ATHUB_BASE__INST0_SEG1 0 137 #define ATHUB_BASE__INST0_SEG2 0 138 #define ATHUB_BASE__INST0_SEG3 0 139 #define ATHUB_BASE__INST0_SEG4 0 140 141 #define ATHUB_BASE__INST1_SEG0 0 142 #define ATHUB_BASE__INST1_SEG1 0 143 #define ATHUB_BASE__INST1_SEG2 0 144 #define ATHUB_BASE__INST1_SEG3 0 145 #define ATHUB_BASE__INST1_SEG4 0 146 147 #define ATHUB_BASE__INST2_SEG0 0 148 #define ATHUB_BASE__INST2_SEG1 0 149 #define ATHUB_BASE__INST2_SEG2 0 150 #define ATHUB_BASE__INST2_SEG3 0 151 #define ATHUB_BASE__INST2_SEG4 0 152 153 #define ATHUB_BASE__INST3_SEG0 0 154 #define ATHUB_BASE__INST3_SEG1 0 155 #define ATHUB_BASE__INST3_SEG2 0 156 #define ATHUB_BASE__INST3_SEG3 0 157 #define ATHUB_BASE__INST3_SEG4 0 158 159 #define ATHUB_BASE__INST4_SEG0 0 160 #define ATHUB_BASE__INST4_SEG1 0 161 #define ATHUB_BASE__INST4_SEG2 0 162 #define ATHUB_BASE__INST4_SEG3 0 163 #define ATHUB_BASE__INST4_SEG4 0 164 165 #define ATHUB_BASE__INST5_SEG0 0 166 #define ATHUB_BASE__INST5_SEG1 0 167 #define ATHUB_BASE__INST5_SEG2 0 168 #define ATHUB_BASE__INST5_SEG3 0 169 #define ATHUB_BASE__INST5_SEG4 0 170 171 #define CLK_BASE__INST0_SEG0 0x00016C00 172 #define CLK_BASE__INST0_SEG1 0 173 #define CLK_BASE__INST0_SEG2 0 174 #define CLK_BASE__INST0_SEG3 0 175 #define CLK_BASE__INST0_SEG4 0 176 177 #define CLK_BASE__INST1_SEG0 0x00016E00 178 #define CLK_BASE__INST1_SEG1 0 179 #define CLK_BASE__INST1_SEG2 0 180 #define CLK_BASE__INST1_SEG3 0 181 #define CLK_BASE__INST1_SEG4 0 182 183 #define CLK_BASE__INST2_SEG0 0x00017000 184 #define CLK_BASE__INST2_SEG1 0 185 #define CLK_BASE__INST2_SEG2 0 186 #define CLK_BASE__INST2_SEG3 0 187 #define CLK_BASE__INST2_SEG4 0 188 189 #define CLK_BASE__INST3_SEG0 0x00017200 190 #define CLK_BASE__INST3_SEG1 0 191 #define CLK_BASE__INST3_SEG2 0 192 #define CLK_BASE__INST3_SEG3 0 193 #define CLK_BASE__INST3_SEG4 0 194 195 #define CLK_BASE__INST4_SEG0 0x00017E00 196 #define CLK_BASE__INST4_SEG1 0 197 #define CLK_BASE__INST4_SEG2 0 198 #define CLK_BASE__INST4_SEG3 0 199 #define CLK_BASE__INST4_SEG4 0 200 201 #define CLK_BASE__INST5_SEG0 0x0001B000 202 #define CLK_BASE__INST5_SEG1 0 203 #define CLK_BASE__INST5_SEG2 0 204 #define CLK_BASE__INST5_SEG3 0 205 #define CLK_BASE__INST5_SEG4 0 206 207 #define DF_BASE__INST0_SEG0 0x00007000 208 #define DF_BASE__INST0_SEG1 0 209 #define DF_BASE__INST0_SEG2 0 210 #define DF_BASE__INST0_SEG3 0 211 #define DF_BASE__INST0_SEG4 0 212 213 #define DF_BASE__INST1_SEG0 0 214 #define DF_BASE__INST1_SEG1 0 215 #define DF_BASE__INST1_SEG2 0 216 #define DF_BASE__INST1_SEG3 0 217 #define DF_BASE__INST1_SEG4 0 218 219 #define DF_BASE__INST2_SEG0 0 220 #define DF_BASE__INST2_SEG1 0 221 #define DF_BASE__INST2_SEG2 0 222 #define DF_BASE__INST2_SEG3 0 223 #define DF_BASE__INST2_SEG4 0 224 225 #define DF_BASE__INST3_SEG0 0 226 #define DF_BASE__INST3_SEG1 0 227 #define DF_BASE__INST3_SEG2 0 228 #define DF_BASE__INST3_SEG3 0 229 #define DF_BASE__INST3_SEG4 0 230 231 #define DF_BASE__INST4_SEG0 0 232 #define DF_BASE__INST4_SEG1 0 233 #define DF_BASE__INST4_SEG2 0 234 #define DF_BASE__INST4_SEG3 0 235 #define DF_BASE__INST4_SEG4 0 236 237 #define DF_BASE__INST5_SEG0 0 238 #define DF_BASE__INST5_SEG1 0 239 #define DF_BASE__INST5_SEG2 0 240 #define DF_BASE__INST5_SEG3 0 241 #define DF_BASE__INST5_SEG4 0 242 243 #define DMU_BASE__INST0_SEG0 0x00000012 244 #define DMU_BASE__INST0_SEG1 0x000000C0 245 #define DMU_BASE__INST0_SEG2 0x000034C0 246 #define DMU_BASE__INST0_SEG3 0x00009000 247 #define DMU_BASE__INST0_SEG4 0 248 249 #define DMU_BASE__INST1_SEG0 0 250 #define DMU_BASE__INST1_SEG1 0 251 #define DMU_BASE__INST1_SEG2 0 252 #define DMU_BASE__INST1_SEG3 0 253 #define DMU_BASE__INST1_SEG4 0 254 255 #define DMU_BASE__INST2_SEG0 0 256 #define DMU_BASE__INST2_SEG1 0 257 #define DMU_BASE__INST2_SEG2 0 258 #define DMU_BASE__INST2_SEG3 0 259 #define DMU_BASE__INST2_SEG4 0 260 261 #define DMU_BASE__INST3_SEG0 0 262 #define DMU_BASE__INST3_SEG1 0 263 #define DMU_BASE__INST3_SEG2 0 264 #define DMU_BASE__INST3_SEG3 0 265 #define DMU_BASE__INST3_SEG4 0 266 267 #define DMU_BASE__INST4_SEG0 0 268 #define DMU_BASE__INST4_SEG1 0 269 #define DMU_BASE__INST4_SEG2 0 270 #define DMU_BASE__INST4_SEG3 0 271 #define DMU_BASE__INST4_SEG4 0 272 273 #define DMU_BASE__INST5_SEG0 0 274 #define DMU_BASE__INST5_SEG1 0 275 #define DMU_BASE__INST5_SEG2 0 276 #define DMU_BASE__INST5_SEG3 0 277 #define DMU_BASE__INST5_SEG4 0 278 279 #define FUSE_BASE__INST0_SEG0 0x00017400 280 #define FUSE_BASE__INST0_SEG1 0 281 #define FUSE_BASE__INST0_SEG2 0 282 #define FUSE_BASE__INST0_SEG3 0 283 #define FUSE_BASE__INST0_SEG4 0 284 285 #define FUSE_BASE__INST1_SEG0 0 286 #define FUSE_BASE__INST1_SEG1 0 287 #define FUSE_BASE__INST1_SEG2 0 288 #define FUSE_BASE__INST1_SEG3 0 289 #define FUSE_BASE__INST1_SEG4 0 290 291 #define FUSE_BASE__INST2_SEG0 0 292 #define FUSE_BASE__INST2_SEG1 0 293 #define FUSE_BASE__INST2_SEG2 0 294 #define FUSE_BASE__INST2_SEG3 0 295 #define FUSE_BASE__INST2_SEG4 0 296 297 #define FUSE_BASE__INST3_SEG0 0 298 #define FUSE_BASE__INST3_SEG1 0 299 #define FUSE_BASE__INST3_SEG2 0 300 #define FUSE_BASE__INST3_SEG3 0 301 #define FUSE_BASE__INST3_SEG4 0 302 303 #define FUSE_BASE__INST4_SEG0 0 304 #define FUSE_BASE__INST4_SEG1 0 305 #define FUSE_BASE__INST4_SEG2 0 306 #define FUSE_BASE__INST4_SEG3 0 307 #define FUSE_BASE__INST4_SEG4 0 308 309 #define FUSE_BASE__INST5_SEG0 0 310 #define FUSE_BASE__INST5_SEG1 0 311 #define FUSE_BASE__INST5_SEG2 0 312 #define FUSE_BASE__INST5_SEG3 0 313 #define FUSE_BASE__INST5_SEG4 0 314 315 #define GC_BASE__INST0_SEG0 0x00001260 316 #define GC_BASE__INST0_SEG1 0x0000A000 317 #define GC_BASE__INST0_SEG2 0 318 #define GC_BASE__INST0_SEG3 0 319 #define GC_BASE__INST0_SEG4 0 320 321 #define GC_BASE__INST1_SEG0 0 322 #define GC_BASE__INST1_SEG1 0 323 #define GC_BASE__INST1_SEG2 0 324 #define GC_BASE__INST1_SEG3 0 325 #define GC_BASE__INST1_SEG4 0 326 327 #define GC_BASE__INST2_SEG0 0 328 #define GC_BASE__INST2_SEG1 0 329 #define GC_BASE__INST2_SEG2 0 330 #define GC_BASE__INST2_SEG3 0 331 #define GC_BASE__INST2_SEG4 0 332 333 #define GC_BASE__INST3_SEG0 0 334 #define GC_BASE__INST3_SEG1 0 335 #define GC_BASE__INST3_SEG2 0 336 #define GC_BASE__INST3_SEG3 0 337 #define GC_BASE__INST3_SEG4 0 338 339 #define GC_BASE__INST4_SEG0 0 340 #define GC_BASE__INST4_SEG1 0 341 #define GC_BASE__INST4_SEG2 0 342 #define GC_BASE__INST4_SEG3 0 343 #define GC_BASE__INST4_SEG4 0 344 345 #define GC_BASE__INST5_SEG0 0 346 #define GC_BASE__INST5_SEG1 0 347 #define GC_BASE__INST5_SEG2 0 348 #define GC_BASE__INST5_SEG3 0 349 #define GC_BASE__INST5_SEG4 0 350 351 #define HDP_BASE__INST0_SEG0 0x00000F20 352 #define HDP_BASE__INST0_SEG1 0 353 #define HDP_BASE__INST0_SEG2 0 354 #define HDP_BASE__INST0_SEG3 0 355 #define HDP_BASE__INST0_SEG4 0 356 357 #define HDP_BASE__INST1_SEG0 0 358 #define HDP_BASE__INST1_SEG1 0 359 #define HDP_BASE__INST1_SEG2 0 360 #define HDP_BASE__INST1_SEG3 0 361 #define HDP_BASE__INST1_SEG4 0 362 363 #define HDP_BASE__INST2_SEG0 0 364 #define HDP_BASE__INST2_SEG1 0 365 #define HDP_BASE__INST2_SEG2 0 366 #define HDP_BASE__INST2_SEG3 0 367 #define HDP_BASE__INST2_SEG4 0 368 369 #define HDP_BASE__INST3_SEG0 0 370 #define HDP_BASE__INST3_SEG1 0 371 #define HDP_BASE__INST3_SEG2 0 372 #define HDP_BASE__INST3_SEG3 0 373 #define HDP_BASE__INST3_SEG4 0 374 375 #define HDP_BASE__INST4_SEG0 0 376 #define HDP_BASE__INST4_SEG1 0 377 #define HDP_BASE__INST4_SEG2 0 378 #define HDP_BASE__INST4_SEG3 0 379 #define HDP_BASE__INST4_SEG4 0 380 381 #define HDP_BASE__INST5_SEG0 0 382 #define HDP_BASE__INST5_SEG1 0 383 #define HDP_BASE__INST5_SEG2 0 384 #define HDP_BASE__INST5_SEG3 0 385 #define HDP_BASE__INST5_SEG4 0 386 387 #define MMHUB_BASE__INST0_SEG0 0x0001A000 388 #define MMHUB_BASE__INST0_SEG1 0 389 #define MMHUB_BASE__INST0_SEG2 0 390 #define MMHUB_BASE__INST0_SEG3 0 391 #define MMHUB_BASE__INST0_SEG4 0 392 393 #define MMHUB_BASE__INST1_SEG0 0 394 #define MMHUB_BASE__INST1_SEG1 0 395 #define MMHUB_BASE__INST1_SEG2 0 396 #define MMHUB_BASE__INST1_SEG3 0 397 #define MMHUB_BASE__INST1_SEG4 0 398 399 #define MMHUB_BASE__INST2_SEG0 0 400 #define MMHUB_BASE__INST2_SEG1 0 401 #define MMHUB_BASE__INST2_SEG2 0 402 #define MMHUB_BASE__INST2_SEG3 0 403 #define MMHUB_BASE__INST2_SEG4 0 404 405 #define MMHUB_BASE__INST3_SEG0 0 406 #define MMHUB_BASE__INST3_SEG1 0 407 #define MMHUB_BASE__INST3_SEG2 0 408 #define MMHUB_BASE__INST3_SEG3 0 409 #define MMHUB_BASE__INST3_SEG4 0 410 411 #define MMHUB_BASE__INST4_SEG0 0 412 #define MMHUB_BASE__INST4_SEG1 0 413 #define MMHUB_BASE__INST4_SEG2 0 414 #define MMHUB_BASE__INST4_SEG3 0 415 #define MMHUB_BASE__INST4_SEG4 0 416 417 #define MMHUB_BASE__INST5_SEG0 0 418 #define MMHUB_BASE__INST5_SEG1 0 419 #define MMHUB_BASE__INST5_SEG2 0 420 #define MMHUB_BASE__INST5_SEG3 0 421 #define MMHUB_BASE__INST5_SEG4 0 422 423 #define MP0_BASE__INST0_SEG0 0x00016000 424 #define MP0_BASE__INST0_SEG1 0 425 #define MP0_BASE__INST0_SEG2 0 426 #define MP0_BASE__INST0_SEG3 0 427 #define MP0_BASE__INST0_SEG4 0 428 429 #define MP0_BASE__INST1_SEG0 0 430 #define MP0_BASE__INST1_SEG1 0 431 #define MP0_BASE__INST1_SEG2 0 432 #define MP0_BASE__INST1_SEG3 0 433 #define MP0_BASE__INST1_SEG4 0 434 435 #define MP0_BASE__INST2_SEG0 0 436 #define MP0_BASE__INST2_SEG1 0 437 #define MP0_BASE__INST2_SEG2 0 438 #define MP0_BASE__INST2_SEG3 0 439 #define MP0_BASE__INST2_SEG4 0 440 441 #define MP0_BASE__INST3_SEG0 0 442 #define MP0_BASE__INST3_SEG1 0 443 #define MP0_BASE__INST3_SEG2 0 444 #define MP0_BASE__INST3_SEG3 0 445 #define MP0_BASE__INST3_SEG4 0 446 447 #define MP0_BASE__INST4_SEG0 0 448 #define MP0_BASE__INST4_SEG1 0 449 #define MP0_BASE__INST4_SEG2 0 450 #define MP0_BASE__INST4_SEG3 0 451 #define MP0_BASE__INST4_SEG4 0 452 453 #define MP0_BASE__INST5_SEG0 0 454 #define MP0_BASE__INST5_SEG1 0 455 #define MP0_BASE__INST5_SEG2 0 456 #define MP0_BASE__INST5_SEG3 0 457 #define MP0_BASE__INST5_SEG4 0 458 459 #define MP1_BASE__INST0_SEG0 0x00016000 460 #define MP1_BASE__INST0_SEG1 0 461 #define MP1_BASE__INST0_SEG2 0 462 #define MP1_BASE__INST0_SEG3 0 463 #define MP1_BASE__INST0_SEG4 0 464 465 #define MP1_BASE__INST1_SEG0 0 466 #define MP1_BASE__INST1_SEG1 0 467 #define MP1_BASE__INST1_SEG2 0 468 #define MP1_BASE__INST1_SEG3 0 469 #define MP1_BASE__INST1_SEG4 0 470 471 #define MP1_BASE__INST2_SEG0 0 472 #define MP1_BASE__INST2_SEG1 0 473 #define MP1_BASE__INST2_SEG2 0 474 #define MP1_BASE__INST2_SEG3 0 475 #define MP1_BASE__INST2_SEG4 0 476 477 #define MP1_BASE__INST3_SEG0 0 478 #define MP1_BASE__INST3_SEG1 0 479 #define MP1_BASE__INST3_SEG2 0 480 #define MP1_BASE__INST3_SEG3 0 481 #define MP1_BASE__INST3_SEG4 0 482 483 #define MP1_BASE__INST4_SEG0 0 484 #define MP1_BASE__INST4_SEG1 0 485 #define MP1_BASE__INST4_SEG2 0 486 #define MP1_BASE__INST4_SEG3 0 487 #define MP1_BASE__INST4_SEG4 0 488 489 #define MP1_BASE__INST5_SEG0 0 490 #define MP1_BASE__INST5_SEG1 0 491 #define MP1_BASE__INST5_SEG2 0 492 #define MP1_BASE__INST5_SEG3 0 493 #define MP1_BASE__INST5_SEG4 0 494 495 #define NBIO_BASE__INST0_SEG0 0x00000000 496 #define NBIO_BASE__INST0_SEG1 0x00000014 497 #define NBIO_BASE__INST0_SEG2 0x00000D20 498 #define NBIO_BASE__INST0_SEG3 0x00010400 499 #define NBIO_BASE__INST0_SEG4 0 500 501 #define NBIO_BASE__INST1_SEG0 0 502 #define NBIO_BASE__INST1_SEG1 0 503 #define NBIO_BASE__INST1_SEG2 0 504 #define NBIO_BASE__INST1_SEG3 0 505 #define NBIO_BASE__INST1_SEG4 0 506 507 #define NBIO_BASE__INST2_SEG0 0 508 #define NBIO_BASE__INST2_SEG1 0 509 #define NBIO_BASE__INST2_SEG2 0 510 #define NBIO_BASE__INST2_SEG3 0 511 #define NBIO_BASE__INST2_SEG4 0 512 513 #define NBIO_BASE__INST3_SEG0 0 514 #define NBIO_BASE__INST3_SEG1 0 515 #define NBIO_BASE__INST3_SEG2 0 516 #define NBIO_BASE__INST3_SEG3 0 517 #define NBIO_BASE__INST3_SEG4 0 518 519 #define NBIO_BASE__INST4_SEG0 0 520 #define NBIO_BASE__INST4_SEG1 0 521 #define NBIO_BASE__INST4_SEG2 0 522 #define NBIO_BASE__INST4_SEG3 0 523 #define NBIO_BASE__INST4_SEG4 0 524 525 #define NBIO_BASE__INST5_SEG0 0 526 #define NBIO_BASE__INST5_SEG1 0 527 #define NBIO_BASE__INST5_SEG2 0 528 #define NBIO_BASE__INST5_SEG3 0 529 #define NBIO_BASE__INST5_SEG4 0 530 531 #define OSSSYS_BASE__INST0_SEG0 0x000010A0 532 #define OSSSYS_BASE__INST0_SEG1 0 533 #define OSSSYS_BASE__INST0_SEG2 0 534 #define OSSSYS_BASE__INST0_SEG3 0 535 #define OSSSYS_BASE__INST0_SEG4 0 536 537 #define OSSSYS_BASE__INST1_SEG0 0 538 #define OSSSYS_BASE__INST1_SEG1 0 539 #define OSSSYS_BASE__INST1_SEG2 0 540 #define OSSSYS_BASE__INST1_SEG3 0 541 #define OSSSYS_BASE__INST1_SEG4 0 542 543 #define OSSSYS_BASE__INST2_SEG0 0 544 #define OSSSYS_BASE__INST2_SEG1 0 545 #define OSSSYS_BASE__INST2_SEG2 0 546 #define OSSSYS_BASE__INST2_SEG3 0 547 #define OSSSYS_BASE__INST2_SEG4 0 548 549 #define OSSSYS_BASE__INST3_SEG0 0 550 #define OSSSYS_BASE__INST3_SEG1 0 551 #define OSSSYS_BASE__INST3_SEG2 0 552 #define OSSSYS_BASE__INST3_SEG3 0 553 #define OSSSYS_BASE__INST3_SEG4 0 554 555 #define OSSSYS_BASE__INST4_SEG0 0 556 #define OSSSYS_BASE__INST4_SEG1 0 557 #define OSSSYS_BASE__INST4_SEG2 0 558 #define OSSSYS_BASE__INST4_SEG3 0 559 #define OSSSYS_BASE__INST4_SEG4 0 560 561 #define OSSSYS_BASE__INST5_SEG0 0 562 #define OSSSYS_BASE__INST5_SEG1 0 563 #define OSSSYS_BASE__INST5_SEG2 0 564 #define OSSSYS_BASE__INST5_SEG3 0 565 #define OSSSYS_BASE__INST5_SEG4 0 566 567 #define SMUIO_BASE__INST0_SEG0 0x00016800 568 #define SMUIO_BASE__INST0_SEG1 0x00016A00 569 #define SMUIO_BASE__INST0_SEG2 0 570 #define SMUIO_BASE__INST0_SEG3 0 571 #define SMUIO_BASE__INST0_SEG4 0 572 573 #define SMUIO_BASE__INST1_SEG0 0 574 #define SMUIO_BASE__INST1_SEG1 0 575 #define SMUIO_BASE__INST1_SEG2 0 576 #define SMUIO_BASE__INST1_SEG3 0 577 #define SMUIO_BASE__INST1_SEG4 0 578 579 #define SMUIO_BASE__INST2_SEG0 0 580 #define SMUIO_BASE__INST2_SEG1 0 581 #define SMUIO_BASE__INST2_SEG2 0 582 #define SMUIO_BASE__INST2_SEG3 0 583 #define SMUIO_BASE__INST2_SEG4 0 584 585 #define SMUIO_BASE__INST3_SEG0 0 586 #define SMUIO_BASE__INST3_SEG1 0 587 #define SMUIO_BASE__INST3_SEG2 0 588 #define SMUIO_BASE__INST3_SEG3 0 589 #define SMUIO_BASE__INST3_SEG4 0 590 591 #define SMUIO_BASE__INST4_SEG0 0 592 #define SMUIO_BASE__INST4_SEG1 0 593 #define SMUIO_BASE__INST4_SEG2 0 594 #define SMUIO_BASE__INST4_SEG3 0 595 #define SMUIO_BASE__INST4_SEG4 0 596 597 #define SMUIO_BASE__INST5_SEG0 0 598 #define SMUIO_BASE__INST5_SEG1 0 599 #define SMUIO_BASE__INST5_SEG2 0 600 #define SMUIO_BASE__INST5_SEG3 0 601 #define SMUIO_BASE__INST5_SEG4 0 602 603 #define THM_BASE__INST0_SEG0 0x00016600 604 #define THM_BASE__INST0_SEG1 0 605 #define THM_BASE__INST0_SEG2 0 606 #define THM_BASE__INST0_SEG3 0 607 #define THM_BASE__INST0_SEG4 0 608 609 #define THM_BASE__INST1_SEG0 0 610 #define THM_BASE__INST1_SEG1 0 611 #define THM_BASE__INST1_SEG2 0 612 #define THM_BASE__INST1_SEG3 0 613 #define THM_BASE__INST1_SEG4 0 614 615 #define THM_BASE__INST2_SEG0 0 616 #define THM_BASE__INST2_SEG1 0 617 #define THM_BASE__INST2_SEG2 0 618 #define THM_BASE__INST2_SEG3 0 619 #define THM_BASE__INST2_SEG4 0 620 621 #define THM_BASE__INST3_SEG0 0 622 #define THM_BASE__INST3_SEG1 0 623 #define THM_BASE__INST3_SEG2 0 624 #define THM_BASE__INST3_SEG3 0 625 #define THM_BASE__INST3_SEG4 0 626 627 #define THM_BASE__INST4_SEG0 0 628 #define THM_BASE__INST4_SEG1 0 629 #define THM_BASE__INST4_SEG2 0 630 #define THM_BASE__INST4_SEG3 0 631 #define THM_BASE__INST4_SEG4 0 632 633 #define THM_BASE__INST5_SEG0 0 634 #define THM_BASE__INST5_SEG1 0 635 #define THM_BASE__INST5_SEG2 0 636 #define THM_BASE__INST5_SEG3 0 637 #define THM_BASE__INST5_SEG4 0 638 639 #define UMC0_BASE__INST0_SEG0 0x00014000 640 #define UMC0_BASE__INST0_SEG1 0 641 #define UMC0_BASE__INST0_SEG2 0 642 #define UMC0_BASE__INST0_SEG3 0 643 #define UMC0_BASE__INST0_SEG4 0 644 645 #define UMC0_BASE__INST1_SEG0 0 646 #define UMC0_BASE__INST1_SEG1 0 647 #define UMC0_BASE__INST1_SEG2 0 648 #define UMC0_BASE__INST1_SEG3 0 649 #define UMC0_BASE__INST1_SEG4 0 650 651 #define UMC0_BASE__INST2_SEG0 0 652 #define UMC0_BASE__INST2_SEG1 0 653 #define UMC0_BASE__INST2_SEG2 0 654 #define UMC0_BASE__INST2_SEG3 0 655 #define UMC0_BASE__INST2_SEG4 0 656 657 #define UMC0_BASE__INST3_SEG0 0 658 #define UMC0_BASE__INST3_SEG1 0 659 #define UMC0_BASE__INST3_SEG2 0 660 #define UMC0_BASE__INST3_SEG3 0 661 #define UMC0_BASE__INST3_SEG4 0 662 663 #define UMC0_BASE__INST4_SEG0 0 664 #define UMC0_BASE__INST4_SEG1 0 665 #define UMC0_BASE__INST4_SEG2 0 666 #define UMC0_BASE__INST4_SEG3 0 667 #define UMC0_BASE__INST4_SEG4 0 668 669 #define UMC0_BASE__INST5_SEG0 0 670 #define UMC0_BASE__INST5_SEG1 0 671 #define UMC0_BASE__INST5_SEG2 0 672 #define UMC0_BASE__INST5_SEG3 0 673 #define UMC0_BASE__INST5_SEG4 0 674 675 #define UVD0_BASE__INST0_SEG0 0x00007800 676 #define UVD0_BASE__INST0_SEG1 0x00007E00 677 #define UVD0_BASE__INST0_SEG2 0 678 #define UVD0_BASE__INST0_SEG3 0 679 #define UVD0_BASE__INST0_SEG4 0 680 681 #define UVD0_BASE__INST1_SEG0 0 682 #define UVD0_BASE__INST1_SEG1 0 683 #define UVD0_BASE__INST1_SEG2 0 684 #define UVD0_BASE__INST1_SEG3 0 685 #define UVD0_BASE__INST1_SEG4 0 686 687 #define UVD0_BASE__INST2_SEG0 0 688 #define UVD0_BASE__INST2_SEG1 0 689 #define UVD0_BASE__INST2_SEG2 0 690 #define UVD0_BASE__INST2_SEG3 0 691 #define UVD0_BASE__INST2_SEG4 0 692 693 #define UVD0_BASE__INST3_SEG0 0 694 #define UVD0_BASE__INST3_SEG1 0 695 #define UVD0_BASE__INST3_SEG2 0 696 #define UVD0_BASE__INST3_SEG3 0 697 #define UVD0_BASE__INST3_SEG4 0 698 699 #define UVD0_BASE__INST4_SEG0 0 700 #define UVD0_BASE__INST4_SEG1 0 701 #define UVD0_BASE__INST4_SEG2 0 702 #define UVD0_BASE__INST4_SEG3 0 703 #define UVD0_BASE__INST4_SEG4 0 704 705 #define UVD0_BASE__INST5_SEG0 0 706 #define UVD0_BASE__INST5_SEG1 0 707 #define UVD0_BASE__INST5_SEG2 0 708 #define UVD0_BASE__INST5_SEG3 0 709 #define UVD0_BASE__INST5_SEG4 0 710 711 #endif 712 713