1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_TV_REGS_H__ 7 #define __INTEL_TV_REGS_H__ 8 9 #include "intel_display_reg_defs.h" 10 11 /* TV port control */ 12 #define TV_CTL _MMIO(0x68000) 13 /* Enables the TV encoder */ 14 # define TV_ENC_ENABLE (1 << 31) 15 /* Sources the TV encoder input from pipe B instead of A. */ 16 # define TV_ENC_PIPE_SEL_SHIFT 30 17 # define TV_ENC_PIPE_SEL_MASK (1 << 30) 18 # define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30) 19 /* Outputs composite video (DAC A only) */ 20 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 21 /* Outputs SVideo video (DAC B/C) */ 22 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 23 /* Outputs Component video (DAC A/B/C) */ 24 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 25 /* Outputs Composite and SVideo (DAC A/B/C) */ 26 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 27 # define TV_TRILEVEL_SYNC (1 << 21) 28 /* Enables slow sync generation (945GM only) */ 29 # define TV_SLOW_SYNC (1 << 20) 30 /* Selects 4x oversampling for 480i and 576p */ 31 # define TV_OVERSAMPLE_4X (0 << 18) 32 /* Selects 2x oversampling for 720p and 1080i */ 33 # define TV_OVERSAMPLE_2X (1 << 18) 34 /* Selects no oversampling for 1080p */ 35 # define TV_OVERSAMPLE_NONE (2 << 18) 36 /* Selects 8x oversampling */ 37 # define TV_OVERSAMPLE_8X (3 << 18) 38 # define TV_OVERSAMPLE_MASK (3 << 18) 39 /* Selects progressive mode rather than interlaced */ 40 # define TV_PROGRESSIVE (1 << 17) 41 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 42 # define TV_PAL_BURST (1 << 16) 43 /* Field for setting delay of Y compared to C */ 44 # define TV_YC_SKEW_MASK (7 << 12) 45 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 46 # define TV_ENC_SDP_FIX (1 << 11) 47 /* 48 * Enables a fix for the 915GM only. 49 * 50 * Not sure what it does. 51 */ 52 # define TV_ENC_C0_FIX (1 << 10) 53 /* Bits that must be preserved by software */ 54 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 55 # define TV_FUSE_STATE_MASK (3 << 4) 56 /* Read-only state that reports all features enabled */ 57 # define TV_FUSE_STATE_ENABLED (0 << 4) 58 /* Read-only state that reports that Macrovision is disabled in hardware*/ 59 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 60 /* Read-only state that reports that TV-out is disabled in hardware. */ 61 # define TV_FUSE_STATE_DISABLED (2 << 4) 62 /* Normal operation */ 63 # define TV_TEST_MODE_NORMAL (0 << 0) 64 /* Encoder test pattern 1 - combo pattern */ 65 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 66 /* Encoder test pattern 2 - full screen vertical 75% color bars */ 67 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 68 /* Encoder test pattern 3 - full screen horizontal 75% color bars */ 69 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 70 /* Encoder test pattern 4 - random noise */ 71 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 72 /* Encoder test pattern 5 - linear color ramps */ 73 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 74 /* 75 * This test mode forces the DACs to 50% of full output. 76 * 77 * This is used for load detection in combination with TVDAC_SENSE_MASK 78 */ 79 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 80 # define TV_TEST_MODE_MASK (7 << 0) 81 82 #define TV_DAC _MMIO(0x68004) 83 # define TV_DAC_SAVE 0x00ffff00 84 /* 85 * Reports that DAC state change logic has reported change (RO). 86 * 87 * This gets cleared when TV_DAC_STATE_EN is cleared 88 */ 89 # define TVDAC_STATE_CHG (1 << 31) 90 # define TVDAC_SENSE_MASK (7 << 28) 91 /* Reports that DAC A voltage is above the detect threshold */ 92 # define TVDAC_A_SENSE (1 << 30) 93 /* Reports that DAC B voltage is above the detect threshold */ 94 # define TVDAC_B_SENSE (1 << 29) 95 /* Reports that DAC C voltage is above the detect threshold */ 96 # define TVDAC_C_SENSE (1 << 28) 97 /* 98 * Enables DAC state detection logic, for load-based TV detection. 99 * 100 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 101 * to off, for load detection to work. 102 */ 103 # define TVDAC_STATE_CHG_EN (1 << 27) 104 /* Sets the DAC A sense value to high */ 105 # define TVDAC_A_SENSE_CTL (1 << 26) 106 /* Sets the DAC B sense value to high */ 107 # define TVDAC_B_SENSE_CTL (1 << 25) 108 /* Sets the DAC C sense value to high */ 109 # define TVDAC_C_SENSE_CTL (1 << 24) 110 /* Overrides the ENC_ENABLE and DAC voltage levels */ 111 # define DAC_CTL_OVERRIDE (1 << 7) 112 /* Sets the slew rate. Must be preserved in software */ 113 # define ENC_TVDAC_SLEW_FAST (1 << 6) 114 # define DAC_A_1_3_V (0 << 4) 115 # define DAC_A_1_1_V (1 << 4) 116 # define DAC_A_0_7_V (2 << 4) 117 # define DAC_A_MASK (3 << 4) 118 # define DAC_B_1_3_V (0 << 2) 119 # define DAC_B_1_1_V (1 << 2) 120 # define DAC_B_0_7_V (2 << 2) 121 # define DAC_B_MASK (3 << 2) 122 # define DAC_C_1_3_V (0 << 0) 123 # define DAC_C_1_1_V (1 << 0) 124 # define DAC_C_0_7_V (2 << 0) 125 # define DAC_C_MASK (3 << 0) 126 127 /* 128 * CSC coefficients are stored in a floating point format with 9 bits of 129 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 130 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 131 * -1 (0x3) being the only legal negative value. 132 */ 133 #define TV_CSC_Y _MMIO(0x68010) 134 # define TV_RY_MASK 0x07ff0000 135 # define TV_RY_SHIFT 16 136 # define TV_GY_MASK 0x00000fff 137 # define TV_GY_SHIFT 0 138 139 #define TV_CSC_Y2 _MMIO(0x68014) 140 # define TV_BY_MASK 0x07ff0000 141 # define TV_BY_SHIFT 16 142 /* 143 * Y attenuation for component video. 144 * 145 * Stored in 1.9 fixed point. 146 */ 147 # define TV_AY_MASK 0x000003ff 148 # define TV_AY_SHIFT 0 149 150 #define TV_CSC_U _MMIO(0x68018) 151 # define TV_RU_MASK 0x07ff0000 152 # define TV_RU_SHIFT 16 153 # define TV_GU_MASK 0x000007ff 154 # define TV_GU_SHIFT 0 155 156 #define TV_CSC_U2 _MMIO(0x6801c) 157 # define TV_BU_MASK 0x07ff0000 158 # define TV_BU_SHIFT 16 159 /* 160 * U attenuation for component video. 161 * 162 * Stored in 1.9 fixed point. 163 */ 164 # define TV_AU_MASK 0x000003ff 165 # define TV_AU_SHIFT 0 166 167 #define TV_CSC_V _MMIO(0x68020) 168 # define TV_RV_MASK 0x0fff0000 169 # define TV_RV_SHIFT 16 170 # define TV_GV_MASK 0x000007ff 171 # define TV_GV_SHIFT 0 172 173 #define TV_CSC_V2 _MMIO(0x68024) 174 # define TV_BV_MASK 0x07ff0000 175 # define TV_BV_SHIFT 16 176 /* 177 * V attenuation for component video. 178 * 179 * Stored in 1.9 fixed point. 180 */ 181 # define TV_AV_MASK 0x000007ff 182 # define TV_AV_SHIFT 0 183 184 #define TV_CLR_KNOBS _MMIO(0x68028) 185 /* 2s-complement brightness adjustment */ 186 # define TV_BRIGHTNESS_MASK 0xff000000 187 # define TV_BRIGHTNESS_SHIFT 24 188 /* Contrast adjustment, as a 2.6 unsigned floating point number */ 189 # define TV_CONTRAST_MASK 0x00ff0000 190 # define TV_CONTRAST_SHIFT 16 191 /* Saturation adjustment, as a 2.6 unsigned floating point number */ 192 # define TV_SATURATION_MASK 0x0000ff00 193 # define TV_SATURATION_SHIFT 8 194 /* Hue adjustment, as an integer phase angle in degrees */ 195 # define TV_HUE_MASK 0x000000ff 196 # define TV_HUE_SHIFT 0 197 198 #define TV_CLR_LEVEL _MMIO(0x6802c) 199 /* Controls the DAC level for black */ 200 # define TV_BLACK_LEVEL_MASK 0x01ff0000 201 # define TV_BLACK_LEVEL_SHIFT 16 202 /* Controls the DAC level for blanking */ 203 # define TV_BLANK_LEVEL_MASK 0x000001ff 204 # define TV_BLANK_LEVEL_SHIFT 0 205 206 #define TV_H_CTL_1 _MMIO(0x68030) 207 /* Number of pixels in the hsync. */ 208 # define TV_HSYNC_END_MASK 0x1fff0000 209 # define TV_HSYNC_END_SHIFT 16 210 /* Total number of pixels minus one in the line (display and blanking). */ 211 # define TV_HTOTAL_MASK 0x00001fff 212 # define TV_HTOTAL_SHIFT 0 213 214 #define TV_H_CTL_2 _MMIO(0x68034) 215 /* Enables the colorburst (needed for non-component color) */ 216 # define TV_BURST_ENA (1 << 31) 217 /* Offset of the colorburst from the start of hsync, in pixels minus one. */ 218 # define TV_HBURST_START_SHIFT 16 219 # define TV_HBURST_START_MASK 0x1fff0000 220 /* Length of the colorburst */ 221 # define TV_HBURST_LEN_SHIFT 0 222 # define TV_HBURST_LEN_MASK 0x0001fff 223 224 #define TV_H_CTL_3 _MMIO(0x68038) 225 /* End of hblank, measured in pixels minus one from start of hsync */ 226 # define TV_HBLANK_END_SHIFT 16 227 # define TV_HBLANK_END_MASK 0x1fff0000 228 /* Start of hblank, measured in pixels minus one from start of hsync */ 229 # define TV_HBLANK_START_SHIFT 0 230 # define TV_HBLANK_START_MASK 0x0001fff 231 232 #define TV_V_CTL_1 _MMIO(0x6803c) 233 /* XXX */ 234 # define TV_NBR_END_SHIFT 16 235 # define TV_NBR_END_MASK 0x07ff0000 236 /* XXX */ 237 # define TV_VI_END_F1_SHIFT 8 238 # define TV_VI_END_F1_MASK 0x00003f00 239 /* XXX */ 240 # define TV_VI_END_F2_SHIFT 0 241 # define TV_VI_END_F2_MASK 0x0000003f 242 243 #define TV_V_CTL_2 _MMIO(0x68040) 244 /* Length of vsync, in half lines */ 245 # define TV_VSYNC_LEN_MASK 0x07ff0000 246 # define TV_VSYNC_LEN_SHIFT 16 247 /* Offset of the start of vsync in field 1, measured in one less than the 248 * number of half lines. 249 */ 250 # define TV_VSYNC_START_F1_MASK 0x00007f00 251 # define TV_VSYNC_START_F1_SHIFT 8 252 /* 253 * Offset of the start of vsync in field 2, measured in one less than the 254 * number of half lines. 255 */ 256 # define TV_VSYNC_START_F2_MASK 0x0000007f 257 # define TV_VSYNC_START_F2_SHIFT 0 258 259 #define TV_V_CTL_3 _MMIO(0x68044) 260 /* Enables generation of the equalization signal */ 261 # define TV_EQUAL_ENA (1 << 31) 262 /* Length of vsync, in half lines */ 263 # define TV_VEQ_LEN_MASK 0x007f0000 264 # define TV_VEQ_LEN_SHIFT 16 265 /* Offset of the start of equalization in field 1, measured in one less than 266 * the number of half lines. 267 */ 268 # define TV_VEQ_START_F1_MASK 0x0007f00 269 # define TV_VEQ_START_F1_SHIFT 8 270 /* 271 * Offset of the start of equalization in field 2, measured in one less than 272 * the number of half lines. 273 */ 274 # define TV_VEQ_START_F2_MASK 0x000007f 275 # define TV_VEQ_START_F2_SHIFT 0 276 277 #define TV_V_CTL_4 _MMIO(0x68048) 278 /* 279 * Offset to start of vertical colorburst, measured in one less than the 280 * number of lines from vertical start. 281 */ 282 # define TV_VBURST_START_F1_MASK 0x003f0000 283 # define TV_VBURST_START_F1_SHIFT 16 284 /* 285 * Offset to the end of vertical colorburst, measured in one less than the 286 * number of lines from the start of NBR. 287 */ 288 # define TV_VBURST_END_F1_MASK 0x000000ff 289 # define TV_VBURST_END_F1_SHIFT 0 290 291 #define TV_V_CTL_5 _MMIO(0x6804c) 292 /* 293 * Offset to start of vertical colorburst, measured in one less than the 294 * number of lines from vertical start. 295 */ 296 # define TV_VBURST_START_F2_MASK 0x003f0000 297 # define TV_VBURST_START_F2_SHIFT 16 298 /* 299 * Offset to the end of vertical colorburst, measured in one less than the 300 * number of lines from the start of NBR. 301 */ 302 # define TV_VBURST_END_F2_MASK 0x000000ff 303 # define TV_VBURST_END_F2_SHIFT 0 304 305 #define TV_V_CTL_6 _MMIO(0x68050) 306 /* 307 * Offset to start of vertical colorburst, measured in one less than the 308 * number of lines from vertical start. 309 */ 310 # define TV_VBURST_START_F3_MASK 0x003f0000 311 # define TV_VBURST_START_F3_SHIFT 16 312 /* 313 * Offset to the end of vertical colorburst, measured in one less than the 314 * number of lines from the start of NBR. 315 */ 316 # define TV_VBURST_END_F3_MASK 0x000000ff 317 # define TV_VBURST_END_F3_SHIFT 0 318 319 #define TV_V_CTL_7 _MMIO(0x68054) 320 /* 321 * Offset to start of vertical colorburst, measured in one less than the 322 * number of lines from vertical start. 323 */ 324 # define TV_VBURST_START_F4_MASK 0x003f0000 325 # define TV_VBURST_START_F4_SHIFT 16 326 /* 327 * Offset to the end of vertical colorburst, measured in one less than the 328 * number of lines from the start of NBR. 329 */ 330 # define TV_VBURST_END_F4_MASK 0x000000ff 331 # define TV_VBURST_END_F4_SHIFT 0 332 333 #define TV_SC_CTL_1 _MMIO(0x68060) 334 /* Turns on the first subcarrier phase generation DDA */ 335 # define TV_SC_DDA1_EN (1 << 31) 336 /* Turns on the first subcarrier phase generation DDA */ 337 # define TV_SC_DDA2_EN (1 << 30) 338 /* Turns on the first subcarrier phase generation DDA */ 339 # define TV_SC_DDA3_EN (1 << 29) 340 /* Sets the subcarrier DDA to reset frequency every other field */ 341 # define TV_SC_RESET_EVERY_2 (0 << 24) 342 /* Sets the subcarrier DDA to reset frequency every fourth field */ 343 # define TV_SC_RESET_EVERY_4 (1 << 24) 344 /* Sets the subcarrier DDA to reset frequency every eighth field */ 345 # define TV_SC_RESET_EVERY_8 (2 << 24) 346 /* Sets the subcarrier DDA to never reset the frequency */ 347 # define TV_SC_RESET_NEVER (3 << 24) 348 /* Sets the peak amplitude of the colorburst.*/ 349 # define TV_BURST_LEVEL_MASK 0x00ff0000 350 # define TV_BURST_LEVEL_SHIFT 16 351 /* Sets the increment of the first subcarrier phase generation DDA */ 352 # define TV_SCDDA1_INC_MASK 0x00000fff 353 # define TV_SCDDA1_INC_SHIFT 0 354 355 #define TV_SC_CTL_2 _MMIO(0x68064) 356 /* Sets the rollover for the second subcarrier phase generation DDA */ 357 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 358 # define TV_SCDDA2_SIZE_SHIFT 16 359 /* Sets the increent of the second subcarrier phase generation DDA */ 360 # define TV_SCDDA2_INC_MASK 0x00007fff 361 # define TV_SCDDA2_INC_SHIFT 0 362 363 #define TV_SC_CTL_3 _MMIO(0x68068) 364 /* Sets the rollover for the third subcarrier phase generation DDA */ 365 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 366 # define TV_SCDDA3_SIZE_SHIFT 16 367 /* Sets the increent of the third subcarrier phase generation DDA */ 368 # define TV_SCDDA3_INC_MASK 0x00007fff 369 # define TV_SCDDA3_INC_SHIFT 0 370 371 #define TV_WIN_POS _MMIO(0x68070) 372 /* X coordinate of the display from the start of horizontal active */ 373 # define TV_XPOS_MASK 0x1fff0000 374 # define TV_XPOS_SHIFT 16 375 /* Y coordinate of the display from the start of vertical active (NBR) */ 376 # define TV_YPOS_MASK 0x00000fff 377 # define TV_YPOS_SHIFT 0 378 379 #define TV_WIN_SIZE _MMIO(0x68074) 380 /* Horizontal size of the display window, measured in pixels*/ 381 # define TV_XSIZE_MASK 0x1fff0000 382 # define TV_XSIZE_SHIFT 16 383 /* 384 * Vertical size of the display window, measured in pixels. 385 * 386 * Must be even for interlaced modes. 387 */ 388 # define TV_YSIZE_MASK 0x00000fff 389 # define TV_YSIZE_SHIFT 0 390 391 #define TV_FILTER_CTL_1 _MMIO(0x68080) 392 /* 393 * Enables automatic scaling calculation. 394 * 395 * If set, the rest of the registers are ignored, and the calculated values can 396 * be read back from the register. 397 */ 398 # define TV_AUTO_SCALE (1 << 31) 399 /* 400 * Disables the vertical filter. 401 * 402 * This is required on modes more than 1024 pixels wide */ 403 # define TV_V_FILTER_BYPASS (1 << 29) 404 /* Enables adaptive vertical filtering */ 405 # define TV_VADAPT (1 << 28) 406 # define TV_VADAPT_MODE_MASK (3 << 26) 407 /* Selects the least adaptive vertical filtering mode */ 408 # define TV_VADAPT_MODE_LEAST (0 << 26) 409 /* Selects the moderately adaptive vertical filtering mode */ 410 # define TV_VADAPT_MODE_MODERATE (1 << 26) 411 /* Selects the most adaptive vertical filtering mode */ 412 # define TV_VADAPT_MODE_MOST (3 << 26) 413 /* 414 * Sets the horizontal scaling factor. 415 * 416 * This should be the fractional part of the horizontal scaling factor divided 417 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 418 * 419 * (src width - 1) / ((oversample * dest width) - 1) 420 */ 421 # define TV_HSCALE_FRAC_MASK 0x00003fff 422 # define TV_HSCALE_FRAC_SHIFT 0 423 424 #define TV_FILTER_CTL_2 _MMIO(0x68084) 425 /* 426 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 427 * 428 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 429 */ 430 # define TV_VSCALE_INT_MASK 0x00038000 431 # define TV_VSCALE_INT_SHIFT 15 432 /* 433 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 434 * 435 * \sa TV_VSCALE_INT_MASK 436 */ 437 # define TV_VSCALE_FRAC_MASK 0x00007fff 438 # define TV_VSCALE_FRAC_SHIFT 0 439 440 #define TV_FILTER_CTL_3 _MMIO(0x68088) 441 /* 442 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 443 * 444 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 445 * 446 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 447 */ 448 # define TV_VSCALE_IP_INT_MASK 0x00038000 449 # define TV_VSCALE_IP_INT_SHIFT 15 450 /* 451 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 452 * 453 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 454 * 455 * \sa TV_VSCALE_IP_INT_MASK 456 */ 457 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 458 # define TV_VSCALE_IP_FRAC_SHIFT 0 459 460 #define TV_CC_CONTROL _MMIO(0x68090) 461 # define TV_CC_ENABLE (1 << 31) 462 /* 463 * Specifies which field to send the CC data in. 464 * 465 * CC data is usually sent in field 0. 466 */ 467 # define TV_CC_FID_MASK (1 << 27) 468 # define TV_CC_FID_SHIFT 27 469 /* Sets the horizontal position of the CC data. Usually 135. */ 470 # define TV_CC_HOFF_MASK 0x03ff0000 471 # define TV_CC_HOFF_SHIFT 16 472 /* Sets the vertical position of the CC data. Usually 21 */ 473 # define TV_CC_LINE_MASK 0x0000003f 474 # define TV_CC_LINE_SHIFT 0 475 476 #define TV_CC_DATA _MMIO(0x68094) 477 # define TV_CC_RDY (1 << 31) 478 /* Second word of CC data to be transmitted. */ 479 # define TV_CC_DATA_2_MASK 0x007f0000 480 # define TV_CC_DATA_2_SHIFT 16 481 /* First word of CC data to be transmitted. */ 482 # define TV_CC_DATA_1_MASK 0x0000007f 483 # define TV_CC_DATA_1_SHIFT 0 484 485 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */ 486 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */ 487 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */ 488 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */ 489 490 #endif /* __INTEL_TV_REGS_H__ */ 491