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Searched refs:TSB (Results 1 – 5 of 5) sorted by relevance

/linux/arch/sparc/include/asm/
H A Dtsb.h77 #define TSB_LOAD_QUAD(TSB, REG) \ argument
78 661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
81 ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
82 ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
85 #define TSB_LOAD_TAG_HIGH(TSB, REG) \ argument
86 661: lduwa [TSB] ASI_N, REG; \
89 lduwa [TSB] ASI_PHYS_USE_EC, REG; \
92 #define TSB_LOAD_TAG(TSB, REG) \ argument
93 661: ldxa [TSB] ASI_N, REG; \
96 ldxa [TSB] ASI_PHYS_USE_EC, REG; \
[all …]
/linux/arch/sparc/kernel/
H A Ddtlb_miss.S3 ldxa [%g0] ASI_DMMU_TSB_8KB_PTR, %g1 ! Get TSB 8K pointer
9 TSB_LOAD_QUAD(%g1, %g4) ! Load TSB entry
H A Ditlb_miss.S3 ldxa [%g0] ASI_IMMU_TSB_8KB_PTR, %g1 ! Get TSB 8K pointer
9 TSB_LOAD_QUAD(%g1, %g4) ! Load TSB entry
/linux/arch/arm64/
H A DKconfig883 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
889 Affected cores may fail to flush the trace data on a TSB instruction, when
893 Workaround is to issue two TSB consecutively on affected cores.
898 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
904 Affected cores may fail to flush the trace data on a TSB instruction, when
908 Workaround is to issue two TSB consecutively on affected cores.
979 Work around this in the driver by executing TSB CSYNC and DSB after collection
/linux/Documentation/arch/sparc/oradax/
H A Ddax-hv-api.txt237 …dresses used in the CCB must have translation entries present in either the TLB or a configured TSB
1121 must be present in either the TLB or an active TSB to be processed. The translation context for vir…
1231 or TSB contents. The submission may be retried after adding the required