Searched refs:TRCSSPCICRn (Results 1 – 3 of 3) sorted by relevance
| /linux/drivers/hwtracing/coresight/ |
| H A D | coresight-etm4x.h | 80 #define TRCSSPCICRn(n) (0x2C0 + (n * 4)) macro
377 CASE_##op((val), TRCSSPCICRn(0)) \
378 CASE_##op((val), TRCSSPCICRn(1)) \
379 CASE_##op((val), TRCSSPCICRn(2)) \
380 CASE_##op((val), TRCSSPCICRn(3)) \
381 CASE_##op((val), TRCSSPCICRn(4)) \
382 CASE_##op((val), TRCSSPCICRn(5)) \
383 CASE_##op((val), TRCSSPCICRn(6)) \
384 CASE_##op((val), TRCSSPCICRn(7)) \
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| H A D | coresight-etm4x-cfg.c | 83 } else if ((offset >= TRCSSCCRn(0)) && (offset <= TRCSSPCICRn(7))) { in etm4_cfg_map_reg_offset()
90 CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask); in etm4_cfg_map_reg_offset()
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| H A D | coresight-etm4x-core.c | 574 etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i)); in etm4_enable_hw()
1926 state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i)); in __etm4_cpu_save()
2056 etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i)); in __etm4_cpu_restore()
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